JPH11183524A - Sampling signal generating circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To conduct sampling with a high precision and with a stable high time-resolution without being influenced by the variation of a trigger signal, by generating a sampling signal of a frequency different slightly from the trigger signal, based on an independent reference signal being different from the trigger signal. SOLUTION: A first frequency mixer 11 mixes the frequencies of a trigger signal Ft and a first reference signal F1 asynchronous with this ahd having an arbitrary frequency, and a signal Ft +F1 is outputted through a first filer(HFP) 21. Next, a second frequency mixer 12 mixes the frequencies of this signal Ft +F1 . and a second frequency signal F2 (F1 +Δdf) synchronous with the first reference signal F1 and having a frequency different from the first reference signal F1 by a slight predetermined frequency Δf, causes it to pass a second filter(LPF) 22, and outputs a sampling signal Fs of a frequency Ft -Δf. Consequently, it becomes possible to perform sampling, maintaining synchronism between the trigger signal Ft and the sampling signal Fs , without being influenced by the frequency variation of the trigger signal Ft .

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a sampling circuit used for measuring a waveform of an optical device, a high-speed electric device, or the like by sampling. The sampling circuit controls high-resolution, high-accuracy, and stable sampling timing. The present invention relates to a sampling signal generation circuit.

[0002]

2. Description of the Related Art First, a sampling circuit using a sampling signal generating circuit will be described. FIG. 4 shows an outline of the sampling circuit. The sampling circuit includes a sampling signal generation circuit 71 and a sampling head 7.
2 in synchronization with a fixed point, ie, a trigger point, set for each cycle on the measured signal Fi waveform generated by the measured device 70 composed of
The trigger signal Ft having the same frequency as the above is input to the sampling signal generation circuit 71. The sampling signal generation circuit 71 is synchronized in phase with the trigger signal Ft.
The frequency is a small value set in advance to determine the sampling interval as compared with the trigger signal Ft,
Generally, a sampling signal Fs that differs by a value called Δf is generated. The sampling head 72 samples the input signal under test Fi at the timing of each cycle of the sampling signal Fs, and outputs the signal under test F
Output the sample waveform of i.

The difference Δf between the frequency of the trigger signal Ft and the frequency of the sampling signal Fs is one of the factors that determine the time resolution of sampling. The smaller the value of Δf, the higher the time resolution. At this time, when the frequency of the sampling signal Fs is lower than the frequency of the trigger signal Ft by Δf, the sampling head 72 sets 1 / Δf with the set trigger point on the waveform of the signal under measurement Fi as a base point.
Sampling at delayed sampling intervals,
A sample output Fo similar to the signal under test Fi is output. Thus, for example, when the sample output Fo is connected to the storage oscilloscope 73 to perform waveform observation,
The signal under measurement Fi can be measured by a method such as AD conversion and data processing. FIG. 5 shows the measured signal F at this time with respect to the trigger point and the sample point.
6 is a timing chart showing a relationship among i, a trigger signal Ft, a sampling signal Fs, and a sample output Fo.

Next, a conventional sampling signal generating circuit will be described with reference to FIG. As shown in FIG. 3, conventionally, a frequency divider 31, another frequency divider 32, a phase comparator 40, a loop filter 50, a voltage controlled oscillator 6
It is composed of a circuit called PLL consisting of zeros.

The frequency divider 31 divides the frequency of the trigger signal Ft by 1 / M and uses it as a reference signal input to the phase comparator 40.
The frequency divider 32 has a frequency F
s is divided by 1 / N and used as a comparison signal input to the phase comparator 40.

[0006] The phase comparator 40 compares the phases of the reference signal and the comparison signal, and outputs an error signal. The loop filter 50 is a kind of integrator, and the phase comparator 4
The error signal output from 0 is integrated and converted into an error voltage Vr. Voltage controlled oscillator 60 having error voltage Vr as input
Is controlled by feedback, the voltage controlled oscillator 60 outputs a sampling signal Fs that is in phase with the frequency of the trigger signal Ft.

At this time, the coefficient M of the frequency division ratio of the frequency divider 31
And the coefficient N of the frequency division ratio of the frequency divider 32, M = N
Assuming that the relationship of +1 (M and N are each an integer) is satisfied, from Ft × (1 / M) = Fs × (1 / N), Fs = Ft × (N / M) = Ft × (M−1 ) / M Therefore, Fs = Ft × (1-1 / M) That is, it is possible to obtain a sampling signal Fs synchronized with the trigger signal Ft and having a frequency lower by the trigger signal frequency Ft × (1 / M).

[0008]

In a conventional sampling signal generation circuit using a PLL circuit, the element Δf that determines the sampling interval is created by dividing the frequency of the trigger signal Ft. Therefore, from the relationship of Δf = trigger signal Ft × (1 / M), there is a problem that Δf itself fluctuates due to the fluctuation of the trigger signal.

On the other hand, the variable range of the trigger signal Ft is PLL
Determined by the lock range of the circuit, for example ± 10 kHz
And narrow.

It is an object of the present invention to provide a sampling signal generating circuit which eliminates the above-mentioned disadvantages and generates a highly accurate sampling signal having a stable high time resolution without being affected by the fluctuation of the trigger signal Ft. It is in.

[0011]

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, a first aspect of the present invention is to provide a trigger signal Ft and an external first reference having an arbitrary frequency which is asynchronous with the trigger signal Ft. Frequency conversion is performed between the signal F1 and the second reference signal F, whose phases are synchronized with the reference signal F1 and whose frequencies are different from each other by Δf, using a two-stage frequency mixer. Frequency conversion means for generating a sum and frequency difference signal, and signal extraction means for extracting only necessary signals by a filter from a plurality of signal groups generated by the frequency conversion means, synchronized with the phase of the trigger signal Ft, This is a sampling signal generation circuit that stably outputs a highly accurate sampling signal Fs.

A second aspect of the present invention for solving the above-mentioned problem is that, as an alternative to the above-mentioned second reference signal F2, the above-mentioned first reference signal F1 is input, and the phase of the first reference signal F1 is changed. By using the output signal F3 of the PLL circuit that generates a signal having a frequency different by Δf in synchronization with the above-described operation of the frequency conversion unit and the signal extraction unit, the output signal F3 is stable and synchronized with the phase of the trigger signal Ft. And a highly accurate sampling signal Fs.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described in the following examples.

[0014]

(Embodiment 1) FIG. 1 is a block diagram showing an embodiment of the present invention. The sampling signal generation circuit of the present invention includes a first frequency mixer 11, a first filter 21,
It comprises a second frequency mixer 12 and a second filter 22.

The first frequency mixer 11 outputs a trigger signal Ft.
And frequency conversion of the first reference signal F1 to generate a signal having a frequency of Ft ± F1. First
The filter 21 is a high-pass filter, to which the output Ft ± F1 of the first frequency mixer 11 is input and the frequency is Ft + F.
1 is output.

The second frequency mixer 12 includes a first filter 21
In synchronization with the output Ft + F1 and the first reference signal F1,
A second reference signal F2 (frequency F2 = F1 + Δf) higher than the reference signal F1 by Δf is frequency-mixed (Ft + F1).
A signal having a frequency of ± (F1 + Δf) is output. The second filter 22 is a low-pass filter, and the second frequency mixer 1
From the two output signals Ft + 2 × F1 + Δf and Ft−Δf, a component having a frequency of Ft−Δf is output as a sampling signal Fs.

As described above, the trigger signal Ft input to the present sampling signal generating circuit is frequency-converted twice by an arbitrary first reference signal F1 and second reference signal F2. Since there is a relationship between F1 and the second reference signal F2, the trigger signal Ft and the sampling signal F
The phase synchronization of s is maintained. Further, the accuracy of Δf, which is an element that determines the time resolution and accuracy of sampling, depends on the frequency accuracy of the first reference signal F1 and the second reference signal F2 independent of the trigger signal Ft.
It is not affected by the frequency fluctuation of t.

If the first reference signal F1 and the second reference signal F2 satisfy the condition that they are synchronized,
There is no restriction on each signal source, and its frequency selection range is also controlled by the two-stage frequency mixer using the trigger signal Ft.
Can be determined based on the performance of a filter capable of removing spurious generated when the frequency is mixed with the output signal so as not to affect the output sampling signal Fs. The waveform of the trigger signal Ft may be of any pulse frequency as long as it does not interfere with frequency mixing. In the case of a pulse, a filter for a fundamental wave may be inserted as desired.

(Embodiment 2) Regarding Embodiment 2 of the present invention,
This will be described with reference to the block diagram of FIG. The description of the same components as those in the first embodiment is omitted. Also, PL
Since the configuration and operation of the L circuit are the same as those described in the related art, the description is also omitted. As shown in FIG. 2, the second embodiment is different from the second reference signal F2 described in the first embodiment.
, The first reference signal F1 is input and the frequency divider 31
, A frequency divider 32, a phase comparator 40, a loop filter 50, and an output signal F3 of a PLL circuit composed of a voltage controlled oscillator 60.

The output signal F3 of the PLL circuit is different in frequency by Δf in synchronization with the phase of the first reference signal F1 by the same operation as described in the prior art.
By the same frequency conversion means and filter means as in the first embodiment, the phase of the trigger signal Ft is synchronized with that of the trigger signal Ft, so that a stable and accurate sampling signal Fs can be generated.

[0021]

As described above in detail, the present invention generates .DELTA.f for determining the time resolution of sampling based on a reference signal independent of the trigger signal, and therefore has a high time resolution and is stable. At the sampling interval
The effect of performing accurate sampling can be improved.

In the present invention, when the frequency of the trigger signal and the reference signal is 100 MHz and Δf = 20 Hz, the band of the filter can be widened, so that the signal to be measured is ± 10 MHz.
In the range, good sampling results could be obtained. Therefore, it is versatile and can be applied to sampling circuits such as high-speed pulse measuring instruments.

[Brief description of the drawings]

FIG. 1 is a first embodiment of a sampling signal generation circuit according to the present invention;
It is a block diagram of.

FIG. 2 is a second embodiment of a sampling signal generation circuit according to the present invention;
It is a block diagram of.

FIG. 3 is a block diagram of a conventional sampling signal generation circuit.

FIG. 4 is a block diagram of a sampling circuit.

FIG. 5 is a timing chart of a sampling circuit.

[Description of Signs] 11 First frequency mixer 12 Second frequency mixer 21 First filter 22 Second filter 31, 32 Divider 40 Phase comparator 50 Loop filter 60 Voltage controlled oscillator 70 Device under test 71 Sampling signal generation Circuit 72 Sampling head 73 Storage oscilloscope

Claims (2)

[Claims] 1. An input trigger signal (frequency signal)
And first frequency conversion means for mixing and outputting an asynchronous first reference signal independent of the trigger signal, and receiving the frequency-converted signal of the first frequency conversion means, A primary signal extracting means for outputting a sum or difference frequency signal; a frequency signal extracted by the primary signal extracting means;
Second frequency conversion means for synchronizing with the first reference signal and frequency-mixing and outputting again a second reference signal which differs from the first reference signal by a slight predetermined frequency; Receiving the signal from the means, and differing from the frequency of the trigger signal by a slight predetermined frequency,
A sampling signal generating circuit, comprising: a secondary signal extracting means for outputting a sampling signal. 2. The sampling signal generation circuit according to claim 1, wherein said second reference signal is a signal generated by a PLL circuit to which said first reference signal is input.