JPH1117744A - Error correction circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce errors by detecting an impossible pattern continuing '1', and correcting the pattern into correct pattern not continuing '1' when pulse wide modulation(PWM) demodulation is performed to the PWM modulated data string of code string not continuing '1'. SOLUTION: The output of a conventional PWM demodulation circuit 12 is inputted to a D-F/F 4 and during delay for four clocks, the pattern of '0110' is detected from the outputs of D-F/F 4, 5, 6 and 7. Then, data latched by the D-F/F 6 and 7 are forcedly turned on '0' by the next detected clock so that the error pattern of '0110' is error-corrected into correct pattern of '0000' and outputted.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an error correction circuit, and more particularly to a PWM (Pulse Width Modul).
an error correction circuit for demodulating data.

[0002]

2. Description of the Related Art PWM (Pulse Width Mod)
As shown in FIG. 5 for explaining the PWM modulation method, the data string is data obtained by modulating the original digital data string so that the value is inverted at "1" in the data string. Column.

When demodulating such PWM data into an original digital data string, an XOR (exclusive OR) gate 33 and DF / F (D-flip-flop) 31, 32 as shown in FIG. Demodulation can be performed by using a circuit configured.

FIG. 3 is an electric circuit diagram showing a configuration of a conventional PWM demodulation circuit, and FIG. 4 is a timing chart showing an operation example of the conventional PWM demodulation circuit.

The operation of the conventional PWM demodulation circuit will be described.

The input signal of the PWM waveform is synchronized by a clock signal and output from the DF / F 31. D-
The F / F 32 outputs a synchronized signal a and a signal b delayed by one clock by the clock signal. Further, an XOR logic of the signal a and the signal b is output from the XOR logic gate 33 as a signal before the original modulation.

[0007] By the way, the original data before being modulated into PWM is usually constituted by a code string in which "1" is not continuous. CD (Compact Disc) is EFM (Eight
toFourteen Modulation *: 8-
14 modulation) is a PW encoded data string.
M and recorded. The EFM code has a run length (bit length of 0 from 1 to 1) of 2 to 10, that is, a code of RLL (2, 10), and 1 does not continue. (Reference: "Optical Disk Technology Handbook" Chapter 4
Signal recording method Optoelectronic Industry and Technology Promotion Association, supervised by Nikkei McGraw-Hill, Inc.) Therefore, if the signal modulated by PWM is demodulated with pulsed noise as shown in FIG. There is a possibility that a portion where “1” continues is included.

The pattern of the portion "0110" in which "1" is continuous is obviously an error, and is originally "0000".
It is a pattern to become.

However, in the circuit of FIG. 3, such an error pattern due to noise is sent to the next block as it is.

In the case of a CD, the data is sent to the EFM code decoding circuit, and the decoded data naturally becomes erroneous data.

[0011]

If the original data sequence to be modulated by PWM is a discontinuous code sequence of "1", as described in the conventional example, the conventional PWM demodulation circuit will operate as described above. , A data string "0" that can be clearly identified as an error
110 "is transferred to the next decoding circuit as it is, resulting in erroneous data.

As a result, the number of errors included in the obtained data increases.

The error pattern “0110” is
This pattern is likely to occur when pulse-like noise is generated on a 0-level or 1-level signal in the PWM state. This is because the pulse-like noise has two transition points, and in PWM, the transition point represents 1, and when demodulated, it becomes "11".

Since "1" is not continuous in the original data string, the pattern "0110" including this pattern is clearly an error and should be "0000".

Sending a pattern that can be clearly determined to be an error and that can be corrected to the decoding circuit without correction reduces the reliability of data.

It is an object of the present invention that, when the original data is a discontinuous code of "1", when the code is demodulated into the original data of the PWM-modulated data, "1" may be continuous. An object of the present invention is to provide an error correction circuit which generates data with few errors by detecting a data string which is not present and converting the data string into a data string in which correct "1" is not continuous.

[0017]

In order to solve the above-mentioned problems, an error correction circuit according to the present invention, when demodulating PWM-modulated data to original data, sets an expected data sequence to "".
A bit string in which "1" is continuous is detected for a data string which is a code string constituted by a 1-bit width code in which "1" is not continuous. Means for converting into a bit string that is not continuous.

More specifically, a multi-stage D-flip-flop connected to the output terminal of the PWM demodulation circuit, a logic operation unit for detecting the output of the D-flip-flop of each stage,
An error correction control unit that controls an output of the D-flip-flop of each stage based on a logical result of the logical operation unit.

According to the present invention, when serial data modulated by PWM is demodulated into an original data sequence, if the demodulated data sequence is composed of a code in which "1" is not continuous, "0110" is apparent. Is a code that includes an error, and the expected code is a code that should be “0000”. Therefore, by detecting a code string "0110" and arranging a circuit for converting the code string into "0000" at the subsequent stage of the demodulation circuit, a data string with few errors can be obtained.

[0020]

Embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is an electric circuit diagram showing a configuration of an error correction circuit according to an embodiment of the present invention, and FIG. 2 is a timing chart showing an operation example of the error correction circuit according to the embodiment.

PWM demodulation circuit 12 surrounded by a dotted line
And an error correction circuit 11 also surrounded by a dotted line.

The PWM demodulation circuit 12 is an XOR circuit which receives as input signals a which is an output of DF / F (D flip-flops) 1 and 2 and DF / F1 and a signal b which is an output of DF / F2. The signal c, which is composed of the gate 3 and is the output of the XOR gate 3, becomes the input data of the error correction circuit 11.

This signal c is also demodulated data obtained by a conventional PWM demodulation circuit.

Next, the configuration of the error correction circuit 11 will be described.

The error correction circuit 11 has DF / F4,
5, 6, 7 and AND gates 8, 9 and a NAND gate 10. Then, it can be said that the NAND gate functions as a logical operation unit and the AND gate functions as an error correction control unit.

DF / F1, 2, 4 to 7 all operate by the same clock signal.

The signal c, which is output data from the PWM demodulation circuit 12, is input to the DF / F4. Hereafter, D
The data is transmitted to -F / Fs 5, 6, and 7 and is output as output data from the DF / F 7 after a delay of 4 clocks.

During the four clock delay, an impossible data string "0110" is detected. The detection of “0110” is based on the fact that the output signals of each DF / F are in order from DF / F4.
This is performed when 0, “1”, “1”, or “0” is reached.

It is the NAND gate 10 that performs this detection, and when it is detected, the output signal g is "0".
become. This signal g is one of the inputs of AND gates 8 and 9 located before the inputs of DF / Fs 6 and 7. When the signal g is "0", the DF / F is output by this AND gate.
When the outputs 5 and 6 are latched as inputs of the next stage, they are forcibly set to "0".

As a result, the pattern “0110” becomes D-
If detected within F / Fs 4 to 7, after one clock, "0"
000 ".

FIG. 2 shows an example of such a situation, and shows error correction of output data obtained when the input data of FIG. 4 used in the description of the prior art is used in this embodiment.

As is apparent from FIG. 2, an error occurs once on the signal c due to the pulse noise on the input signal, but the signal output from the DF / F 7 (output data) In the above, the error has been corrected.

[0034]

The effect of the present invention is that when the original data sequence is a code sequence in which 1s are not continuous, it is one of the data sequences that cannot originally exist when demodulating the PWM-modulated data sequence. By detecting a data string indicating that “1” is continuous, converting the data string to a data string indicating that “1” is not continuous, and sending it out, it is possible to reduce data errors included before demodulation. It is possible.

Thus, the reliability of the restored data can be improved.

[Brief description of the drawings]

FIG. 1 is an electric circuit diagram showing a configuration of an error correction circuit according to an embodiment of the present invention.

FIG. 2 is a timing chart showing an operation example of the error correction circuit according to the embodiment;

FIG. 3 is an electric circuit diagram showing a configuration of a conventional PWM demodulation circuit.

FIG. 4 is a timing chart showing an operation example of a conventional PWM demodulation circuit.

FIG. 5 is a diagram for explaining a PWM modulation method;

[Explanation of symbols]

 1, 2 DF / F (D flip-flop) 3 XOR logic gate 4, 5, 6, 7 DF / F (D flip-flop) 8, 9 AND logic gate 10 NAND logic gate 11 PWM demodulation circuit 12 Error Correction circuits 31, 32 DF / F (D flip-flop) 33 XOR logic gate

Claims (3)

[Claims] When demodulating PWM-modulated data into original data, an expected data sequence is a code sequence composed of a 1-bit width code in which “1” is not continuous. An error correction circuit comprising: means for detecting a bit string in which "1" is continuous, and converting the bit string in which "1" is continuous to a bit string in which "1" is not continuous when detected. 2. A multi-stage D-flip-flop connected to an output terminal of a PWM demodulation circuit, a logic operation unit for detecting an output of the D-flip-flop of each stage, and a logic operation unit based on a logic result of the logic operation unit. An error correction control unit for controlling an output of the D-flip-flop of each stage. 3. The error correction circuit according to claim 2, wherein the logical operation unit is a NOT product logic circuit, and the error correction control unit is an AND circuit.