JPH11177100A - Insulated gate transistor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To miniaturize a transistor and to increase its density by leading the drain region to a single-crystal semiconductor substrate where a first insulation film is adhered to the first main surface of a single-crystal layer via a conductive layer. SOLUTION: In a substrate, a first insulation film 9 is adhered to the side of a flat surface 9a at the opposite side of a single-crystal semiconductor layer 1 using a conductive adhesive. A transistor consists of a single-crystal semiconductor substrate 30' with a second conductivity where an impurity for giving a second conductivity is introduced with a relatively high concentration. Then, a window 29 extended between a drain region 4 and the single-crystal semiconductor substrate 30' is formed on the first insulation film 9, and the window 29 is buried by a conductive layer 31 connected to the drain region 4 and the single-crystal semiconductor substrate 30'. More specifically, the drain region 4 is led to the single-crystal semiconductor substrate 30' where a first insulation film 9 on a first main surface 1a of the single-crystal semiconductor layer 1 is adhered via a conductive layer 31.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to field-effect and bipolar insulated gate transistors.

[0002]

2. Description of the Related Art Hitherto, a field effect type insulated gate transistor described below with reference to FIG. 12 has been proposed. That is, the element isolation insulating film 2 is made of a single-crystal silicon layer having first and second main surfaces 1a and 1b and having a p-type as a first conductivity type, and made of silicon oxide.
Having a single crystal semiconductor layer 1 surrounded by

In the single crystal semiconductor layer 1, a source region 3 having an n-type as a second conductivity type opposite to a p-type as a first conductivity type is formed from the first main surface 1a side. Second
And an offset region 6 having an n-type as a second conductivity type into which an impurity giving an n-type as a conductivity type is introduced at a relatively low concentration, so that a channel region 5 is left therebetween. The second conductive layer is formed at a depth reaching the main surface 1b of the second conductive type and has a relatively high concentration of an impurity imparting n-type as the second conductive type introduced from the first main surface 1a side. Drain region 4 having n-type as a type
However, it is connected to the offset region 6 on the side opposite to the channel region 5 side, and is formed to a depth reaching the second main surface 1b.

The first main surface 1a of the single crystal semiconductor layer 1 is
The element isolation is made such that a gate electrode 7 made of a polycrystalline silicon layer into which an impurity imparting conductivity is introduced at a high concentration faces the channel region 5 via a gate insulating film 8 made of silicon oxide. A first insulating film 9 which is formed on the insulating film 2 for use and is made of silicon oxide.
Are formed to cover the gate electrode 7, the gate insulating film 8, and the insulating film 2 for element isolation. In this case, the surface of the first insulating film 9 opposite to the single crystal semiconductor layer 1 side is a flat surface 9.
a.

Further, second main surface 1 of single crystal semiconductor layer 1
b, a second insulating film 10 made of silicon oxide is formed, and the source region 3 is formed on the second insulating film 10.
And windows 13 and 14 for exposing the drain region 4 to the outside, respectively.

A source electrode 23 and a drain electrode 24 connected to the source region 3 and the drain region 4 through the windows 13 and 14, respectively, are formed on the second insulating film 10.

Although not shown, a gate electrode 7 is formed on the element isolation insulating film 2 and the second insulating film 10 through them.
Is formed on the second insulating film 10, and a gate electrode leading conductive layer connected to the gate electrode 7 through the window is formed on the second insulating film 10.

Further, a substrate 30 made of single crystal silicon, quartz, Pyrex, silicon carbide, aluminum nitride, diamond, sapphire, etc. is provided with an insulating film 9 on the flat surface 9a opposite to the single crystal semiconductor layer 1 side. It is provided to support the above-described configuration in a state where it is adhered to the above.

The above is the configuration of the conventionally proposed field effect type insulated gate transistor. A conventional field-effect insulated gate transistor having such a configuration is manufactured by a manufacturing method described below with reference to FIGS.

That is, an impurity giving the first conductivity type or the second conductivity type is provided on a single crystal semiconductor substrate 41 made of a single crystal silicon substrate having a p-type as the first conductivity type prepared in advance. Single crystal semiconductor layer 4 made of a single crystal silicon layer into which none of the impurities to be given is intentionally introduced.
2 is formed by an epitaxial growth method, and
In the single-crystal semiconductor layer 42, the p-type as the first conductivity type, which becomes the single-crystal semiconductor layer 1 described later with reference to FIG. 12 from the main surface 43 side opposite to the single-crystal semiconductor substrate 41 side, is formed. Forming a semiconductor region (well) 1 'having
A).

Next, on the main surface 43 side of the single crystal semiconductor layer 42, the element isolation insulating film 2 described above with reference to FIG. ′ Are formed by selective oxidation (FIG. 13B).

Next, the single crystal semiconductor substrate 4 which becomes the main surface 1a of the semiconductor region (well) 1 ', which will be described later with reference to FIG.
On the main surface 1a 'on the side opposite to the first side, an insulating film to be the gate insulating film 8 described later with reference to FIG. 12 is formed. A crystalline silicon layer is formed, and then the insulating film and the polycrystalline silicon layer are subjected to an etching process. On the semiconductor region (well) 1 ', the gate electrode 7 described above with reference to FIG.
When the structure formed via the gate insulating film 6 described above is viewed from the side opposite to the single crystal semiconductor substrate 41, the semiconductor region (well) 1 'is divided into two and the gate electrode 7 is separated from the element. It is formed so as to extend on the insulating film 2 for use (FIG. 13C).

Next, in the semiconductor region (well) 1 ', a second electrode using the gate electrode 7 from the main surface 1a' side as a mask is formed.
By the treatment for introducing an impurity giving n-type as the conductivity type, one of the two regions divided by the gate electrode 7 when viewed from the side opposite to the single crystal semiconductor substrate 41 side, the offset described later with reference to FIG. A region 6 'to be the region 6 is formed. Then, in the semiconductor region (well) 1' and the region 6 ', the gate electrode 7 from the main surface 1a' side of the semiconductor region (well) 1 'is used as a mask. The single crystal semiconductor substrate 4 is formed by introducing an impurity that gives n-type conductivity as the second conductivity type.
At the two positions sandwiching the gate electrode 7 as viewed from the side opposite to the first side, the regions 3 'and 4' which will become the source region 3 and the drain region 4 described later with reference to FIG. Thereafter, each is formed so as to leave the region 5 'which becomes the channel region 5 described above with reference to FIG. 12 (FIG. 14).
D).

Next, an insulating film to be the first insulating film 9 described above with reference to FIG. 12 is formed on the single crystal semiconductor layer 42 by the element separating insulating film 2, the gate electrode 7, the gate insulating film 8, and the region 3 '. ,
4 'and 6' are formed so as to cover them. Then, the surface of the insulating film opposite to the side of the single crystal semiconductor layer 42 is flattened by polishing, so that the insulating film having the flat surface 9a described above with reference to FIG. The film 9 is formed (FIG. 14E). Next, the substrate 30 described above with reference to FIG. 12 is bonded onto the flat surface 9a of the insulating film 9 (FIG. 1).
5F).

Next, from the side of the single crystal semiconductor substrate 41, the single crystal semiconductor substrate 4
1, single crystal semiconductor layer 42, semiconductor region 1 ', region 3',
By performing the removal process on 4 ', 5' and 6 ', the first and second main surfaces 1a and 2a described above with reference to FIG. 12 are removed from the semiconductor region 1', regions 3 ', 4', 5 'and 6'. 1b
, A source region 3, a drain region 4, a channel region 5, and an offset region 6 are formed (FIG. 15G).

Next, the second main surface 1b of the single crystal semiconductor layer 1
The second insulating film 10 described above with reference to FIG. 12 is formed thereon, and the window 13 described above with reference to FIG. 12 is formed on the second insulating film 10 so that the source region 3 and the drain region 4 are respectively exposed to the outside. And 14 (FIG. 16H).

Next, the source region 3 and the drain region 4 are formed on the second insulating film 10 through the windows 13 and 14, respectively.
The source electrode 2 described above with reference to FIG.
3 and the drain electrode 24 are formed (FIG. 16I).

Although not shown, after the windows 13 and 14 are formed in the second insulating film 10 or before or after the gate electrode 7 is passed through the second insulating film 10 and the isolation insulating film 2 through them. A window (not shown) facing the outside is formed, and after or before the source electrode 23 and the drain electrode 24 are formed, the window through the second insulating film 10 and the isolation insulating film 2 is formed. A conductive layer for extracting a gate electrode connected to the gate electrode 7 is formed.

The above is the method for manufacturing the conventional field-effect insulated gate transistor described above with reference to FIG. From the above description, the configuration of the conventional field-effect insulated gate transistor shown in FIG. 12 has become clearer.

According to the conventional field effect type insulated gate transistor having such a structure, the source electrode 23
A load (not shown) is connected between the gate electrode 7 and the drain electrode 24 via a power supply (not shown) having the positive electrode side as the drain electrode 24 side. If a control voltage source (not shown) is connected between the conductive layer and the source electrode 23, an n-channel is formed on the gate insulating film 8 side of the channel region 5 according to the value of the control voltage from the control voltage source. The extension between the source region 3 and the offset region 6 can be controlled, and thus, the turning on between the source region 3 and the drain region 4 can be controlled, and thus the control voltage can be controlled. It is possible to obtain a function as a field-effect insulated gate transistor in which supply of current to a load can be controlled in accordance with a value of a control voltage from a source.

The conventional insulated gate transistor shown in FIG. 12 has a configuration in which the offset region 6 is interposed between the channel region 5 and the drain region 4, so that the source electrode 23 and the drain electrode 24 The withstand voltage is higher than the case where the offset region 6 is not interposed between the channel region 5 and the drain region 4, and thus the source electrode 23 and the drain electrode 2
The limitation on the voltage of the power supply connected through a load between the power supply 4 and the power supply 4 is smaller than the case where the offset region 6 is not interposed between the channel region 5 and the drain region 4.
Can ease.

A field-effect insulated gate transistor described below with reference to FIG. 17 has also been proposed. That is, the portions corresponding to those in FIG. 12 are denoted by the same reference numerals, and detailed description thereof is omitted. However, a window 13 that exposes the source region 3 formed in the second insulating film 10 to the outside is provided.
Instead of a window 13 ′ that exposes the source region 3 and the channel region 5 to the outside, it is formed on the second insulating film 10 so as to be connected to the source region 3 through the window 13. The source electrode 23 is replaced with a source / back gate voltage applying electrode 23 ′ formed on the second insulating film 10 and connected to the source region 3 and the channel region 5 through the window 13 ′. Except for FIG.
Has the same configuration as the conventional field-effect insulated gate transistor shown in FIG.

According to the conventional field-effect insulated gate transistor having the above-described structure, the structure is the same as that of the conventional field-effect insulated gate transistor shown in FIG. Therefore, although the detailed description is omitted, the conventional field effect shown in FIG. 12 in which the source electrode 23 is replaced with the source / back gate voltage applying electrode 23 'in the description of the conventional insulated gate transistor shown in FIG. It is clear that the same operation and effect as in the case of the insulated gate type transistor can be obtained.

According to the conventional field effect type insulated gate transistor shown in FIG. 17, the source / back gate voltage applying electrode 23 'is connected to the source region 3 and the channel region 5. In channel area 5,
The back gate voltage can be applied at a value sufficiently close to the potential of the source region 3, so that the function as a field-effect insulated gate transistor can be stably obtained.

A bipolar insulated gate transistor described below with reference to FIG. 18 has also been proposed. That is, portions corresponding to those in FIG. 12 are denoted by the same reference numerals, and detailed description thereof will be omitted.
Inside, from the first main surface 1a side, n as the second conductivity type
The drain region 4 having a shape is connected to the offset region 6 on the side opposite to the channel region 5 side, and is formed to a depth reaching the second main surface 1b. A drain region 4 ′ having a p-type as a first conductivity type into which an impurity giving a p-type as a first conductivity type is introduced at a relatively high concentration from the first main surface 1 a side is formed. The conventional field-effect insulated gate type shown in FIG. 12 except that it is formed so as to be connected to the offset region 6 on the side opposite to the channel region 5 and to reach the second main surface 1b. It has a configuration similar to that of a transistor.

Since such a conventional bipolar insulated gate transistor has the same configuration as the conventional field effect insulated gate transistor shown in FIG. Is omitted,
As in the case of the conventional insulated gate transistor shown in FIG. 12, a load (not shown) is applied between the source electrode 23 and the drain electrode 24, that is, between the source region 5 and the drain region 4 '. And a gate electrode lead-out conductive layer connected to the source electrode 23 and the gate electrode 7.
Therefore, when a control voltage source (not shown) is connected between the source region 3 and the gate electrode 7, the source region 3 and the channel region 5 are disposed on the gate insulating film 8 side of the channel region 5 according to the value of the control voltage from the control voltage source. The formation of an n-channel extending between the offset regions 6 can be controlled, and therefore
The turning on between the source electrode 23 and thus the source region 3 and the drain electrode 24 and thus the drain region 4 'can be controlled, and in this case the drain region 4' is shown in FIG. Unlike the drain region 4 in the case of the conventional field effect type insulated gate transistor, p
Since it has a shape, holes can be injected from the drain region 4 ′ to the channel region 5 side through the offset region 6, so that it is possible to supply current to the load according to the value of the control voltage from the control voltage source. A bipolar insulated gate type in which the current at the time of current supply can be controlled in such a manner that the current can be made larger than that of the conventional field effect type insulated gate transistor shown in FIG. A function as a transistor is obtained.

Conventionally, a bipolar insulated gate transistor described below with reference to FIG. 19 has also been proposed. That is, portions corresponding to those in FIG. 18 are denoted by the same reference numerals, and detailed description thereof will be omitted, but the window 13 with the source region 23 formed in the second insulating film 10 facing the outside is shown.
Is replaced with a window 13 ′ that exposes the source region 3 and the channel region 5 to the outside.
A source electrode 23 formed on the insulating film 10 and connected to the source region 3 through the window 13 is formed on the second insulating film 10.
The conventional bipolar type shown in FIG. 18 is replaced by a source / back gate voltage applying electrode 23 'formed above and connected to the source region 3 and the channel region 5 through the window 13'. Has the same configuration as the insulated gate transistor.

The conventional bipolar insulated gate transistor having such a configuration has the same configuration as the conventional bipolar insulated gate transistor shown in FIG. 18 except for the above-described matters. Although the detailed description is omitted, the conventional field-effect type transistor shown in FIG. 18 in which the source electrode 23 is replaced with the source / back gate voltage applying electrode 23 'in the description of the conventional insulated gate transistor shown in FIG. It is clear that the same operation and effect as in the case of the insulated gate transistor can be obtained.

According to the conventional bipolar insulated gate transistor shown in FIG. 19, the source / back gate voltage applying electrode 23 'is connected to the source region 3 and the channel region 5, so that the channel Area 5
In addition, the back gate voltage can be applied at a value sufficiently close to the potential of the source region 3, so that the function as a bipolar insulated gate transistor can be stably obtained.

A field effect insulated gate transistor described below with reference to FIG. 20 has been proposed.

That is, portions corresponding to those in FIG. 12 are denoted by the same reference numerals, and detailed description thereof will be omitted. However, in the single crystal semiconductor layer 1, (a) the first conductivity type from the first main surface 1a side The source region 3 having the n-type as the second conductivity type opposite to the p-type as the second conductivity type and the impurity giving the n-type as the second conductivity type are introduced at a relatively low concentration. N as
An offset region 6 having a mold is formed at a depth reaching the second main surface 1b so as to leave the channel region 5 therebetween, and a second conductive region is formed from the first main surface 1a side. A drain region 4 having an n-type as a second conductivity type into which an impurity giving an n-type as a type is introduced at a relatively high concentration is provided in a channel region 5 in an offset region 6.
Instead of being connected to the side opposite to the side and being formed to a depth reaching the second main surface 1b, (b) the first main surface 1a side is formed in the single crystal semiconductor layer 1 from the first main surface 1a side. The source region 3 and the drain region 4 having the n-type as the second conductivity type opposite to the p-type as the first conductivity type are formed on the second main surface 1b so as to leave the channel region 5 therebetween. Except that it is formed to a depth that reaches, it has a configuration similar to that of the conventional field-effect insulated gate transistor shown in FIG.

The above is the configuration of the conventionally proposed field-effect insulated gate transistor.

According to the conventional field-effect insulated gate transistor having such a configuration, the same structure as that of the conventional field-effect insulated gate transistor shown in FIG. Therefore, although detailed description is omitted, the source electrode 23 and the drain electrode 24
It is apparent that the same operation and effect as those of the conventional field-effect insulated gate transistor shown in FIG.

A field-effect insulated gate transistor described below with reference to FIG. 21 has also been proposed. That is, portions corresponding to those in FIG. 20 are denoted by the same reference numerals, and detailed description thereof will be omitted. However, a window 13 that exposes the source region 3 formed in the second insulating film 10 to the outside is provided.
Instead of a window 13 ′ that exposes the source region 3 and the channel region 5 to the outside, it is formed on the second insulating film 10 so as to be connected to the source region 3 through the window 13. The source electrode 23 is replaced with a source / back gate voltage applying electrode 13 ′ formed on the second insulating film 10 and connected to the source region 3 and the channel region 5 through the window 13 ′. Except for FIG.
Has the same configuration as the conventional field-effect insulated gate transistor shown in FIG.

According to the conventional field-effect insulated gate transistor having the above-described structure, the structure is the same as that of the conventional field-effect insulated gate transistor shown in FIG. Therefore, although detailed description is omitted, the conventional field effect effect shown in FIG. 20 in which the source electrode 23 is replaced with the source / back gate voltage applying electrode 23 'in the description of the conventional insulated gate transistor shown in FIG. It is clear that the same operation and effect as in the case of the insulated gate type transistor can be obtained, and the source / back gate voltage applying electrode 23 ′
Since it is connected to the source region 3 and the channel region 5, a back gate voltage can be applied to the channel region 5 at a value sufficiently close to the potential of the source region 3, and therefore, as a field effect insulated gate transistor. Function can be stably obtained.

[0036]

Problems to be Solved by the Invention FIGS. 12, 17, and 1
8, 19, 20, and 21, the source region 3, the drain region 4, and the gate electrode 7 are formed of the second main gate of the single crystal semiconductor layer 1 in any of them. These are led out to the source electrode 23, the drain electrode, and the gate electrode lead-out conductive layer, both extending on the second insulating film 10 on the surface 1b.

Therefore, extending the source electrode 23, the drain electrode 24, and the gate electrode lead-out conductive layer on the second insulating film 10 is restricted by each other. Has a drawback that the plane area occupied by the semiconductor device is reduced, and that the insulated gate transistor is limited in size and density.

Thus, the present invention is free from the disadvantages mentioned above,
It is intended to propose new field-effect and bipolar insulated gate transistors.

[0039]

The field effect type insulated gate transistor according to the first invention of the present application is the same as the conventional field effect type insulated gate transistor described above with reference to FIG. 12 or FIG. (A) a single-crystal semiconductor layer having first and second principal surfaces and having a first conductivity type; and (b) the first crystal semiconductor layer in the single-crystal semiconductor layer.
From the main surface side, has a source region having a second conductivity type opposite to the first conductivity type and a second conductivity type into which impurities giving the second conductivity type are introduced at a relatively low concentration. So that the offset area leaves the channel area between them
A second conductivity type formed at a depth reaching the second main surface and having a relatively high concentration of impurities imparting the second conductivity type introduced from the first main surface side. A drain region connected to the offset region on the side opposite to the channel region and formed to a depth reaching the second main surface; and (c) a drain region on the first main surface of the single crystal semiconductor layer. A gate electrode is formed to face the channel region via a gate insulating film, and a first insulating film is formed to cover the gate electrode and the gate insulating film; The surface of the insulating film opposite to the single crystal semiconductor layer side is a flat surface, and (e)
The first insulating film is adhered to the substrate on the flat surface side; (f) a second insulating film is formed on a second main surface of the single crystal semiconductor layer; (g) A source electrode connected to the source region or a source / back gate voltage applying electrode connected to the source region and the channel region is formed on the second insulating film.

However, the field-effect insulated gate transistor according to the first invention of the present application is the same as the field-effect insulated gate transistor having the above-described structure, and (h) the substrate is formed of the second conductivity type. And (i) extending the first insulating film between the drain region and the single-crystal semiconductor substrate. (J) the window is filled with a conductive layer connected to the drain region and the single crystal semiconductor substrate.

The bipolar insulated gate transistor according to the second invention of the present application is similar to the conventional bipolar insulated gate transistor described above with reference to FIGS. A single-crystal semiconductor layer having a second main surface and having a first conductivity type, wherein the single-crystal semiconductor layer has an opposite side to the first conductivity type in the single-crystal semiconductor layer from the first main surface side; A source region having a second conductivity type and a second
And an offset region having a second conductivity type into which an impurity giving the conductivity type is introduced at a relatively low concentration, is formed at a depth reaching the second main surface so as to leave a channel region therebetween. And a drain region having a first conductivity type into which an impurity imparting a first conductivity type is introduced at a relatively high concentration from the first main surface side is provided in the offset region in the channel region. Articulated on the opposite side to the side and formed to a depth reaching the second main surface,
(B) a gate electrode is formed on the first main surface of the single crystal semiconductor layer so as to face the channel region via a gate insulating film, and the first insulating film is (C) formed over the gate insulating film;
The surface of the first insulating film opposite to the single crystal semiconductor layer side is a flat surface, and (d) the first insulating film is bonded to the substrate on the flat surface side. (E) a second insulating film is formed on a second main surface of the single crystal semiconductor layer, and (f) a source electrode or a source electrode connected to the source region on the second insulating film. A source / back gate voltage applying electrode connected to the source region and the channel region is formed.

However, the bipolar insulated gate transistor according to the second invention of the present application is a bipolar insulated gate transistor having such a configuration, wherein (g) the substrate provides the first conductivity type. A single-crystal semiconductor substrate having a first conductivity type into which impurities are introduced at a relatively high concentration; and (h) extending over the first insulating film between the drain region and the single-crystal semiconductor substrate. And (i) the window is filled with a conductive layer connected to the drain region and the single crystal semiconductor substrate.

The field effect type insulated gate transistor according to the third invention of the present application is similar to the conventional field effect type insulated gate transistor described above with reference to FIGS. A single-crystal semiconductor layer having first and second main surfaces and having a first conductivity type; and (b) a first conductive layer in the single-crystal semiconductor layer from the first main surface side. A source region and a rain region having a second conductivity type opposite to the mold leaving a channel region therebetween.
(C) a gate electrode is formed on the first main surface of the single crystal semiconductor layer so as to face the channel region via a gate insulating film; And a first insulating film is formed to cover the gate electrode and the gate insulating film, and (d) a surface of the first insulating film opposite to the single crystal semiconductor layer is a flat surface. (E) the first insulating film is adhered to the substrate on the flat surface side, and (f) a second insulating film is formed on the second main surface of the single crystal semiconductor layer. Formed,
(G) A source electrode connected to the source region or a source / back gate voltage applying electrode connected to the source region and the channel region is formed on the second insulating film.

However, the field effect type insulated gate transistor according to the third invention of the present application is the same as the field effect type insulated gate transistor having the above-mentioned structure, and (h) the substrate is formed of the second conductivity type. And (i) extending the first insulating film between the drain region and the single-crystal semiconductor substrate. (J) the window is filled with a conductive layer connected to the drain region and the single crystal semiconductor substrate.

[0045]

Embodiment 1 Next, referring to FIG.
The first embodiment of the field effect insulated gate transistor according to the second invention will be described.

In the field-effect insulated gate transistor according to the first aspect of the present invention shown in FIG. 1, portions corresponding to those of the conventional field-effect insulated gate transistor shown in FIG. Although description is omitted, a window 14 is formed in the second insulating film 10 so that the drain region 4 is exposed to the outside.
Is omitted, and accordingly,
The drain region 4 is formed on the second insulating film 10 through the window 14.
The formation of the drain electrode 24 connected to the substrate 30 is omitted, however, the substrate 30 on which the first insulating film 9 is bonded on the flat surface 9a side opposite to the single crystal semiconductor layer 1 side The first insulating film 9 is
The second surface has a relatively high concentration of impurities imparting n-type conductivity as the second conductivity type, which is bonded to the flat surface 9a opposite to the side using a conductive adhesive. Is replaced with a single crystal semiconductor substrate 30 'made of a single crystal silicon substrate having an n-type as the conductivity type, and extends between the drain region 4 and the single crystal semiconductor substrate 30' on the first insulating film 9. Window 29 is formed and the window 2
9 is a conductive layer 31 made of, for example, tungsten and connected to the drain region 4 and the single crystal semiconductor substrate 30 '.
It has the same configuration as the conventional field-effect insulated gate transistor shown in FIG.

The above is the configuration of the first embodiment of the field-effect insulated gate transistor according to the first invention of the present application. The first embodiment of the field-effect insulated gate transistor according to the first invention of the present application having such a configuration is manufactured by an embodiment of a manufacturing method described below with reference to FIGS. I can do it.

That is, in FIGS.
Parts corresponding to those in FIG. 16 are denoted by the same reference numerals, and detailed description thereof is omitted. However, as in the case of the conventional insulated gate transistor shown in FIGS. A single crystal semiconductor layer 42 is formed on the substrate, and the single crystal semiconductor layer 1 described above with reference to FIG.
A p-type semiconductor region (well) 1 'is formed (FIG. 2A).

Next, as in the case of the conventional method of manufacturing an insulated gate transistor shown in FIGS. 13 to 16, an element isolation insulating film 44 is formed on the main surface 43 side of the single crystal semiconductor layer 42 in the semiconductor region ( (Well) 1 '(FIG. 3B).

Next, in the same manner as in the case of the conventional method of manufacturing the insulated gate transistor shown in FIGS. 13 to 16, on the main surface 1a 'of the semiconductor region (well) 1' in FIG. The configuration in which the gate electrode 7 described above is formed via the gate insulating film 6 described above with reference to FIG. 1 is such that the semiconductor region (well) 1 ′ is divided into two when viewed from the side opposite to the single crystal semiconductor substrate 41 side. And the gate electrode 7 is formed so as to extend on the isolation insulating film 2 (FIG. 3C).

Next, in the same manner as in the case of the conventional method of manufacturing the insulated gate transistor shown in FIGS. 13 to 16, by the same processing, the offset region described above with reference to FIG. 6 are formed, and then, in the semiconductor region (well) 1 'and the region 6', the regions 3 'and 4' which become the source region 3 and the drain region 4 described later with reference to FIG. A region 5 'is formed between the region 3' and the region 6 'so as to remain as the channel region 5 described later with reference to FIG. 1 (FIG. 3D).

Next, on the single-crystal semiconductor layer 42, FIGS.
As in the case of the conventional method of manufacturing the insulated gate transistor shown in FIG. 16, the insulating film to be the first insulating film 9 described above with reference to FIG. 1 is replaced with the element isolating insulating film 2, the gate electrode 7, and the gate insulating film 8. , Covering the regions 3 ', 4' and 6 ',
Next, as in the case of the conventional method of manufacturing the insulated gate transistor shown in FIGS. 13 to 16, the surface of the insulating film opposite to the single crystal semiconductor layer 42 side is flattened by polishing, and FIG. The first insulating film 9 having the flat surface 9a described above is formed, and then the window 29 described above with reference to FIG. 1 is formed on the first insulating film 9 so that the region 4 'faces outside (FIG. 4E).

Next, a window 29 formed in the first insulating film 9 is formed.
Is filled with a conductive layer 31 made of, for example, tungsten and connected to the region 4 'so that the upper surface is flush with the flat surface 9a of the first insulating film 9 (FIG. 4F).

Next, on the flat surface 9a of the first insulating film 9, the single crystal semiconductor substrate 30 'described above with reference to FIG. 3
Adhesion is applied to the mode connected to 0 '(FIG. 5G).

Next, as in the case of the conventional method of manufacturing an insulated gate transistor shown in FIGS. 13 to 16, the single crystal semiconductor substrate 41 is moved from the single crystal semiconductor substrate 41 side to the element isolation insulating film 44. , The single crystal semiconductor layer 42, the semiconductor region 1 ', the regions 3', 4 ', 5', and 6 'are removed from the semiconductor region 1', the regions 3 ', 4', 5 ', and 6'. A single-crystal semiconductor layer 1 having first and second main surfaces 1a and 1b described above with reference to FIG.
A source region 3, a drain region 4, a channel region 5, and an offset region 6 are formed (FIG. 5H).

Next, in accordance with the case of the conventional insulated gate transistor shown in FIGS.
The second insulating film 1 described above with reference to FIG.
0 is formed, and the window 13 described above with reference to FIG. 1 is formed in the second insulating film 10 so that the source region 3 faces the outside (FIG. 6I).

Next, according to the conventional method of manufacturing the insulated gate transistor shown in FIGS. 13 to 16, the source region 3 is connected to the source region 3 through the window 13 on the second insulating film 10. The above-described source electrode 23 is formed (FIG. 6
J).

Although not shown, after or before the window 13 is formed in the second insulating film 10, the gate electrode 7 is exposed to the outside through the second insulating film 10 and the isolation insulating film 2 through them. A window (not shown) is formed, and after or before the source electrode 23 is formed, it is connected to the gate electrode 7 through the window through the second insulating film 10 and the element isolation insulating film 2. The gate electrode leading conductive layer is formed.

The above is the embodiment of the manufacturing method of the first embodiment of the field-effect insulated gate transistor according to the first invention of the present application described above with reference to FIG. From the above, the configuration of the first embodiment of the field-effect insulated gate transistor according to the first invention of the present application has become clearer.

The first embodiment of the field-effect insulated gate transistor according to the first aspect of the present invention having such a configuration is described below.
According to the embodiment, the drain region 4 is formed of the conductive layer 31.
12, the structure is led out to the single crystal semiconductor substrate 30 'via the gate electrode, so that the source electrode 23 and the single crystal semiconductor substrate 30' are connected in the same manner as in the case of the conventional field effect type insulated gate transistor shown in FIG. And a load (not shown)
A positive electrode side is connected via a power supply (not shown) having a single crystal semiconductor substrate 30 ′ side, and between the gate electrode leading conductive layer connected to the gate electrode 7 and the source electrode 23.
If a control voltage source (not shown) is connected, the gate insulating film 27 of the channel region 5 is controlled according to the value of the control voltage from the control voltage source, as in the case of the conventional insulated gate transistor shown in FIG. On the side, it is possible to control that an n-channel is formed extending between the source region 3 and the offset region 6, so that the source region 3 and the drain region 4 can be controlled.
Can be controlled to be in the on state,
As in the case of the conventional insulated gate transistor shown in FIG. 12, a field effect insulated gate capable of controlling supply of current to a load in accordance with the value of a control voltage from a control voltage source. The function as a type transistor can be obtained.

However, in the case of the field-effect insulated gate transistor according to the first aspect of the present invention shown in FIG. 1, the source region 3 and the gate electrode 7 have the conventional field-effect insulated gate transistor shown in FIG. As in the case of (1), the single crystal semiconductor layer 1 is led to the source electrode 23 and the gate electrode lead-out conductive layer extending on the second insulating film 10 on the second main surface 1b of the single crystal semiconductor layer 1. Drain region 4
However, unlike the case of the conventional field-effect insulated gate transistor shown in FIG. 12, a single crystal semiconductor in which the first insulating film 9 on the first main surface 1a of the single crystal semiconductor layer 1 is bonded. Since the configuration is such that the source electrode 23 and the gate electrode lead-out conductive layer extend on the second insulating film 10 because of the configuration led out to the substrate 30 ′ via the conductive layer 31, FIG.
12 is not limited by the drain electrode 24 extending on the second insulating film 10 as in the case of the conventional field effect type insulated gate transistor shown in FIG. Electrode 24 leading out of the drain region 4 does not extend over the second main surface 1b of the single crystal semiconductor layer 1 as in the case of the insulated gate transistor of the transistor type. The plane area occupied by the gate-type transistor can be reduced as compared with the conventional insulated-gate transistor shown in FIG.
2 can be made smaller and more densely than the conventional insulated gate transistor shown in FIG.

[0062]

[Embodiment 2] Next, with reference to FIG.
A second embodiment of the field-effect insulated gate transistor according to the second invention will be described.

The field-effect insulated gate transistor according to the first invention of the present invention shown in FIG. 7 includes a conventional field-effect insulated gate transistor shown in FIG. 17 and the first invention of the present invention shown in FIG. Corresponding portions to those of the field-effect insulated gate transistor are denoted by the same reference numerals, and detailed description thereof will be omitted. However, similar to the case of the field-effect insulated gate transistor according to the first invention shown in FIG. It is omitted that a window 14 for exposing the drain region 4 to the outside is formed in the second insulating film 10, and accordingly, the drain region is formed on the second insulating film 10 through the window 14. The formation of the drain electrode 24 connected to the first insulating film 9 is omitted.
Is bonded on the flat surface 9a side opposite to the single crystal semiconductor layer 1 side, and the first insulating film 9 is bonded to the flat surface 9a side opposite to the single crystal semiconductor layer 1 side. Single-crystal silicon having an n-type as the second conductivity type, which is bonded using an adhesive having conductivity and has a relatively high concentration of impurities imparting n-type as the second conductivity type. Instead of a single-crystal semiconductor substrate 30 '
A window 29 extending between the drain region 4 and the single crystal semiconductor substrate 30 'is formed in the first insulating film 9, and the window 29 is connected to the drain region 4 and the single crystal semiconductor substrate 30'. Except for being buried with the conductive layer 31 having the same structure as that of the conventional field-effect insulated gate transistor shown in FIG.

The above is the configuration of the second embodiment of the field-effect insulated gate transistor according to the first invention of the present application. The second embodiment of the field-effect insulated gate transistor according to the first aspect of the present invention having such a configuration is as follows.
According to the embodiment, except for the matters described above, FIG.
17 has the same configuration as that of the conventional field-effect insulated gate transistor described above, and a detailed description thereof will be omitted. However, in [Prior Art], the conventional field-effect insulated gate transistor shown in FIG. The same operation and effect as described in the above are obtained, and in [Embodiment 1], in the field effect type insulated gate transistor according to the first invention of the present application shown in FIG. Obviously, the same operation and effect as described with reference to the fact that the conductive layer 30 is led out through the conductive layer 31 can be obtained.

[0065]

Third Embodiment Next, referring to FIG.
The first embodiment of the bipolar insulated gate transistor according to the second invention will be described.

The bipolar insulated gate transistor according to the first invention of the present invention shown in FIG. 8 is a conventional bipolar insulated gate transistor shown in FIG. 18 and the field effect according to the first invention of the present invention shown in FIG. The same reference numerals are given to the portions corresponding to the insulated gate type transistors, and the detailed description is omitted. However, according to the case of the field effect type insulated gate transistor according to the first invention shown in FIG. The formation of a window 14 for exposing the drain region 4 to the outside is omitted in the insulating film 10 of FIG.
Accordingly, the formation of the drain electrode 24 connected to the drain region 4 through the window 14 on the second insulating film 10 is omitted, however, the first insulating film 9 is formed of a single crystal semiconductor. A substrate 30 adhered on the flat surface 9a side opposite to the layer 1 side has conductivity on the flat surface 9a side opposite to the single crystal semiconductor layer 1 side with the first insulating film 9 A single-crystal silicon substrate having a p-type as the first conductivity type and having a relatively high concentration of an impurity imparting a p-type as the first conductivity type, which is bonded using an adhesive. A window 29 extending between the drain region 4 and the single crystal semiconductor substrate 30 ′ is formed in the first insulating film 9 instead of the crystalline semiconductor substrate 30 ′, and the window 29 is made of tungsten. And the drain region 4 and the single crystal semiconductor It is filled with a conductive layer which is connected to the substrate 30 ', except that, FIG. 18
Has the same configuration as the conventional bipolar insulated gate transistor shown in FIG.

The above is the configuration of the first embodiment of the bipolar insulated gate transistor according to the second invention of the present application. According to the first embodiment of the bipolar insulated gate transistor according to the second invention of the present application having such a configuration, the conventional bipolar insulated gate transistor shown in FIG. Since the structure is the same as that of the transistor, the detailed description is omitted. However, in [Prior Art], the same operation and effect as those of the conventional bipolar insulated gate transistor shown in FIG. 18 can be obtained. [Embodiment 1]
In the field effect type insulated gate transistor according to the first aspect of the present invention shown in FIG. 1, the drain region 4 is led out to the single crystal semiconductor substrate 30 ′ via the conductive layer 31. It is clear that the operation and effect of the above can be obtained.

[0068]

Embodiment 4 Next, referring to FIG.
A second embodiment of the bipolar insulated gate transistor according to the second invention will be described.

The bipolar insulated gate transistor according to the second aspect of the present invention shown in FIG. 9 is a conventional bipolar insulated gate type transistor shown in FIG. 19 and the field effect according to the first aspect of the present invention shown in FIG. The same reference numerals are given to the portions corresponding to the insulated gate type transistors, and the detailed description is omitted. As in the case of the field effect type insulated gate transistor according to the first invention shown in FIG. The formation of a window 14 for exposing the drain region 4 to the outside is omitted in the insulating film 10 of FIG.
Accordingly, the formation of the drain electrode 24 connected to the drain region 4 through the window 14 on the second insulating film 10 is omitted, however, the first insulating film 9 is formed of a single crystal semiconductor. A substrate 30 adhered on the flat surface 9a side opposite to the layer 1 side has conductivity on the flat surface 9a side opposite to the single crystal semiconductor layer 1 side with the first insulating film 9 A single-crystal silicon substrate having a p-type as the first conductivity type and having a relatively high concentration of an impurity imparting a p-type as the first conductivity type, which is bonded using an adhesive. A window 29 extending between the drain region 4 and the single crystal semiconductor substrate 30 ′ is formed in the first insulating film 9 instead of the crystalline semiconductor substrate 30 ′, and the window 29 is made of tungsten. And the drain region 4 and the single crystal semiconductor It is filled with a conductive layer which is connected to the substrate 30 ', except that, FIG. 19
Has the same configuration as the conventional bipolar insulated gate transistor shown in FIG.

The above is the configuration of the bipolar insulated gate transistor according to the second embodiment of the present invention. According to the second embodiment of the bipolar insulated gate transistor according to the second invention of the present application having such a configuration, except for the above-described matter, the conventional bipolar insulated gate transistor shown in FIG. Since the structure is the same as that of the transistor, the detailed description is omitted. However, in [Prior Art], the same operation and effect as those of the conventional bipolar insulated gate transistor shown in FIG. 19 can be obtained. [Embodiment 1]
In the field effect type insulated gate transistor according to the first aspect of the present invention shown in FIG. 1, the drain region 4 is led out to the single crystal semiconductor substrate 30 ′ via the conductive layer 31. It is clear that the operation and effect of the above can be obtained.

[0071]

Fifth Embodiment Next, a first embodiment of a field-effect insulated gate transistor according to the third invention of the present application will be described with reference to FIG.

The field-effect insulated gate transistor according to the third invention shown in FIG. 10 is the same as the conventional field-effect insulated gate transistor shown in FIG.
The same reference numerals are given to portions corresponding to the field-effect insulated gate transistor according to the first invention of the present application shown in FIG. As in the case of the insulated gate transistor, the formation of the window 14 for exposing the drain region 4 to the outside is omitted in the second insulating film 10, and accordingly, the second insulating film It is omitted that the drain electrode 24 connected to the drain region 4 through the window 14 is formed on the first insulating film 9.
Is bonded on the flat surface 9a side opposite to the single crystal semiconductor layer 1 side, and the first insulating film 9 is bonded to the flat surface 9a side opposite to the single crystal semiconductor layer 1 side. Single-crystal silicon having an n-type as the second conductivity type, which is bonded using an adhesive having conductivity and has a relatively high concentration of impurities imparting n-type as the second conductivity type. Instead of a single-crystal semiconductor substrate 30 '
A window 29 extending between the drain region 4 and the single crystal semiconductor substrate 30 ′ is formed in the first insulating film 9, the window 29 is made of tungsten, and the drain region 4 and the single crystal semiconductor substrate 30 ′ are formed. 'Has the same structure as the conventional field-effect insulated gate transistor shown in FIG. 20 except that it is buried with a conductive layer connected to'.

The above is the configuration of the first embodiment of the field effect insulated gate transistor according to the third invention of the present application. The first embodiment of the field-effect insulated gate transistor according to the third aspect of the present invention having such a configuration.
According to the embodiment shown in FIG.
Since the configuration is the same as that of the conventional field-effect insulated gate transistor shown in FIG. 20, detailed description is omitted, but in [Prior Art], the conventional field-effect insulated gate transistor shown in FIG. The same operation and effect as described in the above are obtained, and in [Embodiment 1], in the field effect type insulated gate transistor according to the first invention of the present application shown in FIG. Obviously, the same operation and effect as described with reference to the fact that the conductive layer 30 is led out through the conductive layer 31 can be obtained.

[0074]

[Embodiment 6] Next, a second embodiment of a field effect insulated gate transistor according to the third invention of the present application will be described with reference to FIG.

The field effect type insulated gate transistor according to the third invention shown in FIG. 11 is the same as the conventional field effect type insulated gate transistor shown in FIG. 21 and FIG.
The same reference numerals are given to portions corresponding to the field-effect insulated gate transistor according to the first invention of the present application shown in FIG. As in the case of the insulated gate transistor, the formation of the window 14 for exposing the drain region 4 to the outside is omitted in the second insulating film 10, and accordingly, the second insulating film It is omitted that the drain electrode 24 connected to the drain region 4 through the window 14 is formed on the first insulating film 9.
Is bonded on the flat surface 9a side opposite to the single crystal semiconductor layer 1 side, and the first insulating film 9 is bonded to the flat surface 9a side opposite to the single crystal semiconductor layer 1 side. Single-crystal silicon having an n-type as the second conductivity type, which is bonded using an adhesive having conductivity and has a relatively high concentration of impurities imparting n-type as the second conductivity type. Instead of a single-crystal semiconductor substrate 30 '
A window 29 extending between the drain region 4 and the single crystal semiconductor substrate 30 ′ is formed in the first insulating film 9, the window 29 is made of tungsten, and the drain region 4 and the single crystal semiconductor substrate 30 ′ are formed. 'Has the same configuration as the conventional field-effect insulated gate transistor shown in FIG. 21 except that it is buried with a conductive layer connected to'.

The above is the configuration of the field effect type insulated gate transistor according to the third embodiment of the present invention. The second embodiment of the field-effect insulated gate transistor according to the third aspect of the present invention having such a configuration is as follows.
According to the embodiment shown in FIG.
Since the configuration is the same as that of the conventional field-effect insulated gate transistor shown in FIG. 21, detailed description is omitted, but in [Prior Art], the conventional field-effect insulated gate transistor shown in FIG. The same operation and effect as described in the above are obtained, and in [Embodiment 1], in the field effect type insulated gate transistor according to the first invention of the present application shown in FIG. Obviously, the same operation and effect as described with reference to the fact that the conductive layer 30 is led out through the conductive layer 31 can be obtained.

In the above, only a few embodiments have been described for each of the insulated gate transistors according to the first invention, the second invention and the third invention of the present application. Various modifications and changes may be made without departing from the spirit of the invention.

[0078]

In the case of the insulated gate transistors according to the first invention, the second invention and the third invention of the present application, the source region of each of them is the same as that of the conventional field effect type insulated gate transistor. As in the case of the transistor, the source electrode is extended to the source electrode extending on the second insulating film on the second main surface of the single crystal semiconductor layer. Unlike the case, the source electrode is provided through the conductive layer to the single crystal semiconductor substrate to which the first insulating film over the first main surface of the single crystal semiconductor layer is bonded, so that the source electrode is The extension on the second insulating film is not limited by the drain electrode extending on the second insulating film as in the case of the conventional insulated gate transistor, and the conventional insulated gate Type tiger Like the register, and a drain electrode that is derived drain region, the single crystal semiconductor layer and the second
Because it does not extend on the main surface of the transistor, the plane area occupied by the insulated gate transistor can be reduced as compared with the case of the conventional insulated gate transistor. Compared with a conventional insulated gate type transistor, it is possible to realize a compact and dense structure.

[Brief description of the drawings]

FIG. 1 is a schematic cross-sectional view showing a first embodiment of a field-effect insulated gate transistor according to the first invention of the present application.

FIG. 2 is a schematic cross-sectional view in a sequential step for describing a method of manufacturing the field-effect insulated gate transistor according to the first embodiment of the present invention shown in FIG. 1 according to the first embodiment;

FIG. 3 is a view for explaining a method of manufacturing the field-effect insulated gate transistor according to the first embodiment of the first invention shown in FIG. 1 in a sequential step following the sequential step shown in FIG. 2; It is an approximate line sectional view.

FIG. 4 is a view for explaining a method of manufacturing the field-effect insulated gate transistor according to the first embodiment of the first invention shown in FIG. 1 in a sequential step following the sequential step shown in FIG. 3; It is an approximate line sectional view.

FIG. 5 is a diagram illustrating a method of manufacturing the field-effect insulated gate transistor according to the first embodiment of the first invention shown in FIG. 1 in a sequential step following the sequential step shown in FIG. 4; It is an approximate line sectional view.

FIG. 6 is a view for explaining a method of manufacturing the field-effect insulated gate transistor according to the first embodiment of the first invention shown in FIG. 1 in a sequential step subsequent to the sequential step shown in FIG. 5; It is an approximate line sectional view.

FIG. 7 is a schematic sectional view showing a second embodiment of a field-effect insulated gate transistor according to the first invention of the present application;

FIG. 8 is a schematic sectional view showing a first embodiment of a bipolar insulated gate transistor according to the second invention of the present application;

FIG. 9 is a schematic sectional view showing a bipolar insulated gate transistor according to a second embodiment of the present invention.

FIG. 10 is a schematic sectional view showing a first embodiment of a field-effect insulated gate transistor according to the third invention of the present application;

FIG. 11 is a schematic sectional view showing a second embodiment of a field-effect insulated gate transistor according to the third invention of the present application.

FIG. 12 is a schematic cross-sectional view showing one conventional field-effect insulated gate transistor.

FIG. 13 is a schematic cross-sectional view in a sequential step for explaining a method of manufacturing the conventional field-effect insulated gate transistor shown in FIG.

FIG. 14 is a schematic cross-sectional view in a step subsequent to the step shown in FIG. 13 for explaining the method of manufacturing the conventional field-effect insulated gate transistor shown in FIG.

15 is a schematic cross-sectional view in a step subsequent to the step shown in FIG. 14 for explaining the method of manufacturing the conventional field-effect insulated gate transistor shown in FIG.

16 is a schematic cross-sectional view in a sequential step following the sequential step shown in FIG. 15 for explaining the method of manufacturing the conventional field-effect insulated gate transistor shown in FIG.

FIG. 17 is a schematic sectional view showing another conventional field-effect insulated gate transistor.

FIG. 18 is a schematic sectional view showing one of conventional bipolar insulated gate transistors.

FIG. 19 is a schematic sectional view showing another example of a conventional bipolar insulated gate transistor.

FIG. 20 is a schematic sectional view showing still another conventional field-effect insulated gate transistor.

FIG. 21 is a schematic sectional view showing still another one of the conventional field effect type insulated gate transistors.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Single crystal semiconductor layer 1 'Semiconductor region (well) 1a, 1b Main surface of single crystal semiconductor layer 1 Element isolation insulating film 3 Source region 4 Drain region 5 Channel region 6 Offset region 7 Gate electrode 8 Gate insulating film 9, DESCRIPTION OF SYMBOLS 10 Insulating film 9a Flat surface of insulating film 9, 13, 14 Window 23 Source electrode 23 'Source / back gate voltage applying electrode 24 Drain electrode 29 Window 30 Substrate 30' Single crystal semiconductor substrate 31 Conductive layer 41 Single crystal semiconductor Substrate 42 Single crystal semiconductor layer 43 Main surface of single crystal semiconductor layer 42

 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Toshiaki Taniuchi 3-19-2 Nishi Shinjuku, Shinjuku-ku, Tokyo Nippon Telegraph and Telephone Corporation (72) Inventor Yoshihiro Arimoto 4-chome Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture No. 1 in Fujitsu Limited (72) Inventor Akio Ito 4-1-1 Kamikodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture

Claims (3)

[Claims] The semiconductor device includes a single crystal semiconductor layer having first and second main surfaces and a first conductivity type, wherein a single crystal semiconductor layer is formed in the single crystal semiconductor layer from the first main surface side. A source region having a second conductivity type opposite to the first conductivity type and an offset region having a second conductivity type into which an impurity imparting the second conductivity type is introduced at a relatively low concentration are formed therebetween. In order to leave a channel region at a depth, a depth reaching the second main surface is formed, and an impurity imparting a second conductivity type is introduced at a relatively high concentration from the first main surface side. A drain region having a second conductivity type connected to the offset region on a side opposite to the channel region side and formed to a depth reaching a second main surface; 1 on the main surface of the above-mentioned channel via a gate insulating film. A first insulating film is formed so as to face the region, and a first insulating film is formed to cover the gate electrode and the gate insulating film; and a surface of the first insulating film opposite to the single crystal semiconductor layer side Has a flat surface, the first insulating film is bonded to the substrate on the flat surface side, and a second insulating film is formed on a second main surface of the single crystal semiconductor layer. A field effect in which a source electrode connected to the source region or a source / back gate voltage applying electrode connected to the source region and the channel region is formed on the second insulating film; Insulating gate type transistor, wherein the substrate is a single-crystal semiconductor substrate having a second conductivity type into which an impurity imparting a second conductivity type is introduced at a relatively high concentration; The above drain region And a window extending between the single crystal semiconductor substrates is formed, and the window is filled with a conductive layer connected to the drain region and the single crystal semiconductor substrate. Type insulated gate transistor. 2. A semiconductor device having a single crystal semiconductor layer having first and second main surfaces and having a first conductivity type, wherein a single crystal semiconductor layer is formed in the single crystal semiconductor layer from the first main surface side. A source region having a second conductivity type opposite to the first conductivity type and an offset region having a second conductivity type into which an impurity imparting the second conductivity type is introduced at a relatively low concentration are formed therebetween. In order to leave a channel region at a depth reaching the second main surface, an impurity imparting a first conductivity type is introduced at a relatively high concentration from the first main surface side. A drain region having a first conductivity type is formed to a depth reaching the second main surface, which is connected to the offset region on a side opposite to the channel region side, and a first region of the single crystal semiconductor layer is formed. On the main surface of the first channel region, a gate electrode is formed via a gate insulating film. And a first insulating film is formed to cover the gate electrode and the gate insulating film, and a surface of the first insulating film opposite to the single crystal semiconductor layer is formed on the first insulating film. The first insulating film is adhered to a substrate on the flat surface side, and a second insulating film is formed on a second main surface of the single crystal semiconductor layer. A bipolar electrode in which a source electrode connected to the source region or a source / back gate voltage applying electrode connected to the source region and the channel region is formed on the second insulating film; In the insulated gate transistor, the substrate is a single-crystal semiconductor substrate having a first conductivity type into which an impurity imparting the first conductivity type is introduced at a relatively high concentration; The above drain area And a window extending between the single crystal semiconductor substrates is formed, wherein the window is filled with a conductive layer connected to the drain region and the single crystal semiconductor substrate. Insulated gate transistor. 3. A single crystal semiconductor layer having first and second main surfaces and having a first conductivity type, wherein a single crystal semiconductor layer is formed in the single crystal semiconductor layer from the first main surface side. 1
A source region and a rain region having a second conductivity type opposite to the first conductivity type are formed at a depth reaching the second main surface so as to leave a channel region therebetween; A gate electrode is formed on the first main surface so as to face the channel region with a gate insulating film interposed therebetween, and a first insulating film is formed to cover the gate electrode and the gate insulating film. A surface of the first insulating film opposite to the single crystal semiconductor layer side is a flat surface, and the first insulating film is adhered to a substrate on the flat surface side; A second insulating film is formed over a second main surface of the single crystal semiconductor layer, and a source electrode connected to the source region or the source region and the channel region are formed over the second insulating film. Connected source and back gate In a field effect type insulated gate transistor having a pressure applying electrode formed therein, the substrate has a single crystal having a second conductivity type into which an impurity imparting the second conductivity type is introduced at a relatively high concentration. A window extending between the drain region and the single-crystal semiconductor substrate is formed in the first insulating film, and the window is connected to the drain region and the single-crystal semiconductor substrate; Field-effect insulated gate transistor characterized by being filled with a conductive layer.