JPH11176990A - Package for housing semiconductor device - Google Patents

Package for housing semiconductor device

Info

Publication number
JPH11176990A
JPH11176990A JP9339084A JP33908497A JPH11176990A JP H11176990 A JPH11176990 A JP H11176990A JP 9339084 A JP9339084 A JP 9339084A JP 33908497 A JP33908497 A JP 33908497A JP H11176990 A JPH11176990 A JP H11176990A
Authority
JP
Japan
Prior art keywords
insulating
semiconductor element
mgo
magnetic
zno
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP9339084A
Other languages
Japanese (ja)
Other versions
JP3526526B2 (en
Inventor
Kunihide Yomo
邦英 四方
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyocera Corp
Original Assignee
Kyocera Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kyocera Corp filed Critical Kyocera Corp
Priority to JP33908497A priority Critical patent/JP3526526B2/en
Publication of JPH11176990A publication Critical patent/JPH11176990A/en
Application granted granted Critical
Publication of JP3526526B2 publication Critical patent/JP3526526B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15312Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161Cap
    • H01L2924/1615Shape
    • H01L2924/16195Flat cap [not enclosing an internal cavity]

Abstract

PROBLEM TO BE SOLVED: To properly absorb a noise if penetrating in a wiring layer of an insulation board from a wiring conductor of an external electric circuit board, thereby effectively preventing the noise from getting into its semiconductor device to normally operate the semiconductor device for a long time. SOLUTION: The package comprises an insulation board 1 having a semiconductor device mounting part 1a on the top surface and wiring layers 8 led to bottom surface from the mounting part 1a, and cover 2 mounted on the board 1 to seal a semiconductor device mounted on the mounting part. The board 1 is formed by laminating SiO2 -Al2 O3 -MgO-ZnO-B2 O3 crystalline glass- made insulation layer 4, 5, 6, and a lowest insulation layer 4 is a magnetic insulation layer 4a contg. a magnetic material.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、LSI(大規模集
積回路素子)等の半導体素子を収容するための半導体素
子収納用パッケージに関するものである。
The present invention relates to a semiconductor device housing package for housing a semiconductor device such as an LSI (Large Scale Integrated Circuit).

【0002】[0002]

【従来の技術】従来、LSI(大規模集積回路素子)等
の半導体素子を収容する半導体素子収納用パッケージ
は、一般に酸化アルミニウム質焼結体等の電気絶縁材料
から成り、その上面略中央部に半導体素子を収容するた
めの凹部を設けた絶縁基体と、該絶縁基体の凹部周辺か
ら下面にかけて導出されたタングステン、モリブデン、
マンガン等の高融点金属粉末から成る複数個の配線層
と、蓋体とから構成されており、絶縁基体の凹部底面に
半導体素子を搭載収容するとともに半導体素子の各電極
をボンディングワイヤ等の電気的接続手段を介して配線
層に接続させ、しかる後、絶縁基体の上面に蓋体を封止
用の接着材を介して接合させ、絶縁基体と蓋体とから成
る容器内部に半導体素子を気密に収容することによって
製品としての半導体装置が完成する。
2. Description of the Related Art Conventionally, a semiconductor element housing package for housing a semiconductor element such as an LSI (large-scale integrated circuit element) is generally made of an electrically insulating material such as an aluminum oxide sintered body and has a substantially central portion on its upper surface. An insulating base provided with a recess for accommodating a semiconductor element, and tungsten, molybdenum led out from the periphery of the recess to the lower surface of the insulating base;
It consists of a plurality of wiring layers made of a high melting point metal powder such as manganese, and a lid. The semiconductor element is mounted and accommodated on the bottom of the concave portion of the insulating base, and each electrode of the semiconductor element is electrically connected to a bonding wire or the like. It is connected to the wiring layer via the connection means, and thereafter, the lid is bonded to the upper surface of the insulating base via an adhesive for sealing, and the semiconductor element is hermetically sealed inside the container composed of the insulating base and the lid. The semiconductor device as a product is completed by being accommodated.

【0003】かかる半導体装置は絶縁基体の下面に導出
している配線層の一部を外部電気回路基板の配線導体に
接続させることによって半導体素子の各電極が外部電気
回路に接続されることとなり、外部電気回路基板の配線
導体を介して半導体素子の各電極に電気信号が出し入れ
されることになる。
In such a semiconductor device, each electrode of a semiconductor element is connected to an external electric circuit by connecting a part of a wiring layer extending to a lower surface of an insulating base to a wiring conductor of an external electric circuit board. An electric signal is input / output to / from each electrode of the semiconductor element via the wiring conductor of the external electric circuit board.

【0004】[0004]

【発明が解決しようとする課題】しかしながら、近年、
情報処理装置は高性能化が急激に進展し、これに伴って
半導体素子も高速駆動が行われ、ノイズの影響を極めて
受け易いものになってきたこと、従来の半導体素子収納
用パッケージは絶縁基体に設けたタングステンやモリブ
デン等から成る配線層が高調波のノイズを伝搬させ易い
こと等から配線層に外部電気回路基板の配線導体から高
調波のノイズが入り込んだ場合、このノイズがそのまま
配線層を伝搬して半導体素子に入り込み、半導体素子を
誤動作させてしまうという欠点を有していた。
However, in recent years,
Information processing devices have rapidly advanced in performance, with the result that semiconductor devices have been driven at high speeds, making them extremely susceptible to noise. If the wiring layer made of tungsten, molybdenum, etc. provided in the wiring layer easily propagates the harmonic noise, etc., the harmonic noise enters the wiring layer from the wiring conductor of the external electric circuit board. It has a drawback that it propagates into the semiconductor element and causes the semiconductor element to malfunction.

【0005】本発明は、上記欠点に鑑み案出されたもの
で、その目的は、絶縁基体に設けた配線層に外部電気回
路基板の配線導体よりノイズが入り込んだとしてもその
ノイズを良好に吸収し、ノイズがそのまま半導体素子に
入り込むのを有効に防止して半導体素子を長期間にわた
り正常に作動させることができる半導体素子収納用パッ
ケージを提供することにある。
SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned drawbacks, and has as its object to satisfactorily absorb noise even if noise enters from a wiring conductor of an external electric circuit board into a wiring layer provided on an insulating base. It is another object of the present invention to provide a semiconductor element storage package that can effectively prevent noise from directly entering the semiconductor element and can operate the semiconductor element normally for a long period of time.

【0006】[0006]

【課題を解決するための手段】本発明は、上面に半導体
素子が搭載される搭載部を有し、該搭載部より下面にか
けて導出される複数個の配線層を有する絶縁基体と、前
記絶縁基体に取着され、搭載部に搭載される半導体素子
を封止する蓋体とから成る半導体素子収納用パッケージ
であって、前記絶縁基体を複数のSiO2 ーAl2 3
ーMgOーZnOーB2 3 系結晶性ガラスから成る絶
縁層を積層して形成するとともに少なくとも最下層の絶
縁層に磁性材料を含有させて磁性絶縁層としたことを特
徴とするものである。
According to the present invention, there is provided an insulating substrate having a mounting portion on an upper surface on which a semiconductor element is mounted, and a plurality of wiring layers extending from the mounting portion to the lower surface; And a lid for sealing the semiconductor element mounted on the mounting portion, wherein the insulating base is made of a plurality of SiO 2 —Al 2 O 3
It is characterized in that a magnetic insulating layer contain a magnetic material on at least the lowermost insulating layer as well as formed by laminating an insulating layer consisting of over MgO over ZnO over B 2 O 3 based crystalline glass .

【0007】また本発明は、前記磁性絶縁層における磁
性材料の含有量が50〜90重量%であることを特徴と
するものである。
The present invention is also characterized in that the content of the magnetic material in the magnetic insulating layer is 50 to 90% by weight.

【0008】更に本発明は、前記磁性絶縁層に、外添加
で10〜40重量部の無機物フィラーを含有させたこと
を特徴とするものである。
Further, the present invention is characterized in that the magnetic insulating layer contains 10 to 40 parts by weight of an inorganic filler by external addition.

【0009】本発明の半導体素子収納用パッケージによ
れば、上面に半導体素子が搭載される搭載部を有し、該
搭載部より下面にかけて複数個の配線層が被着形成され
ている絶縁基体を複数のSiO2 ーAl2 3 ーMgO
ーZnOーB2 3 系結晶性ガラスから成る絶縁層を積
層して形成するとともに少なくとも最下層の絶縁層に磁
性材料を含有させて磁性絶縁層としたことから外部電気
回路基板の配線導体より配線層にノイズが入り込もうと
してもそのノイズは絶縁基体の最下部に位置する磁性絶
縁層に含有されている磁性材料で熱エネルギーに変換さ
れて吸収され、その結果、ノイズが配線層に入り込んで
半導体素子に伝搬することはなく、半導体素子を常に正
常に作動させることが可能となる。
According to the package for housing a semiconductor element of the present invention, there is provided an insulating substrate having a mounting portion on which a semiconductor element is mounted on an upper surface, and a plurality of wiring layers attached and formed from the mounting portion to a lower surface. Multiple SiO 2 -Al 2 O 3 -MgO
An insulating layer made of crystalline ZnO-B 2 O 3 -based glass is laminated, and at least the lowermost insulating layer contains a magnetic material to form a magnetic insulating layer. Even if noise tries to enter the wiring layer, the noise is converted into thermal energy by the magnetic material contained in the magnetic insulating layer located at the bottom of the insulating base and absorbed, and as a result, the noise enters the wiring layer. It does not propagate to the semiconductor element, and the semiconductor element can always operate normally.

【0010】また本発明の半導体素子収納用パッケージ
によれば、絶縁基体を構成する絶縁層がSiO2 ーAl
2 3 ーMgOーZnOーB2 3 系結晶性ガラスで形
成されており、該SiO2 ーAl2 3 ーMgOーZn
OーB2 3 系結晶性ガラスはその焼成温度が800〜
1050℃と低いことからこの結晶性ガラス中に磁性材
料を含有させて焼成しても磁性材料は磁性を失うことは
なく、ノイズを良好に吸収することが可能となる。
Further, according to the package for housing a semiconductor element of the present invention, the insulating layer constituting the insulating base is made of SiO 2 -Al.
It is made of 2 O 3 —MgO—ZnO—B 2 O 3 based crystalline glass, and the SiO 2 —Al 2 O 3 —MgO—Zn
OB 2 O 3 crystalline glass has a firing temperature of 800-
Since the temperature is as low as 1050 ° C., the magnetic material does not lose its magnetism even when the crystalline glass is mixed with the magnetic material and fired, and the noise can be well absorbed.

【0011】同時にSiO2 ーAl2 3 ーMgOーZ
nOーB2 3 系結晶性ガラスの焼成温度が低いことか
ら銅、銀、金等の融点が低くく、導通抵抗の低い材料か
ら成る配線層を同時焼成によって形成することが可能と
なり、配線層を電気信号が伝搬した際、電気信号に減衰
等が生じるのを有効に防止して半導体素子を正確に作動
させることもできる。
At the same time, SiO 2 —Al 2 O 3 —MgO—Z
Since the firing temperature of the nO—B 2 O 3 crystalline glass is low, it is possible to form a wiring layer made of a material having a low melting point, such as copper, silver, and gold, and a low conduction resistance by simultaneous firing. When an electric signal propagates through the layer, it is possible to effectively prevent attenuation or the like from occurring in the electric signal, and to operate the semiconductor element accurately.

【0012】更に絶縁基体を構成するSiO2 ーAl2
3 ーMgOーZnOーB2 3 系結晶性ガラスに無機
物フィラーを外添加で10〜40重量部の範囲で含有さ
せるとSiO2 ーAl2 3 ーMgOーZnOーB2
3 系結晶性ガラスの機械的強度が強くなり、これによっ
て絶縁基体に外力等が印加されても破損等が発生するの
を有効に防止することができる。
[0012] SiO 2 over Al 2 further constituting the insulating substrate
When an inorganic filler is externally added to the O 3 —MgO—ZnO—B 2 O 3 -based crystalline glass in the range of 10 to 40 parts by weight, SiO 2 —Al 2 O 3 —MgO—ZnO—B 2 O
The mechanical strength of 3 based crystalline glass becomes stronger, whereby it is possible to effectively prevent the damage even if an external force or the like is applied is generated in the insulating base.

【0013】[0013]

【発明の実施の形態】次に本発明を添付図面に基づき詳
細に説明する。図1は本発明の半導体素子収納用パッケ
ージの一実施例を示し、1は絶縁基体、2は蓋体であ
る。この絶縁基体1と蓋体2とで半導体素子を内部に収
容するための容器が構成される。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described in detail with reference to the accompanying drawings. FIG. 1 shows an embodiment of a package for accommodating a semiconductor element according to the present invention, wherein 1 is an insulating base, and 2 is a lid. The insulating base 1 and the lid 2 constitute a container for housing the semiconductor element therein.

【0014】前記絶縁基体1は、その上面中央部に半導
体素子3が載置収容される凹部1aが設けてあり、該凹
部1a底面に半導体素子3が接着材を介して接着固定さ
れる。
The insulating substrate 1 has a recess 1a in the center of the upper surface in which the semiconductor element 3 is placed and accommodated, and the semiconductor element 3 is bonded and fixed to the bottom of the recess 1a via an adhesive.

【0015】前記絶縁基体1は3つのSiO2 ーAl2
3 ーMgOーZnOーB2 3 系結晶性ガラスから成
る絶縁層4、5、6を積層一体化して形成されており、
例えば、SiO2 、Al2 3 、MgO、ZnO、B2
3 に適当な有機溶剤、溶媒、可塑剤等を添加混合して
泥漿状となすとともに、該泥漿物をドクターブレード法
やカレンダーロール法等によりシート状に成形して複数
枚のグリーンシート(生シート)を得、しかる後、前記
グリーンシートに適当な打ち抜き加工を施すとともに所
定の順に上下に積層し、800〜1050℃の温度で焼
成することによって製作される。
The insulating substrate 1 is made of three SiO 2 —Al 2
O 3 and the over MgO over ZnO over B 2 O 3 based dielectric layer 4, 5 and 6 made of crystalline glass is formed by laminating integrally,
For example, SiO 2 , Al 2 O 3 , MgO, ZnO, B 2
O 3 in a suitable organic solvent, solvents, together form a mud漿状was added and mixed plasticizer, a plurality of green sheets (green and formed into a sheet of該泥漿物by a doctor blade method or calendar roll method, etc. After that, the green sheet is manufactured by subjecting the green sheet to an appropriate punching process, stacking the green sheet up and down in a predetermined order, and firing at a temperature of 800 to 1050 ° C.

【0016】また前記絶縁基体1は凹部1aの周囲から
絶縁基体1に設けた貫通孔7を介して下面に導出する複
数個の配線層8が形成されており、該配線層8は内部に
収容する半導体素子3の各電極を外部電気回路に電気的
に接続する作用をなし、配線層8の凹部1a周辺部には
半導体素子3の各電極がボンディングワイヤ等の電気的
接続手段9を介して電気的に接続され、また絶縁基体1
の下面に導出する部位には外部電気回路基板の配線導体
に接続される外部リートピン10がロウ材を介して接合
されている。
The insulating substrate 1 is provided with a plurality of wiring layers 8 extending from the periphery of the concave portion 1a to the lower surface through through holes 7 provided in the insulating substrate 1, and the wiring layers 8 are housed inside. The electrodes of the semiconductor element 3 are electrically connected to an external electric circuit, and the electrodes of the semiconductor element 3 are connected to the periphery of the concave portion 1a of the wiring layer 8 through an electrical connection means 9 such as a bonding wire. Electrically connected to the insulating substrate 1
An external lead pin 10 connected to a wiring conductor of an external electric circuit board is joined to a portion led out to the lower surface of the external electric circuit board via a brazing material.

【0017】前記配線層8は銅、銀、金等の電気抵抗率
が3μΩ・cm以下の金属材料から成り、例えば、銅等
の金属粉末に適当な有機溶剤、溶媒を添加混合して得た
金属ペーストを絶縁基体1となるグリーンシートの上面
及びグリーンシートに孔開け加工により開けた孔内に予
め従来周知のスクリーン印刷法等により所定パターンに
印刷塗布しておくことによって絶縁基体1の凹部周囲か
ら下面にかけて被着形成される。この場合、銅、銀、金
等の金属材料から成る配線層8はSiO2 ーAl2 3
ーMgOーZnOーB2 3 系結晶性ガラスから成る絶
縁基体1の焼成温度が800〜1050℃と低いため、
絶縁基体1の焼成時に金属ペーストの銅や銀等の金属粉
末が気散してしまうことはなく、絶縁基体1と同時焼成
によって絶縁基体1の所定位置に形成することができ
る。
The wiring layer 8 is made of a metal material such as copper, silver, and gold having an electrical resistivity of 3 μΩ · cm or less. For example, the wiring layer 8 is obtained by adding a suitable organic solvent and a solvent to a metal powder such as copper. By printing and applying a metal paste in a predetermined pattern by a well-known screen printing method or the like in advance on the upper surface of the green sheet serving as the insulating substrate 1 and in the holes formed in the green sheet by a perforation process, the periphery of the concave portion of the insulating substrate 1 is formed. To the lower surface. In this case, the wiring layer 8 made of a metal material such as copper, silver, and gold is made of SiO 2 —Al 2 O 3
Since the sintering temperature of the insulating substrate 1 made of —MgO—ZnO—B 2 O 3 crystalline glass is as low as 800 to 1050 ° C.,
When the insulating substrate 1 is fired, metal powder such as copper or silver of the metal paste does not diffuse, and can be formed at a predetermined position on the insulating substrate 1 by simultaneous firing with the insulating substrate 1.

【0018】また前記配線層8を形成する銅、銀、金等
はその電気抵抗率が3μΩ・cm以下と低いことから配
線層8を電気信号が伝搬しても電気信号に減衰等が生じ
るのを有効に防止することができ、その結果、半導体素
子3に対し電気信号を正確に出し入れすることが可能と
なり、半導体素子3を常に正常に作動させることができ
る。
Further, since the electrical resistivity of copper, silver, gold and the like forming the wiring layer 8 is as low as 3 μΩ · cm or less, even if the electric signal propagates through the wiring layer 8, the electric signal is attenuated. Can be effectively prevented, and as a result, it is possible to accurately send and receive electric signals to and from the semiconductor element 3, and the semiconductor element 3 can always be normally operated.

【0019】なお、前記配線層8は銅や銀から成る場
合、その露出表面に耐蝕性に優れる金等をメッキ法によ
り1.0〜20μmの厚みに被着させておくと配線層8
の酸化腐蝕を有効に防止することができるとともに配線
層8とボンディングワイヤ等の電気的接続手段9との接
続及び配線層8への外部リードピン10の接合を強固と
なすことができる。従って、前記配線層8は銅や銀から
成る場合、その露出表面に金等の耐蝕性に優れる金属を
メッキ法により1.0〜20μmの厚みに被着させてお
くことが好ましい。
When the wiring layer 8 is made of copper or silver, gold or the like having excellent corrosion resistance is applied to the exposed surface to a thickness of 1.0 to 20 μm by a plating method.
Can be effectively prevented, and the connection between the wiring layer 8 and the electrical connection means 9 such as a bonding wire and the bonding of the external lead pins 10 to the wiring layer 8 can be strengthened. Therefore, when the wiring layer 8 is made of copper or silver, it is preferable that a metal having excellent corrosion resistance such as gold is applied to the exposed surface to a thickness of 1.0 to 20 μm by plating.

【0020】また前記絶縁基体1の下面において配線層
8に接合されている外部リードピン10は鉄ーニッケル
ーコバルト合金や鉄ーニッケル合金、銅等の金属材料か
ら成り、半導体素子3の各電極を外部電気回路に電気的
に接続する用をなす。
The external lead pins 10 joined to the wiring layer 8 on the lower surface of the insulating base 1 are made of a metal material such as an iron-nickel-cobalt alloy, an iron-nickel alloy, or copper. Used to electrically connect to an electric circuit.

【0021】前記外部リードピン10は鉄ーニッケルー
コバルト合金等のインゴット(塊)を圧延加工法や打ち
抜き加工法等、従来周知の金属加工法を採用することに
よって所定形状に形成される。
The external lead pin 10 is formed into a predetermined shape by employing a conventionally known metal working method such as a rolling method or a punching method for an ingot (a lump) such as an iron-nickel-cobalt alloy.

【0022】前記外部リードピン10は例えば、融点が
500℃以下の金属材料からなるロウ材、具体的には、
10〜50重量%のインジウムまたは錫と、10〜70
重量%の銀と、10〜75重量%のアンチモンと、10
重量%以下の銅とから成る合金、15〜25重量%の錫
と、75〜85重量%の金とから成る合金、10〜15
重量%のゲルマニウムと、85〜90重量%の金とから
成る合金、鉛と、錫、インジウム、アンチモン、ビスマ
スの少なくとも1種との合金等を使用することによって
絶縁基体1の下面で配線層8に接合される。
The external lead pin 10 is made of, for example, a brazing material made of a metal material having a melting point of 500 ° C. or less, specifically,
10 to 50% by weight of indium or tin, 10 to 70%
Weight percent silver, 10 to 75 weight percent antimony,
Alloy consisting of less than 15% by weight of copper; alloy consisting of 15 to 25% by weight of tin and 75 to 85% by weight of gold;
The wiring layer 8 is formed on the lower surface of the insulating substrate 1 by using an alloy composed of germanium of 85% by weight and 85 to 90% by weight of gold, an alloy of lead and at least one of tin, indium, antimony, and bismuth. Joined to.

【0023】前記融点が500℃以下の金属材料からな
るロウ材を使用して外部リードピン10を絶縁基体1の
下面で配線層8に接合させた場合、ロウ付けの際のロウ
材を加熱溶融させる温度が低く、ロウ材の加熱溶融の熱
によって絶縁基体1が大きく変形することはなく、これ
によって絶縁基体1に設けられている配線層8に断線等
を招来するのを有効に防止することができる。
When the external lead pins 10 are joined to the wiring layer 8 on the lower surface of the insulating base 1 using a brazing material made of a metal material having a melting point of 500 ° C. or less, the brazing material at the time of brazing is heated and melted. The temperature is low, and the insulating base 1 is not significantly deformed by the heat of heating and melting the brazing material. This effectively prevents the wiring layer 8 provided on the insulating base 1 from being disconnected or the like. it can.

【0024】かくして、上述の半導体素子収納用パッケ
ージよれば、絶縁基体1の凹部1a内に半導体素子3を
接着材を介して搭載固定するとともに半導体素子3の各
電極をボンディングワイヤ等の電気的接続手段9を介し
て配線層8に接続し、しかる後、絶縁基体1の上面に蓋
体2をガラス、樹脂、ロウ材等の封止部材を介して接合
させ、絶縁基体1と蓋体2とから成る容器内部に半導体
素子3を気密に封止することによって製品としての半導
体装置となる。
Thus, according to the above-mentioned package for accommodating a semiconductor element, the semiconductor element 3 is mounted and fixed in the concave portion 1a of the insulating base 1 via an adhesive, and each electrode of the semiconductor element 3 is electrically connected with a bonding wire or the like. The lid 2 is connected to the wiring layer 8 via the means 9 and then the lid 2 is joined to the upper surface of the insulating base 1 via a sealing member such as glass, resin, brazing material, or the like. A semiconductor device as a product is obtained by hermetically sealing the semiconductor element 3 inside the container made of.

【0025】かかる半導体装置は外部リードピン10を
外部電気回路基板の配線導体(不図示)に半田等を介し
て接続すれば、容器内部に収容する半導体素子3の各電
極は外部リードピン10、配線層8及び電気的接続手段
9を介して外部電気回路基板の配線導体に接続されるこ
ととなり、半導体素子3と外部電気回路基板の配線導体
との間で電気信号の出し入れが可能となる。
In this semiconductor device, when the external lead pins 10 are connected to wiring conductors (not shown) of an external electric circuit board via solder or the like, the electrodes of the semiconductor element 3 housed in the container are connected to the external lead pins 10 and the wiring layer. The connection between the semiconductor element 3 and the wiring conductor of the external electric circuit board becomes possible through the connection to the wiring conductor of the external electric circuit board via the electric connection means 8 and the electric connection means 9.

【0026】本発明においては絶縁基体1を構成する各
絶縁層4、5、6をSiO2 ーAl2 3 ーMgOーZ
nOーB2 3 系結晶性ガラスで形成することが重要で
ある。
In the present invention, each of the insulating layers 4, 5, and 6 constituting the insulating base 1 is made of SiO 2 —Al 2 O 3 —MgO—Z
It is important to form the nO—B 2 O 3 crystalline glass.

【0027】このSiO2 ーAl2 3 ーMgOーZn
OーB2 3 系結晶性ガラスは、例えば、SiO2 :4
0〜46重量%、Al2 3 :25〜30重量%、Mg
O:8〜13重量%、ZnO:6〜9重量%、B
2 3 :8〜11重量%で形成されている。
This SiO 2 —Al 2 O 3 —MgO—Zn
OB 2 O 3 crystalline glass is, for example, SiO 2 : 4
0-46 wt%, Al 2 O 3: 25~30 wt%, Mg
O: 8 to 13% by weight, ZnO: 6 to 9% by weight, B
2 O 3 : formed at 8 to 11% by weight.

【0028】前記SiO2 ーAl2 3 ーMgOーZn
OーB2 3 系結晶性ガラスは、焼成時にガーナイト
(ZnO・Al2 3 )、コージェライト(2MgO・
2Al2 3 )、スピネル型結晶相(MgO・Al2
3 、ZnO・Al2 3 )等の結晶相を生成するが、こ
れらの結晶相の生成により絶縁基体1の強度が向上する
という性質を持っている。
The above-mentioned SiO 2 —Al 2 O 3 —MgO—Zn
The OB 2 O 3 -based crystalline glass is made of garnet (ZnO.Al 2 O 3 ), cordierite (2MgO.
2Al 2 O 3), spinel-type crystal phase (MgO · Al 2 O
3 , a crystal phase such as ZnO.Al 2 O 3 ) is generated, and the generation of these crystal phases has the property that the strength of the insulating substrate 1 is improved.

【0029】前記SiO2 ーAl2 3 ーMgOーZn
OーB2 3 系結晶性ガラスはその焼成温度が800〜
1050℃と低いことから、配線層8を銅、銀、金等の
融点が低くく、導通抵抗の低い材料としても絶縁基体1
と同時焼成によって形成することが可能となり、配線層
8を電気信号が伝搬した際、電気信号に減衰等が生じる
のを有効に防止して半導体素子3を正確に作動させるこ
とができる。
The above SiO 2 -Al 2 O 3 -MgO-Zn
OB 2 O 3 crystalline glass has a firing temperature of 800-
Since the wiring layer 8 has a low melting point, such as copper, silver, or gold, and a low conduction resistance because of its low temperature of 1050 ° C.,
When the electric signal propagates through the wiring layer 8, it is possible to effectively prevent the electric signal from attenuating and the like, and to operate the semiconductor element 3 accurately.

【0030】また前記SiO2 ーAl2 3 ーMgOー
ZnOーB2 3 系結晶性ガラスはその比誘電率が約5
(室温1MHz)と低いことから、絶縁基体1に形成し
た配線層8に電気信号を伝搬させても伝搬遅延を招来す
ることはなく、その結果、配線層8に高速で電気信号を
伝搬させることが可能となる。
The SiO 2 —Al 2 O 3 —MgO—ZnO—B 2 O 3 crystalline glass has a relative dielectric constant of about 5
(At room temperature of 1 MHz), even if the electric signal is propagated to the wiring layer 8 formed on the insulating base 1, no propagation delay is caused, and as a result, the electric signal is propagated to the wiring layer 8 at high speed. Becomes possible.

【0031】なお、前記SiO2 ーAl2 3 ーMgO
ーZnOーB2 3 系結晶性ガラスは、SiOの量が4
0重量%未満、或いは46重量%を超えるとSiO2
Al2 3 ーMgOーZnOーB2 3 系結晶性ガラス
の焼成温度が高いものとなって銅等の金属材料からなる
配線層8を同時に焼成するのが困難となる。従って、S
iO2 の量は40〜46重量%の範囲としておくことが
好ましい。
The above SiO 2 -Al 2 O 3 -MgO
Over ZnO over B 2 O 3 based crystalline glass, the amount of SiO 4
If the amount is less than 0% by weight or more than 46% by weight, the firing temperature of the SiO 2 —Al 2 O 3 —MgO—ZnO—B 2 O 3 based crystalline glass becomes high, and the wiring layer is made of a metal material such as copper. 8 becomes difficult to fire simultaneously. Therefore, S
Preferably, the amount of iO 2 is in the range of 40-46% by weight.

【0032】またAl2 3 の量が25重量%未満、或
いは30重量%を超えるとSiO2ーAl2 3 ーMg
OーZnOーB2 3 系結晶性ガラスの焼成温度が高い
ものとなって銅等の金属材料からなる配線層8を同時に
焼成するのが困難となる。従って、Al2 3 の量は2
5〜30重量%の範囲としておくことが好ましい。
When the amount of Al 2 O 3 is less than 25% by weight or more than 30% by weight, SiO 2 —Al 2 O 3 —Mg
The sintering temperature of the O—ZnO—B 2 O 3 -based crystalline glass becomes high, and it becomes difficult to simultaneously sinter the wiring layer 8 made of a metal material such as copper. Therefore, the amount of Al 2 O 3 is 2
It is preferable to set the range of 5 to 30% by weight.

【0033】またMgOの量が8重量%未満となると焼
成によってSiO2 ーAl2 3 ーMgOーZnOーB
2 3 系結晶性ガラスからなる絶縁基体1を製作する
際、生成するコージェライト(2MgO・2Al
2 3 )の量が少なくなって絶縁基体1の強度を大きく
向上させることができず、また13重量%を超えるとS
iO2ーAl2 3 ーMgOーZnOーB2 3 系結晶
性ガラスの焼成温度が高いものとなって銅等の金属材料
からなる配線層8を同時に焼成するのが困難となる。従
って、MgOの量は8〜13重量%の範囲としておくこ
とが好ましい。
When the amount of MgO is less than 8% by weight, the sintering is performed to form SiO 2 —Al 2 O 3 —MgO—ZnO—B.
The cordierite (2MgO.2Al) formed when the insulating substrate 1 made of 2 O 3 -based crystalline glass is produced.
The amount of 2 O 3 ) is small and the strength of the insulating substrate 1 cannot be greatly improved.
iO 2 over Al 2 O 3 that is baked over MgO over ZnO over B 2 O 3 based wiring layer 8 made of a metal material such as copper is as firing temperature of the crystallizable glass is high at the same time difficult. Therefore, the amount of MgO is preferably set in the range of 8 to 13% by weight.

【0034】またZnOの量が6重量%未満となると焼
成によってSiO2 ーAl2 3 ーMgOーZnOーB
2 3 系結晶性ガラスからなる絶縁基体1を製作する
際、生成するガーナイト(ZnO・Al2 3 )の量が
少なくなって絶縁基体1の強度を大きく向上させること
ができず、また9重量%を超えるとSiO2 ーAl2
3 ーMgOーZnOーB2 3 系結晶性ガラスの焼成温
度が高いものとなって銅等の金属材料からなる配線層8
を同時に焼成するのが困難となる。従って、ZnOの量
は6〜9重量%の範囲としておくことが好ましい。
If the amount of ZnO is less than 6% by weight, the material is calcined to form SiO 2 —Al 2 O 3 —MgO—ZnO—B
When manufacturing the insulating substrate 1 made of 2 O 3 -based crystalline glass, the amount of garnet (ZnO.Al 2 O 3 ) generated is small, and the strength of the insulating substrate 1 cannot be greatly improved. If the content exceeds% by weight, SiO 2 —Al 2 O
3 over MgO over ZnO over B 2 O 3 system firing temperature of the crystalline glass is made of a metal material such as copper becomes high wiring layer 8
At the same time. Therefore, the amount of ZnO is preferably set in the range of 6 to 9% by weight.

【0035】またB2 3 の量が8重量%未満となると
焼成によってSiO2 ーAl2 3ーMgOーZnOー
2 3 系結晶性ガラスからなる絶縁基体1を製作する
際、ガーナイト(ZnO・Al2 3 )、コージェライ
ト(2MgO・2Al2 3)、スピネル型結晶相(M
gO・Al2 3 、ZnO・Al2 3 )等の結晶相が
過剰に生成され、絶縁基体1が多孔質のものとなって容
器の気密の信頼性が大きく低下してしまい、また11重
量%を超えると耐薬品性が大きく低下し、半導体阻止収
納用パッケージの信頼性が低下してしまう。従って、B
2 3 の量は8〜11重量%の範囲としておくことが好
ましい。
Further in fabricating the insulating base 1, the amount of B 2 O 3 is made of SiO 2 over Al 2 O 3 over MgO over ZnO over B 2 O 3 based crystalline glass by firing less than 8 wt%, gahnite (ZnO · Al 2 O 3) , cordierite (2MgO · 2Al 2 O 3) , spinel-type crystal phase (M
gO.Al 2 O 3 , ZnO.Al 2 O 3 ), etc., are excessively generated, and the insulating substrate 1 becomes porous, so that the reliability of hermetic sealing of the container is greatly reduced. If the content is more than 10% by weight, the chemical resistance is greatly reduced, and the reliability of the semiconductor blocking package is reduced. Therefore, B
Preferably, the amount of 2 O 3 is in the range of 8 to 11% by weight.

【0036】また本発明においては、前記絶縁基体1を
構成する絶縁層4、5、6のうち少なくとも最下層の絶
縁層4に磁性材料を含有させて磁性絶縁層4aとしてお
くことが重要である。
In the present invention, it is important that at least the lowermost one of the insulating layers 4, 5, and 6 constituting the insulating base 1 contains a magnetic material to form the magnetic insulating layer 4 a. .

【0037】前記絶縁基体1の最下層を磁性絶縁層4a
としておく外部リードピン10を外部電気回路基板の配
線導体に接続させ、半導体素子3と外部電気回路との間
で電気信号の出し入れをする場合、外部電気回路基板の
配線導体より配線層8にノイズが入り込もうとしてもそ
のノイズは絶縁基体1の最下層に位置する磁性絶縁層4
aに含有されている磁性材料で熱エネルギーに変換され
吸収されて配線層8に入り込むことはなく、その結果、
ノイズが配線層8を伝搬し半導体素子3に入り込みこと
は殆どなく、これによって半導体素子3を常に正常に作
動させることが可能となる。
The lowermost layer of the insulating substrate 1 is a magnetic insulating layer 4a.
When the external lead pins 10 are connected to the wiring conductor of the external electric circuit board and electric signals are taken in and out between the semiconductor element 3 and the external electric circuit, noise is generated in the wiring layer 8 by the wiring conductor of the external electric circuit board. Even if the noise enters, the noise is generated by the magnetic insulating layer 4 located at the bottom
a is not converted into heat energy by the magnetic material contained in a and absorbed and does not enter the wiring layer 8, and as a result,
The noise hardly propagates through the wiring layer 8 and enters the semiconductor element 3, so that the semiconductor element 3 can always operate normally.

【0038】なお、前記磁性絶縁層4aは、SiO2
Al2 3 ーMgOーZnOーB2O3 系結晶性ガラスの
焼成温度が800〜1050℃と低いことから焼成時、
磁性材料の磁性が失われることはなく、これによって配
線層8に入り込んだノイズを良好に吸収することが可能
となる。
[0038] Incidentally, the magnetic insulating layer 4a is during firing since the firing temperature of the SiO 2 chromatography Al 2 O 3 over MgO over ZnO over B 2 O 3 based crystalline glass is 800 to 1050 ° C. and lower,
The magnetism of the magnetic material is not lost, so that noise entering the wiring layer 8 can be favorably absorbed.

【0039】前記磁性絶縁層4aに含有される磁性材料
としてはZnFe2 4 、MnFe2 4 、FeFe2
4 、CoFe2 4 、NiFe2 4 、CuFe2
4 の少なくとも1種が好適に使用され、例えば、焼成に
よって絶縁層4となるグリーンシートに、ZnFe2
4 、MnFe2 4 、FeFe2 4 、CoFe
2 4 、NiFe2 4 、CuFe2 4 の少なくとも
1種から成る磁性粉末を添加含有させておくことによっ
て絶縁層4内に含有され、磁性絶縁層4aとなる。
The magnetic material contained in the magnetic insulating layer 4a is ZnFe 2 O 4 , MnFe 2 O 4 , FeFe 2
O 4 , CoFe 2 O 4 , NiFe 2 O 4 , CuFe 2 O
4 is preferably used. For example, ZnFe 2 O is added to a green sheet that becomes the insulating layer 4 by firing.
4 , MnFe 2 O 4 , FeFe 2 O 4 , CoFe
By adding and containing a magnetic powder composed of at least one of 2 O 4 , NiFe 2 O 4 and CuFe 2 O 4 , the magnetic powder is contained in the insulating layer 4 and becomes a magnetic insulating layer 4 a.

【0040】また前記磁性絶縁層4aは磁性材料が90
重量%を超える、言い換えるとSiO2 ーAl2 3
MgOーZnOーB2 3 系結晶性ガラスの量が10重
量%未満となるとSiO2 ーAl2 3 ーMgOーZn
OーB2 3 系結晶性ガラスの焼成温度が高いものとな
って銅等の金属材料からなる配線層8を同時に焼成する
のが困難となり、また磁性材料が50重量%未満、言い
換えるとSiO2 ーAl2 3 ーMgOーZnOーB2
3 系結晶性ガラスの量が50重量%を超えると、外部
電気回路基板の配線導体より配線層8にノイズが入り込
むのを良好に防止することができず、半導体素子3に誤
動作を起こさせてしまう。従って、前記磁性絶縁層4a
は磁性材料の量を50〜90重量%の範囲にしておくこ
とが好ましい。
The magnetic insulating layer 4a is made of a magnetic material of 90%.
When the content of the crystalline glass is more than 10% by weight, in other words, when the amount of the SiO 2 —Al 2 O 3 —MgO—ZnO—B 2 O 3 based crystalline glass is less than 10% by weight, SiO 2 —Al 2 O 3 —MgO—Zn
The sintering temperature of the OB 2 O 3 -based crystalline glass becomes high, making it difficult to simultaneously sinter the wiring layer 8 made of a metal material such as copper, and the magnetic material is less than 50% by weight, in other words, SiO 2 2 -Al 2 O 3 -MgO-ZnO-B 2
When the amount of the O 3 -based crystalline glass exceeds 50% by weight, it is not possible to prevent the noise from entering the wiring layer 8 from the wiring conductor of the external electric circuit board satisfactorily, causing the semiconductor element 3 to malfunction. Would. Therefore, the magnetic insulating layer 4a
It is preferable that the amount of the magnetic material be in the range of 50 to 90% by weight.

【0041】更に前記磁性材料はその粒径が0.5μm
未満となると焼成によってSiO2ーAl2 3 ーMg
OーZnOーB2 3 系結晶性ガラスからなる絶縁基体
1を製作する際、SiO2 ーAl2 3 ーMgOーZn
OーB2 3 系結晶性ガラスとの反応が進行じ磁性材料
の残存率が低下してノイズを効果的に吸収することがで
きなくなり、また10μmを超えるとSiO2 ーAl2
3 ーMgOーZnOーB2 3 系結晶性ガラスの焼成
温度が高いものとなって銅等の金属材料からなる配線層
8と同時に焼成するのが困難となる。従って、前記磁性
材料はその粒径を0.5μm〜10μmの範囲としてお
くことが好ましい。
Further, the magnetic material has a particle size of 0.5 μm.
If it is less than the above, firing will result in SiO 2 --Al 2 O 3 --Mg
When manufacturing the insulating substrate 1 made of O—ZnO—B 2 O 3 based crystalline glass, SiO 2 —Al 2 O 3 —MgO—Zn
The reaction with the OB 2 O 3 -based crystalline glass progresses, and the residual ratio of the magnetic material decreases, making it impossible to effectively absorb noise. If it exceeds 10 μm, SiO 2 -Al 2
O 3 over the firing temperature of MgO over ZnO over B 2 O 3 based crystalline glass becomes high and becomes to difficult to firing simultaneously with the wiring layer 8 made of a metal material such as copper. Therefore, the magnetic material preferably has a particle size in the range of 0.5 μm to 10 μm.

【0042】また更に前記絶縁基体1を構成する磁性絶
縁層4及び絶縁層5、6はその内部に無機物フィラー,
具体的にはアルミナ、シリカ、窒化珪素、窒化アルミニ
ウム等の粉末を外添加で10〜40重量部添加含有させ
ておくと機械的強度が大幅に向上し、外力印加によって
破損等を招来するのが有効に防止される。従って、絶縁
基体1の機械的強度を向上させ、外力印加によって破損
等を招来しないようにするのはSiO2 ーAl2 3
MgOーZnOーB2 3 系結晶性ガラスから成る磁性
絶縁層4及び絶縁層5、6に無機物フィラーを外添加で
10〜40重量部添加含有させておくことが好ましい。
Further, the magnetic insulating layer 4 and the insulating layers 5 and 6 constituting the insulating base 1 have an inorganic filler,
Specifically, when 10 to 40 parts by weight of powder of alumina, silica, silicon nitride, aluminum nitride, etc. is added and added, the mechanical strength is greatly improved, and application of an external force may cause damage or the like. Effectively prevented. Therefore, the mechanical strength of the insulating substrate 1 is improved, and the application of an external force so as not to cause breakage or the like is made of a magnetic insulating material made of SiO 2 —Al 2 O 3 —MgO—ZnO—B 2 O 3 crystalline glass. It is preferable to add 10 to 40 parts by weight of an inorganic filler to the layer 4 and the insulating layers 5 and 6 by external addition.

【0043】前記絶縁基体1を構成する磁性絶縁層4及
び絶縁層5、6に無機物フィラーを添加含有させる場
合、無機物フィラーの粒径を0.5〜5μmの範囲とし
ておくと無機物フィラーがガラスセラミック焼結体中に
均一に分散含有されて磁性絶縁層4及び絶縁層5、6か
ら成る絶縁基体1の機械的強度を均一に向上させること
ができる。従って、前記無機物フィラーはその粒径を
0.5〜5μmの範囲としておくことが好ましい。
When the magnetic insulating layer 4 and the insulating layers 5 and 6 constituting the insulating substrate 1 contain an inorganic filler, the inorganic filler may be made of glass ceramic if the particle size of the inorganic filler is in the range of 0.5 to 5 μm. The mechanical strength of the insulating base 1 composed of the magnetic insulating layer 4 and the insulating layers 5 and 6 can be uniformly improved by being uniformly dispersed and contained in the sintered body. Therefore, it is preferable that the particle diameter of the inorganic filler be in the range of 0.5 to 5 μm.

【0044】なお、本発明は上述の実施例に限定される
ものではなく、本発明の要旨を逸脱しない範囲であれば
種々の変更は可能であり、例えば、上述の実施例におい
ては外部リードピン10を外部電気回路基板の配線導体
に接続させることによって半導体素子3の各電極が外部
電気回路に接続されるようになっているが、外部リード
ピンを設けず、絶縁基体1の下面に導出する配線層8を
そのまま外部電気回路基板の配線導体に接続させるよう
にしてもよい。
It should be noted that the present invention is not limited to the above-described embodiment, and various changes can be made without departing from the scope of the present invention. Is connected to a wiring conductor of an external electric circuit board, so that each electrode of the semiconductor element 3 is connected to the external electric circuit. 8 may be directly connected to the wiring conductor of the external electric circuit board.

【0045】また上述の実施例では絶縁基体1を3つの
絶縁層4,5,6で形成したが、これを2つの絶縁層で
形成しても、また4つ以上の絶縁層で形成してもよい。
In the above embodiment, the insulating base 1 is formed of three insulating layers 4, 5, and 6. However, the insulating base 1 may be formed of two insulating layers or may be formed of four or more insulating layers. Is also good.

【0046】更に上述の実施例では絶縁基体1の最下層
の絶縁層4のみを磁性絶縁層4aとしたが、全ての絶縁
層に磁性材料を含有させて磁性絶縁層としてもよい。
Furthermore, in the above-described embodiment, only the lowermost insulating layer 4 of the insulating base 1 is the magnetic insulating layer 4a. However, a magnetic insulating layer may be formed by including a magnetic material in all the insulating layers.

【0047】[0047]

【発明の効果】本発明の半導体素子収納用パッケージに
よれば、上面に半導体素子が搭載される搭載部を有し、
該搭載部より下面にかけて複数個の配線層が被着形成さ
れている絶縁基体を複数のSiO2 ーAl2 3 ーMg
OーZnOーB2 3 系結晶性ガラスから成る絶縁層を
積層して形成するとともに少なくとも最下層の絶縁層に
磁性材料を含有させて磁性絶縁層としたことから外部電
気回路基板の配線導体より配線層にノイズが入り込もう
としてもそのノイズは絶縁基体の最下部に位置する磁性
絶縁層に含有されている磁性材料で熱エネルギーに変換
されて吸収され、その結果、ノイズが配線層に入り込ん
で半導体素子に伝搬することはなく、半導体素子を常に
正常に作動させることが可能となる。
According to the semiconductor device housing package of the present invention, the semiconductor device has a mounting portion on which the semiconductor device is mounted on the upper surface,
A plurality of SiO 2 —Al 2 O 3 —Mg are formed on the insulating substrate, on which a plurality of wiring layers are formed from the mounting portion to the lower surface.
O over ZnO over B 2 O 3 system to contain a magnetic material on at least the lowermost insulating layer wiring conductor of the external electric circuit board since it has a magnetic insulating layer with an insulating layer formed by stacking comprising a crystal glass Even if noise is more likely to enter the wiring layer, the noise is converted into thermal energy by the magnetic material contained in the magnetic insulating layer located at the bottom of the insulating base and absorbed, and as a result, the noise enters the wiring layer. Therefore, the semiconductor device can always be normally operated without propagating to the semiconductor device.

【0048】また本発明の半導体素子収納用パッケージ
によれば、絶縁基体を構成する絶縁層がSiO2 ーAl
2 3 ーMgOーZnOーB2 3 系結晶性ガラスで形
成されており、該SiO2 ーAl2 3 ーMgOーZn
OーB2 3 系結晶性ガラスはその焼成温度が850〜
1000℃と低いことからこの結晶性ガラス中に磁性材
料を含有させて焼成しても磁性材料は磁性を失うことは
なく、ノイズを良好に吸収することが可能となる。
Further, according to the package for housing a semiconductor element of the present invention, the insulating layer constituting the insulating base is made of SiO 2 -Al.
It is made of 2 O 3 —MgO—ZnO—B 2 O 3 based crystalline glass, and the SiO 2 —Al 2 O 3 —MgO—Zn
OB 2 O 3 crystalline glass has a firing temperature of 850 to 850.
Since the temperature is as low as 1000 ° C., the magnetic material does not lose its magnetism even if the crystalline material is mixed with the magnetic material and fired, so that noise can be favorably absorbed.

【0049】同時にSiO2 ーAl2 3 ーMgOーZ
nOーB2 3 系結晶性ガラスの焼成温度が低いことか
ら銅、銀、金等の融点が低くく、導通抵抗の低い材料か
ら成る配線層を同時焼成によって形成することが可能と
なり、配線層を電気信号が伝搬した際、電気信号に減衰
等が生じるのを有効に防止して半導体素子を正確に作動
させることもできる。
Simultaneously, SiO 2 —Al 2 O 3 —MgO—Z
Since the firing temperature of the nO—B 2 O 3 crystalline glass is low, it is possible to form a wiring layer made of a material having a low melting point, such as copper, silver, and gold, and a low conduction resistance by simultaneous firing. When an electric signal propagates through the layer, it is possible to effectively prevent attenuation or the like from occurring in the electric signal, and to operate the semiconductor element accurately.

【0050】更に絶縁基体を構成するSiO2 ーAl2
3 ーMgOーZnOーB2 3 系結晶性ガラスに無機
物フィラーを外添加で10〜40重量部の範囲で含有さ
せるとSiO2 ーAl2 3 ーMgOーZnOーB2
3 系結晶性ガラスの機械的強度が強くなり、これによっ
て絶縁基体に外力等が印加されても破損等が発生するの
を有効に防止することができる。
The SiO 2 chromatography Al 2 further constituting the insulating substrate
When an inorganic filler is externally added to the O 3 —MgO—ZnO—B 2 O 3 -based crystalline glass in the range of 10 to 40 parts by weight, SiO 2 —Al 2 O 3 —MgO—ZnO—B 2 O
The mechanical strength of 3 based crystalline glass becomes stronger, whereby it is possible to effectively prevent the damage even if an external force or the like is applied is generated in the insulating base.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の半導体素子収納用パッケージの一実施
例を示す断面図である。
FIG. 1 is a cross-sectional view showing one embodiment of a semiconductor element storage package according to the present invention.

【符号の説明】[Explanation of symbols]

1・・・・・・絶縁基体 2・・・・・・蓋体 3・・・・・・半導体素子 4、5、6・・絶縁層 4a・・・・・磁性絶縁層 DESCRIPTION OF SYMBOLS 1 ... Insulating base 2 ... Lid 3 ... Semiconductor element 4, 5, 6 ... Insulating layer 4a ... Magnetic insulating layer

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】上面に半導体素子が搭載される搭載部を有
し、該搭載部より下面にかけて導出される複数個の配線
層を有する絶縁基体と、前記絶縁基体に取着され、搭載
部に搭載される半導体素子を封止する蓋体とから成る半
導体素子収納用パッケージであって、前記絶縁基体を複
数のSiO2 ーAl2 3 ーMgOーZnOーB2 3
系結晶性ガラスから成る絶縁層を積層して形成するとと
もに少なくとも最下層の絶縁層に磁性材料を含有させて
磁性絶縁層としたことを特徴とする半導体素子収納用パ
ッケージ。
An insulating base having a plurality of wiring layers extending from the mounting portion to a lower surface; and an insulating base attached to the insulating base, the mounting portion being provided on the mounting portion. A package for enclosing a semiconductor element to be mounted, comprising a lid for sealing a semiconductor element to be mounted, wherein the insulating base is made of a plurality of SiO 2 —Al 2 O 3 —MgO—ZnO—B 2 O 3
A package for housing a semiconductor element, wherein a magnetic insulating layer is formed by laminating insulating layers made of a crystalline glass and at least a lowermost insulating layer contains a magnetic material.
【請求項2】前記磁性絶縁層における磁性材料の含有量
が50〜90重量%であることを特徴とする請求項1に
記載の半導体素子収納用パッケージ。
2. The package according to claim 1, wherein the content of the magnetic material in the magnetic insulating layer is 50 to 90% by weight.
【請求項3】前記磁性絶縁層に、外添加で10〜40重
量部の無機物フィラーを含有させたことを特徴とする請
求項1又は2に記載の半導体素子収納用パッケージ。
3. The package according to claim 1, wherein the magnetic insulating layer contains 10 to 40 parts by weight of an inorganic filler by external addition.
JP33908497A 1997-12-09 1997-12-09 Package for storing semiconductor elements Expired - Fee Related JP3526526B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP33908497A JP3526526B2 (en) 1997-12-09 1997-12-09 Package for storing semiconductor elements

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP33908497A JP3526526B2 (en) 1997-12-09 1997-12-09 Package for storing semiconductor elements

Publications (2)

Publication Number Publication Date
JPH11176990A true JPH11176990A (en) 1999-07-02
JP3526526B2 JP3526526B2 (en) 2004-05-17

Family

ID=18324112

Family Applications (1)

Application Number Title Priority Date Filing Date
JP33908497A Expired - Fee Related JP3526526B2 (en) 1997-12-09 1997-12-09 Package for storing semiconductor elements

Country Status (1)

Country Link
JP (1) JP3526526B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100377472B1 (en) * 1999-12-10 2003-03-26 앰코 테크놀로지 코리아 주식회사 semiconductor package and its manufacturing method
KR100377470B1 (en) * 1999-12-10 2003-03-26 앰코 테크놀로지 코리아 주식회사 semiconductor package

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100377472B1 (en) * 1999-12-10 2003-03-26 앰코 테크놀로지 코리아 주식회사 semiconductor package and its manufacturing method
KR100377470B1 (en) * 1999-12-10 2003-03-26 앰코 테크놀로지 코리아 주식회사 semiconductor package

Also Published As

Publication number Publication date
JP3526526B2 (en) 2004-05-17

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