JPH11176978A - Semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve noise immunity and resistance to latch-up. SOLUTION: An integrated circuit chip 1, in which an integrated circuit is formed, is mounted on a package substrate 22 to configure a chip scale package CSP. A side of the integrated circuit chip 1 to which the integrated circuit is integrated is directed downward. A conductive metal part 3 is stuck on the opposite side of the integrated circuit chip to the side which the integrated circuit integrated thereto, while having conductivity with respect to a semiconductor substrate 10. A current hardly flows to the semiconductor substrate 10 due to internal causes or due to external disturbances through the presence of the conductive metallic plate 3. Then a potential distribution tends to be hardly generated resulting from of a voltage difference unexpectedly.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a method of mounting an integrated circuit chip on which an integrated circuit is formed by sequentially laminating wiring layers on a semiconductor substrate on a substrate on which a user's circuit is formed. The present invention relates to a semiconductor integrated circuit mounted on a package substrate such that a surface on which an integrated circuit is formed is on the lower side, and more particularly to a semiconductor integrated circuit capable of improving noise resistance and latch-up resistance. .

[0002]

2. Description of the Related Art CSP (chip scale package)
P (dual inline package) or PGA (pin grid arra
Compared to y), it has a small area, a thin and small external shape, and a small mounting area and volume. For this reason, it is effective for miniaturization of equipment to be used.

The CSP is roughly classified into a flip type and a non-flip type according to a mounting method.

First, in a flip-type CSP integrated circuit chip 1, as shown in FIG. 1, for example, an integrated circuit is formed on a semiconductor substrate 10 by sequentially laminating wiring layers. When wiring is drawn out from the integrated circuit to the outside, the wiring is connected to the solder bump 16 by the drawing wiring layer 14. Here, in FIG. 1, reference numeral 12 denotes an insulating layer.

[0005] As shown in FIG. 2, such an integrated circuit chip 1 is mounted on a package substrate 22 with its front and back turned to be a CSP. That is, when the integrated circuit chip 1 is mounted on the substrate 5 on which the circuit of the user is formed, the integrated circuit chip 1 is inverted so that the surface on which the integrated circuit is formed is on the lower side, and the integrated circuit chip 1 is mounted on the package substrate 22. I have.
The mounting is performed by melting the solder bumps 16.

[0006] Here, other elements are mounted on the user circuit board 5 in addition to the flip-type CSP to form a user circuit. Further, the solder bumps 16 of the integrated circuit chip 1 and the solder balls 24 of the package substrate 22 are wirings of a wiring layer formed on the package substrate 22, and are basically electrically connected one to one. The package substrate 22 is generally made of glass epoxy resin or the like as a base material.

Next, as shown in FIG. 3, the non-flip type CSP integrated circuit chip 1 is mounted on a tape substrate 32 to become a CSP. The integrated circuit chip 1 is mounted with the surface on which the integrated circuit is formed facing upward. At this time, the bonding pads formed in the integrated circuit chip 1 are connected to the pads of the tape substrate 32 by the bonding wires 36. The pads are wirings of a wiring layer formed on the tape substrate 32 and are basically electrically connected to the solder balls 34 one-to-one.

[0008]

However, in the above-mentioned flip-type CSP and non-flip-type CSP, since the electric resistance of the semiconductor substrate 10 is high (not small), noise resistance and latch-up resistance are reduced. Problem. In particular, in the case of flip mounting, such a problem is likely to occur.

When the flip-type CSP is mounted on a board on which a user's circuit is formed and used, the integrated circuit of the integrated circuit chip is mounted on the side opposite to the user circuit board. This is a rare side. For this reason, the semiconductor substrate of the CSP is susceptible to external influences such as an electric field and a magnetic field, and the noise resistance and the latch-up resistance of the integrated circuit chip are reduced.

An object of the present invention is to solve the above-mentioned conventional problems, and an object of the present invention is to provide a semiconductor integrated circuit capable of improving noise resistance and latch-up resistance.

[0011]

According to the present invention, an integrated circuit chip in which an integrated circuit is formed by, for example, sequentially laminating wiring layers on a semiconductor substrate is mounted on a package substrate. In a semiconductor integrated circuit in which the package substrate is mounted and used on a substrate on which a user's circuit is to be formed, such that the surface on which the integrated circuit is formed is on the lower side, the integrated circuit of the integrated circuit chip This problem is solved by a semiconductor integrated circuit characterized in that a conductive metal plate is attached to a surface opposite to a surface on which the semiconductor substrate is formed, in a state where the semiconductor substrate is conductive. It was done.

In the semiconductor integrated circuit, the conductive metal plate has a thermal expansion coefficient equal to that of the semiconductor substrate and a thickness of 0.1 mm or more.
Noise immunity and latch-up immunity can be effectively improved.

Hereinafter, the operation of the present invention will be briefly described.

Investigation was made on the factors that reduce the noise resistance and the latch-up resistance of the flip-type CSP and the non-flip-type CSP. As a result, the electrical resistance of the semiconductor substrate 10 is high (not small). And the problem that the latch-up resistance is reduced.
When a current flows through the semiconductor substrate 10 having a high electric resistance due to an internal factor or an external factor, a potential difference occurs and a potential distribution occurs. Then, noise resistance and latch-up resistance are reduced.

In the semiconductor integrated circuit of the CSP according to the present invention, a conductive metal plate is attached to a surface of the integrated circuit chip opposite to the surface on which the integrated circuit is formed, in a state of being conductive with respect to the semiconductor substrate. Like that. Therefore, the substantial electrical resistance of the semiconductor substrate can be suppressed, and
Noise immunity and latch-up immunity can be improved.

In addition, when a factor that reduces noise resistance and latch-up resistance in the flip-type CSP was examined, an adverse effect on the semiconductor substrate of the CSP due to disturbance such as an electric field or a magnetic field was found. The flip type CSP is
In a state where the integrated circuit chip is used by being mounted on a substrate on which a user's circuit is formed, the surface opposite to the user circuit substrate is a surface on which the integrated circuit of the integrated circuit chip is not formed.
For this reason, it has been found that the semiconductor substrate of the CSP is easily affected by external influences such as an electric field and a magnetic field, and the noise resistance and the latch-up resistance of the integrated circuit chip are reduced.

In order to suppress the influence of the disturbance as described above, in the flip-type CSP semiconductor integrated circuit of the present invention, the flip-type CSP is mounted on a surface opposite to the surface on which the integrated circuit of the integrated circuit chip is formed. A conductive metal plate is stuck in a state where there is conductivity.

When the conductive metal plate is attached in this manner, it becomes difficult for a current to flow through the semiconductor substrate due to an internal factor or due to some disturbance, so that a potential difference is inadvertently generated and a potential distribution is less likely to occur. Further, the conductive metal plate has a shielding effect against external influences such as an electric field and a magnetic field, so that problems caused by the external influences can be reduced.

As described above, according to the present invention, noise resistance and latch-up resistance can be improved.

Further, in the CSP, the integrated circuit chip is finely processed, and there is a possibility that a flaw or the like may occur during transportation or storage, thereby causing a problem. Regarding this problem, one surface (the lower surface in the figure) of the integrated circuit chip 1 is protected by the package substrate 22, as shown in FIG. When the present invention is applied, the opposite surface (the upper surface in the drawing) of the integrated circuit chip 1 can be protected by a conductive metal plate indicated by reference numeral 3. By applying the present invention in this manner, the quality of CSP products can be easily maintained.

[0021]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 4 is a diagram showing C of the embodiment to which the present invention is applied.
It is sectional drawing of SP.

This figure is drawn corresponding to FIG. 2 described above. As is clear from comparison of these figures, the present embodiment of FIG. 4 is newly added to the conventional CSP of FIG.
A conductive metal plate 3 is provided. The conductive metal plate 3 is attached to the surface of the integrated circuit chip 1 opposite to the surface on which the integrated circuit is formed, in a state of being conductive with respect to the semiconductor substrate 10.

The conductive metal plate 3 is made of copper, aluminum, iron,
Other materials such as simple metals or alloys having no problem in conductivity are used as the material. For example, “42 Arrowy”, which is an alloy mainly containing iron and nickel, which is also used for a lead frame of a semiconductor integrated circuit may be used.

The shape of the conductive metal plate 3 is preferably 0.1 mm or more in order to secure conductivity. In consideration of such a thickness, the formation of the conductive metal plate 3 is more preferably performed by bonding than by vapor deposition. The bonding by this bonding is performed in a state where the semiconductor substrate 10 is conductive.

In addition, from the viewpoint of the quality and reliability of such an attached state, it is preferable that the difference in the coefficient of thermal expansion between the material of the semiconductor substrate 10 and the material of the conductive metal plate 3 is small. Preferably, the coefficient of thermal expansion of the material of the conductive metal plate 5 is equal to the coefficient of thermal expansion of the material of the semiconductor substrate 10. For example, if the material of the conductive metal plate 3 is “42 Arrowy”, the coefficient of thermal expansion between the conductive metal plate 3 and the semiconductor substrate 10 made of a silicon material is equivalent.

Here, consider a potential difference generated in the semiconductor substrate 10 of the integrated circuit chip 1 when a current flows between the solder bumps 16 of the reference numerals A and B in FIG. In this case, the cross section of the integrated circuit chip 1 between the solder bumps 16 of the reference numerals A and B is as shown in FIG.

First, conventionally, when there is no conductive metal plate 3, the current between the solder bumps 16 of the reference numerals A and B flows through the semiconductor substrate 10. The electric resistance to the current depends on the conductivity of the semiconductor substrate 10 and is large (not small).

On the other hand, in the case of the present embodiment, the conductive metal plate 3
In this case, the distance between the solder bump 16 of symbol A and the conductive metal plate 3 is the thickness of the semiconductor substrate 10 and is extremely short, and the electrical resistance between the solder bump 16 and the conductive metal plate 3 is small. Is small. Furthermore, the solder bump 1 of the code B
The same applies to the space between the conductive metal plate 6 and the conductive metal plate 3. Further, the current between the solder bumps 16 of the reference numerals A and B almost flows to the conductive metal plate 3 having a higher conductivity than the semiconductor substrate 10, and hardly flows to the semiconductor substrate 10.

As described above, the electric resistance to the current between the solder bumps 16 depends only on the conductivity of the conductive metal plate 3 and is relatively small. Further, the current flowing through the semiconductor substrate 10 is small. Therefore, the potential difference generated in the semiconductor substrate 10 is smaller than in the above-described conventional example in which the conductive metal plate 3 is not provided.

As described above, in the present embodiment, as described above, even when the current first flows due to an internal factor, the current hardly flows through the semiconductor substrate 10. Also, due to some disturbance, it becomes difficult for the current to flow through the semiconductor substrate 10,
A potential difference is inadvertently generated in the semiconductor substrate 10 and a potential distribution is less likely to occur. Further, the conductive metal plate has a shielding effect against external influences such as an electric field and a magnetic field, so that problems caused by the external influences can be reduced.

As described above, according to the present embodiment, the present invention can be effectively applied, and noise resistance and latch-up resistance can be improved.

[0033]

According to the present invention, noise resistance and latch-up resistance can be improved.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of a conventional flip-type CSP integrated circuit chip.

FIG. 2 is a cross-sectional view when the integrated circuit chip is configured as a CSP.

FIG. 3 is a sectional view of a conventional non-flip type CSP.

FIG. 4 is a flip type CS according to an embodiment to which the present invention is applied;
Sectional view of P

FIG. 5 is a plan view showing a situation in which a current flows through the integrated circuit chip 1 in a flip-type CSP.

FIG. 6 is a cross-sectional view of the flip-type CSP in the above situation.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Integrated circuit chip 3 ... Conductive metal plate 5 ... User circuit board 10 ... Semiconductor substrate 12 ... Insulating layer 14 ... Lead-out wiring layer 16 ... Solder bump 22 ... Package board 24 ... Solder ball 32 ... Tape board 34 ... Solder ball 36 ... Bonding Wire

Claims (2)

[Claims] When an integrated circuit chip on which an integrated circuit is formed by, for example, sequentially laminating wiring layers on a semiconductor substrate is mounted on a substrate on which a circuit of a user is formed, the integrated circuit chip is formed with the integrated circuit. A semiconductor integrated circuit mounted on a package substrate so that the surface of the integrated circuit chip is located on the lower side, with respect to the surface of the integrated circuit chip opposite to the surface on which the integrated circuit is formed. A semiconductor integrated circuit, wherein a conductive metal plate is adhered in a state of being conductive. 2. The semiconductor integrated circuit according to claim 1, wherein said conductive metal plate has a thermal expansion coefficient equal to that of said semiconductor substrate and a thickness of 0.1 mm or more.