JPH05326615A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH05326615A
JPH05326615A JP12585592A JP12585592A JPH05326615A JP H05326615 A JPH05326615 A JP H05326615A JP 12585592 A JP12585592 A JP 12585592A JP 12585592 A JP12585592 A JP 12585592A JP H05326615 A JPH05326615 A JP H05326615A
Authority
JP
Japan
Prior art keywords
bonding pad
silicon
copper
aluminium
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12585592A
Other languages
Japanese (ja)
Inventor
Takeshi Kato
剛 加藤
Hideo Miyagi
秀雄 宮城
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electronics Corp filed Critical Matsushita Electronics Corp
Priority to JP12585592A priority Critical patent/JPH05326615A/en
Publication of JPH05326615A publication Critical patent/JPH05326615A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/05599Material
    • H01L2224/056Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05617Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05624Aluminium [Al] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01005Boron [B]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01006Carbon [C]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01013Aluminum [Al]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01014Silicon [Si]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01029Copper [Cu]

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To provide a semiconductor device having improved bonding pads mainly composed of aluminium. CONSTITUTION:An insulation film 5 is formed on the surface of a silicon substrate 4 and a bonding pad 6, mainly composed of aluminium, is formed in a contact hole made through the insulation film 5, wherein the lower layer 6-a is composed of an aluminium layer heavily added with silicon, the intermediate layer 6-b is composed of an aluminium layer heavily added with copper, and the upper layer 6-c is composed of an aluminium layer substantially containing no copper. This structure suppresses alloy pit and electromigration effectively and provides a bonding pad having good adhesion to the silicon substrate 4 or a thin metal wire.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、半導体装置、特にその
ボンディングパッドの改良に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to an improvement in its bonding pad.

【0002】[0002]

【従来の技術】図2は従来の半導体装置のボンディング
パッドの周辺を示すものであり、シリコン基板1の表面
をシリコン酸化膜等の絶縁膜2で覆い、絶縁膜2に設け
たコンタクトホール内と絶縁膜2の表面の一部にボンデ
ィングパッド3を形成したものである。ボンディングパ
ッド3は、通常、シリコン(Si)を約1.0重量%、
銅(Cu)を約0.5重量%程度含むアルミニウムで構
成される。
2. Description of the Related Art FIG. 2 shows the periphery of a bonding pad of a conventional semiconductor device. The surface of a silicon substrate 1 is covered with an insulating film 2 such as a silicon oxide film, and the inside of a contact hole formed in the insulating film 2 is covered. The bonding pad 3 is formed on a part of the surface of the insulating film 2. The bonding pad 3 is usually about 1.0% by weight of silicon (Si),
It is composed of aluminum containing about 0.5% by weight of copper (Cu).

【0003】半導体装置の組立時には、ワイヤボンダー
のキャピラリーで運ばれてきた金線等の金属細線(図示
せず)がボンディングパッド3の上面に押しつけられ、
金属細線とボンディングパッド3が電気的、機械的に接
続される。
At the time of assembling the semiconductor device, a thin metal wire (not shown) such as a gold wire carried by the capillary of the wire bonder is pressed against the upper surface of the bonding pad 3,
The thin metal wire and the bonding pad 3 are electrically and mechanically connected.

【0004】[0004]

【発明が解決しようとする課題】ボンディングパッド3
中に添加されるシリコンはアロイピットを抑制する。ア
ロイピットは特にボンディングパッド3の下部に発生す
る。
Bonding pad 3
Silicon added inside suppresses alloy pits. Alloy pits are generated especially below the bonding pad 3.

【0005】銅はエレクトロマイグレーションを抑止す
る。しかし、銅は金線等の金属細線とボンディングパッ
ド3の接着性およびボンディングパッド3とシリコン基
板1の接着性を弱めるため、ボンディングパッド3の上
方および下方には含まれないことが望ましい。
Copper suppresses electromigration. However, since copper weakens the adhesiveness between the metal thin wire such as a gold wire and the bonding pad 3 and the adhesiveness between the bonding pad 3 and the silicon substrate 1, it is desirable that copper is not included above and below the bonding pad 3.

【0006】ところが、従来の半導体装置においては、
ボンディングパッド3中にシリコンおよび銅が一様に添
加されているため、アロイピットやエレクトロマイグレ
ーションを抑制することはできるが、アロイピットの発
生をより効果的に抑制するとか、あるいは金線等の金属
細線とボンディングパッド3の接着性およびボンディン
グパッド3とシリコン基板1の接着性を高めるという点
では必ずしも十分でない。
However, in the conventional semiconductor device,
Since silicon and copper are uniformly added to the bonding pad 3, alloy pits and electromigration can be suppressed, but the generation of alloy pits can be suppressed more effectively, or metal thin wires such as gold wires can be suppressed. It is not always sufficient in terms of improving the adhesiveness of the bonding pad 3 and the adhesiveness of the bonding pad 3 and the silicon substrate 1.

【0007】本発明はこのような従来の問題を解決する
半導体装置を提供するものである。
The present invention provides a semiconductor device that solves such conventional problems.

【0008】[0008]

【課題を解決するための手段】本発明は、シリコン基板
の表面を絶縁膜で覆い、この絶縁膜に設けたコンタクト
ホール内にアルミニウムを主成分とするボンディングパ
ッドを形成するとともに、このボンディングパッドの下
部をシリコンの添加量の多いアルミニウム層で、中部を
銅の添加量の多いアルミニウム層で、上部をシリコン、
銅を実質的に含まないアルミニウム層で形成したもので
ある。
According to the present invention, a surface of a silicon substrate is covered with an insulating film, and a bonding pad containing aluminum as a main component is formed in a contact hole formed in the insulating film. The lower part is an aluminum layer with a large amount of silicon added, the middle part is an aluminum layer with a large amount of copper added, and the upper part is silicon.
It is formed of an aluminum layer that does not substantially contain copper.

【0009】[0009]

【作用】このようにすれば、エレクトロマイグレーショ
ン、アロイピットを効果的に抑制できるとともに、金属
細線、シリコン基板とボンディングパッドの接着性も良
好に保つことができる。
By doing so, electromigration and alloy pits can be effectively suppressed, and the adhesiveness between the metal fine wire or the silicon substrate and the bonding pad can be kept good.

【0010】[0010]

【実施例】以下、本発明の一実施例について、図面を参
照しながら説明する。図1は本発明の一実施例における
半導体装置の断面図である。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a sectional view of a semiconductor device according to an embodiment of the present invention.

【0011】図1において、シリコン基板4の表面をシ
リコン酸化膜等の絶縁膜5で覆い、絶縁膜5に設けたコ
ンタクトホール内と絶縁膜5の表面の一部にボンディン
グパッド6を形成する。
In FIG. 1, a surface of a silicon substrate 4 is covered with an insulating film 5 such as a silicon oxide film, and a bonding pad 6 is formed in a contact hole provided in the insulating film 5 and a part of the surface of the insulating film 5.

【0012】ボンディングパッド6は、次のような方法
で形成する。ボンディングパッドを形成するためのスパ
ッタリングのターゲットを任意に選択できるようにして
おき、まず、アルミニウムとシリコンのターゲットを用
いてボンディングパッド下部6−aを形成する。ボンデ
ィングパッド下部6−aはシリコン添加量の多いアルミ
ニウム層となるため、特にボンディングパッド6の下方
に発生しやすいアロイピットを効果的に抑制する。
The bonding pad 6 is formed by the following method. The sputtering target for forming the bonding pad can be arbitrarily selected, and first, the bonding pad lower portion 6-a is formed using the targets of aluminum and silicon. Since the lower portion 6-a of the bonding pad is an aluminum layer with a large amount of silicon added, it effectively suppresses alloy pits that are likely to occur particularly below the bonding pad 6.

【0013】次に、アルミニウムと銅のターゲットを用
い、ボンディングパッド中部6−bを形成する。ボンデ
ィングパッド中部6−bは銅の添加量は多いが、シリコ
ンはほとんど添加されない。そして、ボンディングパッ
ド中部6−bに添加された銅によってエレクトロマイグ
レーションが抑制される。
Next, using a target of aluminum and copper, the middle portion 6-b of the bonding pad is formed. The middle portion 6-b of the bonding pad contains a large amount of copper, but almost no silicon. Then, electromigration is suppressed by the copper added to the middle portion 6-b of the bonding pad.

【0014】最後に、アルミニウムのターゲットを用
い、ボンディングパッド上部6−cを形成する。ボンデ
ィングパッド上部6−cは銅、シリコンともにほとんど
添加されない。したがって、金線等の金属細線をボンデ
ィングパッド6の上面に押しつけ、金属細線とボンディ
ングパッドを電気的、機械的に接続する際にも、良好な
接着性を確保することができる。
Finally, using the aluminum target, the upper portion 6-c of the bonding pad is formed. Neither copper nor silicon is added to the upper portion 6-c of the bonding pad. Therefore, good adhesiveness can be ensured even when a metal thin wire such as a gold wire is pressed against the upper surface of the bonding pad 6 to electrically and mechanically connect the metal thin wire and the bonding pad.

【0015】[0015]

【発明の効果】本発明は、ボンディングパッドを形成す
る際、濃度勾配を設けてシリコン、銅をアルミニウムに
添加しているため、エレクトロマイグレーション、アロ
イピットを効果的に抑制できるとともに、金属細線、シ
リコン基板とボンディングパッドの接着性も良好に保つ
ことができる。
According to the present invention, since a concentration gradient is provided and silicon and copper are added to aluminum when a bonding pad is formed, electromigration and alloy pits can be effectively suppressed, and a fine metal wire and a silicon substrate can be obtained. The adhesiveness of the bonding pad can also be kept good.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施例における半導体装置の断面図FIG. 1 is a sectional view of a semiconductor device according to an embodiment of the present invention.

【図2】従来の半導体装置の断面図FIG. 2 is a sectional view of a conventional semiconductor device.

【符号の説明】 1 シリコン基板 2 絶縁膜 3 ボンディングパッド 4 シリコン基板 5 絶縁膜 6 ボンディングパッド 6−a ボンディングパッド下部 6−b ボンディングパッド中部 6−c ボンディングパッド上部[Explanation of Codes] 1 Silicon substrate 2 Insulating film 3 Bonding pad 4 Silicon substrate 5 Insulating film 6 Bonding pad 6-a Lower bonding pad 6-b Middle bonding pad 6-c Upper bonding pad

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】シリコン基板の表面を絶縁膜で覆い、上記
絶縁膜に設けたコンタクトホール内にアルミニウムを主
成分とするボンディングパッドを形成するとともに、上
記ボンディングパッドの下部をシリコンの添加量の多い
アルミニウム層で、中部を銅の添加量の多いアルミニウ
ム層で、上部をシリコン、銅を実質的に含まないアルミ
ニウム層で形成したことを特徴とする半導体装置。
1. A surface of a silicon substrate is covered with an insulating film, a bonding pad containing aluminum as a main component is formed in a contact hole provided in the insulating film, and a lower portion of the bonding pad is heavily doped with silicon. A semiconductor device comprising an aluminum layer, an aluminum layer having a large amount of copper added in the middle, and an aluminum layer containing substantially no silicon or copper in the upper portion.
JP12585592A 1992-05-19 1992-05-19 Semiconductor device Pending JPH05326615A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12585592A JPH05326615A (en) 1992-05-19 1992-05-19 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12585592A JPH05326615A (en) 1992-05-19 1992-05-19 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH05326615A true JPH05326615A (en) 1993-12-10

Family

ID=14920613

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12585592A Pending JPH05326615A (en) 1992-05-19 1992-05-19 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH05326615A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108400227A (en) * 2018-05-04 2018-08-14 佛山市国星半导体技术有限公司 A kind of flip LED chips and preparation method thereof
JP2021150374A (en) * 2020-03-17 2021-09-27 株式会社東芝 Semiconductor device and inspection device

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108400227A (en) * 2018-05-04 2018-08-14 佛山市国星半导体技术有限公司 A kind of flip LED chips and preparation method thereof
CN108400227B (en) * 2018-05-04 2023-08-15 佛山市国星半导体技术有限公司 Flip LED chip and manufacturing method thereof
JP2021150374A (en) * 2020-03-17 2021-09-27 株式会社東芝 Semiconductor device and inspection device
US12040303B2 (en) 2020-03-17 2024-07-16 Kabushiki Kaisha Toshiba Semiconductor device and inspection device

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