JPH11176881A - Electronic circuit and manufacture thereof - Google Patents
Electronic circuit and manufacture thereofInfo
- Publication number
- JPH11176881A JPH11176881A JP34482197A JP34482197A JPH11176881A JP H11176881 A JPH11176881 A JP H11176881A JP 34482197 A JP34482197 A JP 34482197A JP 34482197 A JP34482197 A JP 34482197A JP H11176881 A JPH11176881 A JP H11176881A
- Authority
- JP
- Japan
- Prior art keywords
- solder
- weight
- circuit board
- gold bump
- semiconductor chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Wire Bonding (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、電子回路とその製
造方法に関する。より詳しく言えば、本発明は、電子部
品類、特に大規模集積回路（ＬＳＩ）チップをチップ上
の金バンプに被着したはんだを介して基板に接合するフ
リップチップ接合により表面実装して製造された電子回
路とその製造方法に関する。[0001] The present invention relates to an electronic circuit and a method for manufacturing the same. More specifically, the present invention is manufactured by surface mounting electronic components, especially large-scale integrated circuit (LSI) chips, by flip-chip bonding, in which the chips are bonded to a substrate via solder applied to gold bumps on the chip. Electronic circuit and a method of manufacturing the same.
【０００２】[0002]
【従来の技術】フリップチップ接合は、実装面積が小さ
く、また、回路の配線長が短いことから、高密度実装や
高速デバイスの実装に適している。このため、フリップ
チップ接合は大型コンピュータの分野で採用されてきた
が、最近では小型化、高機能化が進む民生用電子機器に
も用いられるようになってきた。2. Description of the Related Art Flip-chip bonding is suitable for high-density mounting and high-speed device mounting because of its small mounting area and short circuit wiring length. For this reason, flip chip bonding has been adopted in the field of large computers, but recently it has also been used in consumer electronic devices that are becoming smaller and more sophisticated.
【０００３】フリップチップ接合のバンプについては、
アルミニウム電極上へのバンプ形成が容易であることか
ら金バンプを用いた開発例が増加している。金バンプと
基板電極の接続には、はんだ付け、異方導電性フィル
ム、導電ペーストなどのように中間材を介す方式と、バ
ンプと基板電極を熱圧着して金属間の固相拡散により接
合する方式がある。[0003] Regarding flip-chip bonding bumps,
Because of easy formation of bumps on aluminum electrodes, development examples using gold bumps are increasing. The connection between the gold bump and the substrate electrode is via an intermediate material such as soldering, anisotropic conductive film, conductive paste, etc. There is a method to do.
【０００４】金属間の固相拡散により接合する方式は、
良好な状態の接合形成が難しく、濡れ不良等により信頼
性の低下を招く。その一方、中間材を介す方式のうち、
異方導電性フィルムや導電ペーストにより金バンプと基
板電極を接続する方式では、位置ずれ、高抵抗、リペア
（補修）不可といった問題点がある。これに対して、は
んだ付けにより金バンプと基板電極を接続する場合、セ
ルフアライメント効果による位置ずれ補正、低抵抗化、
リペア性の付与といった長所が考えられる。[0004] The joining method by solid-phase diffusion between metals is as follows.
It is difficult to form a bond in a good state, and the reliability is lowered due to poor wetting or the like. On the other hand, among the methods through intermediate materials,
The method of connecting the gold bump and the substrate electrode with an anisotropic conductive film or conductive paste has problems such as misalignment, high resistance, and no repair (repair). On the other hand, when connecting the gold bumps and the board electrodes by soldering, the misalignment correction by the self-alignment effect, low resistance,
Advantages such as providing repairability are conceivable.
【０００５】従来、チップ側バンプと基板電極との接合
部のはんだは、溶融はんだ射出、はんだペースト印刷、
あるいはスーパーソルダ法により、基板電極側に供給す
る方法が一般に用いられている。しかし、基板にはんだ
を供給するこれらの方法では、狭ピッチ化への対応にお
いて、例えば溶融はんだ射出の場合はブリッジの発生、
はんだペーストの場合は印刷性やはんだ粉末の微小化の
限界という問題がある。更に、これらの方法では、工数
が増加したり、基板メーカへ処理を依頼しなければなら
ず、コストの上昇を引き起こす。Conventionally, the solder at the joint between the chip-side bump and the board electrode is formed by injection of molten solder, solder paste printing,
Alternatively, a method of supplying the substrate electrode side by a super solder method is generally used. However, in these methods of supplying solder to the board, in response to narrow pitch, for example, in the case of molten solder injection, the occurrence of bridges,
In the case of the solder paste, there are problems such as printability and limitation of miniaturization of the solder powder. Furthermore, in these methods, the number of man-hours is increased and processing must be requested to a substrate maker, which causes an increase in cost.
【０００６】このような不都合を解消し、チップの金バ
ンプと基板電極の接合にはんだ付けを用い且つ狭ピッチ
化に対応可能なフリップチップ接合を目指す技術とし
て、溶融はんだ槽に金バンプを浸漬することにより金バ
ンプ側にはんだを供給する方法が着目されている。しか
しながら、この方法においては、はんだ中に含まれるス
ズが金と反応してＡｕＳｎ、ＡｕＳｎ2 、ＡｕＳｎ4 と
いった金属間化合物を形成しやすく、そしてこのような
金属間化合物は固くて脆い性質を有し、接合部に発生す
るとしばしば信頼性低下の原因となることが問題となっ
ている。As a technique for solving such inconvenience and using a solder for joining the gold bumps of the chip and the substrate electrodes and aiming at flip-chip joining which can cope with a narrow pitch, the gold bumps are immersed in a molten solder bath. Accordingly, attention has been paid to a method of supplying solder to the gold bump side. However, in this method, tin contained in the solder easily reacts with gold to form an intermetallic compound such as AuSn, AuSn 2 or AuSn 4 , and such an intermetallic compound has a hard and brittle property. The problem is that if it occurs at the joint, it often causes a decrease in reliability.
【０００７】チップ上に形成した金バンプを溶融はんだ
中に浸漬して金バンプにはんだを供給し、基板上の導体
配線パターンに接合する技術を開示している特開平３−
１０８７３４号公報では、はんだをインジウムを含む合
金と限定している。はんだにインジウムを含ませること
で、金とスズとの反応を抑制することが可能になる。と
ころが、はんだがインジウムを含む場合には、次に述べ
るような問題が生じる。第一に、インジウムの易酸化性
からはんだ浴表面を清浄な状態に保つことが難しく、特
に大気中では溶融浴のはんだをバンプへ移す（供給す
る）ことが良好に行なえない。第二に、雰囲気の調整等
で第一の問題を解消しても、はんだの供給を良好に行な
うためには、はんだ浴の設定温度を融点から５０℃以上
高くしなければならず、他のはんだと比べてより大きな
熱応力が金バンプに加わる。第三に、インジウムは高価
な材料であることから、コストが高くなる。以上のよう
に、インジウムを含むはんだを用いた場合には、金バン
プへのはんだの供給がしずらくなり、且つコストの上昇
を招く。Japanese Patent Laid-Open Publication No. Hei 3 (1991) discloses a technique in which a gold bump formed on a chip is immersed in molten solder to supply the solder to the gold bump and join it to a conductor wiring pattern on a substrate.
In Japanese Patent No. 108734, the solder is limited to an alloy containing indium. By including indium in the solder, it becomes possible to suppress the reaction between gold and tin. However, when the solder contains indium, the following problems occur. First, it is difficult to keep the solder bath surface in a clean state due to the oxidizability of indium, and it is not possible to transfer (supply) the solder in the molten bath to the bumps particularly in the air. Second, even if the first problem is solved by adjusting the atmosphere or the like, in order to supply the solder satisfactorily, the set temperature of the solder bath must be raised by 50 ° C. or more from the melting point. Greater thermal stress is applied to the gold bumps than solder. Third, indium is an expensive material, which increases costs. As described above, when the solder containing indium is used, it becomes difficult to supply the solder to the gold bumps, and the cost is increased.
【０００８】[0008]
【発明が解決しようとする課題】本発明は、従来技術に
存する上記の欠点を解消して、インジウムを含むはんだ
を使用した場合に比べて金バンプへのはんだの供給が容
易であって、しかも金とはんだ中のスズとの反応を抑制
できる新しいはんだ供給方法を利用して、ＬＳＩチップ
に代表される半導体チップを回路基板へ表面実装して電
子回路を製造する方法と、その方法により製作したチッ
プ−基板間の接合の信頼性の高い電子回路を提供するこ
とを目的とする。SUMMARY OF THE INVENTION The present invention solves the above-mentioned disadvantages of the prior art, and makes it easier to supply solder to gold bumps than when using solder containing indium. Utilizing a new solder supply method that can suppress the reaction between gold and tin in the solder, a method of manufacturing an electronic circuit by surface mounting a semiconductor chip typified by an LSI chip on a circuit board, and manufacturing the electronic circuit by the method An object of the present invention is to provide an electronic circuit having high reliability of bonding between a chip and a substrate.
【０００９】[0009]
【課題を解決するための手段】本発明の電子回路製造方
法は、半導体チップを回路基板にはんだを介して接合す
ることにより電子回路を製造する方法であって、半導体
チップの電極上に形成された金バンプを液相線温度が１
２５℃以上且つ１８０℃未満のはんだの溶融浴に浸漬し
て金バンプ上にはんだを供給及び被着し、次いで半導体
チップを回路基板上の所定の位置に配置し、そして金バ
ンプ上のはんだを溶融後再固化させて半導体チップを回
路基板に接合する方法である。SUMMARY OF THE INVENTION An electronic circuit manufacturing method according to the present invention is a method for manufacturing an electronic circuit by bonding a semiconductor chip to a circuit board via solder, and is formed on an electrode of the semiconductor chip. Liquid bump temperature is 1
The solder is supplied and deposited on the gold bumps by dipping in a molten bath of solder at a temperature of 25 ° C. or more and less than 180 ° C. Then, the semiconductor chip is placed at a predetermined position on the circuit board, and the solder on the gold bumps is removed. This is a method in which a semiconductor chip is bonded to a circuit board by melting and then re-solidifying.
【００１０】また、本発明の電子回路は、半導体チップ
がその電極上に形成された金バンプをはんだを介して回
路基板の電極に接合して当該回路基板に搭載されている
電子回路であって、当該はんだが液相線温度が１２５℃
以上且つ１８０℃未満のはんだであることを特徴とす
る。The electronic circuit of the present invention is an electronic circuit in which a semiconductor chip is mounted on a circuit board by bonding a gold bump formed on the electrode to an electrode of the circuit board via solder. The solder has a liquidus temperature of 125 ° C.
It is characterized in that the solder is above 180 ° C.
【００１１】[0011]
【発明の実施の形態】本発明では、金バンプを備えた、
ＬＳＩチップに代表される半導体チップを回路基板にフ
リップチップ接合する際に使用されるはんだとして、液
相線温度が１２５℃以上且つ１８０℃未満のはんだ合金
を使用する。上述のように、金バンプをはんだを介して
回路基板の電極に接合すると、金とはんだ中のスズとの
金属間化合物が生成して接合部の信頼性の低下の原因と
なる。本発明は、この金属間化合物の生成を抑制するに
は、比較的低融点のはんだを採用し、金とはんだの反応
温度を下げることを可能とすることが有効であることを
見いだしてなされたものである。DETAILED DESCRIPTION OF THE INVENTION In the present invention, a gold bump is provided.
A solder alloy having a liquidus temperature of 125 ° C. or more and less than 180 ° C. is used as solder used when a semiconductor chip typified by an LSI chip is flip-chip bonded to a circuit board. As described above, when a gold bump is joined to an electrode of a circuit board via solder, an intermetallic compound of gold and tin in the solder is generated, which causes a reduction in the reliability of the joint. The present invention has been found to be effective in suppressing the formation of this intermetallic compound by employing a solder having a relatively low melting point and enabling a reduction in the reaction temperature between gold and solder. Things.
【００１２】はんだを金バンプへ供給して被着するとき
及び被着したはんだを介しチップを回路基板へ実装する
ときの温度が高いと、はんだ中への金の拡散が著しく進
行するため、Ａｕ−Ｓｎ化合物が多量に生成し、基板実
装後の接合部は非常に脆い状態となる。そのような接合
部が電子回路の反復使用に伴う発熱と冷却のサイクルに
さらされると、異種材料間の熱膨張率差による応力が加
わるため、接合部にクラックが発生し、オープン不良
（絶縁不良）が発生する。先に説明した特開平３−１０
８７３４号公報では、インジウムを含むはんだを用いる
ことでこのような不都合の解消を図っている。If the temperature is high when the solder is supplied to and attached to the gold bumps and when the chip is mounted on the circuit board via the applied solder, the diffusion of gold into the solder remarkably progresses. A large amount of -Sn compound is generated, and the joint after mounting on the substrate is in a very brittle state. When such joints are subjected to heat and cooling cycles associated with the repeated use of electronic circuits, stress is applied due to the difference in the coefficient of thermal expansion between dissimilar materials, causing cracks in the joints and open failure (insulation failure). ) Occurs. Japanese Patent Laid-Open No. 3-10 described above
In JP 8734, such inconvenience is solved by using a solder containing indium.
【００１３】これに対し、本発明によれば、はんだの融
点を低くすることで、バンプへのはんだ供給時及びチッ
プの基板実装時の温度を低下させることにより、Ａｕ−
Ｓｎ化合物の生成を抑制することで、チップと基板との
接合部の信頼性を高めることがとが可能となる。On the other hand, according to the present invention, by lowering the melting point of the solder, the temperature at the time of supplying the solder to the bumps and at the time of mounting the chip on the substrate is reduced.
By suppressing the generation of the Sn compound, it is possible to increase the reliability of the joint between the chip and the substrate.
【００１４】本発明で使用するはんだは、液相線温度が
１２５℃以上且つ１８０℃未満の合金である。１２５℃
という下限は、これより低い液相線温度の合金の実用の
可能性がないことによる。１８０℃という上限は、液相
線温度がこれ以上になるとＡｕ−Ｓｎ化合物の生成量が
多くなることによるものである。The solder used in the present invention is an alloy having a liquidus temperature of 125 ° C. or more and less than 180 ° C. 125 ° C
The lower limit is due to the lack of practicality of lower liquidus temperature alloys. The upper limit of 180 ° C. is attributable to the fact that when the liquidus temperature becomes higher than this, the amount of the generated Au—Sn compound increases.
【００１５】本発明におけるはんだとして好適なもの
は、ＳｎとＢｉを主成分とする合金である。このＳｎ−
Ｂｉはんだにおける好ましいＳｎ含有量は４０〜５９重
量％であり、残部（すなわち４１〜６０重量％）がＢｉ
である。このＳｎ−Ｂｉはんだは、上記の組成範囲内に
おいて、更にＡｇを最高で２重量％まで含んでもよい。
すなわちＡｇを含む場合のはんだ組成は、Ｓｎが４０〜
５９重量％、Ｂｉが４１〜６０重量％、そしてＡｇが２
重量％以下となる。Ａｇには、ＳｎとＢｉだけからなる
はんだの熱疲労特性を改善する優れた作用があり、すな
わちＡｇを含むＳｎ−Ｂｉはんだは延性が増して接合部
の信頼性を更に高めることができる。２重量％より多量
の銀を使用しても差し支えはないが、はんだの延性を高
める銀の効果はその含有量を２重量％をより多くすると
延性を逆に低下させるので、実用的には２重量％以下の
銀含有量とすることが好ましい。本発明において特に好
ましいはんだは、Ｓｎを４２重量％、Ｂｉを５７重量
％、そしてＡｇを１重量％含有するものである。Preferred as the solder in the present invention is an alloy containing Sn and Bi as main components. This Sn-
The preferred Sn content in the Bi solder is 40 to 59% by weight, and the balance (i.e., 41 to 60% by weight) is Bi.
It is. The Sn-Bi solder may further contain up to 2% by weight of Ag within the above composition range.
That is, when the solder composition contains Ag, the Sn
59% by weight, 41 to 60% by weight of Bi, and 2% of Ag
% By weight or less. Ag has an excellent effect of improving the thermal fatigue characteristics of a solder consisting of Sn and Bi alone, that is, Sn-Bi solder containing Ag has an increased ductility and can further enhance the reliability of the joint. It is safe to use silver in an amount larger than 2% by weight. However, the effect of silver which enhances the ductility of the solder decreases the ductility when the content is more than 2% by weight. Preferably, the silver content is less than or equal to% by weight. Particularly preferred solders in the present invention are those containing 42% by weight of Sn, 57% by weight of Bi, and 1% by weight of Ag.
【００１６】Ｓｎ−Ｂｉはんだ、あるいはＳｎ−Ｂｉ−
Ａｇはんだのほかに、本発明では例えばＳｎ−Ｂｉ−Ｐ
ｂ系のはんだ等を使用することも可能である。[0016] Sn-Bi solder or Sn-Bi-
In addition to Ag solder, in the present invention, for example, Sn-Bi-P
It is also possible to use b-type solder or the like.
【００１７】本発明において半導体チップの金バンプを
はんだ溶融浴に浸漬して金バンプへはんだを供給する具
体的方法、及び金バンブに被着したはんだを介して半導
体チップを回路基板の電極に接合する具体的方法は、半
導体産業の分野において周知であり、ここで詳しく説明
するには及ばない。In the present invention, a specific method of immersing a gold bump of a semiconductor chip in a solder melting bath and supplying solder to the gold bump, and bonding the semiconductor chip to an electrode of a circuit board via the solder attached to the gold bump Specific methods of doing so are well known in the semiconductor industry and need not be described at length here.
【００１８】[0018]
【実施例】次に、実施例により本発明を更に説明する。
表１に示したように液相線温度の異なる各種はんだ合金
を、同表に浸漬温度として示した液相線温度以上の温度
に加熱して溶融状態とし、これにＬＳＩチップのアルミ
ニウム電極上に形成した金バンプを浸漬させた。浸漬後
の金バンプ断面の走査型電子顕微鏡（ＳＥＭ）観察によ
り、金バンプ上へのはんだ供給・被着状態を調査した。
その結果から金バンプへうまくはんだを供給してバンプ
上にはんだ皮膜を形成できた試料（表１の「はんだ被着
状態」が○と表示されているもの）について、被着した
はんだを加熱溶融することにより金バンプを回路基板の
銅電極上に接合し、ＬＳＩチップを基板へ実装した。
（表１の「はんだ被着状態」が×と表示されているもの
は、バンプ上のはんだ皮膜が十分でなかったことを示し
ている。）実装後の接合部断面を電子プローブ微量分析
計（ＥＰＭＡ）で分析して、金バンプの基板への接合状
態を調査した。Next, the present invention will be further described with reference to examples.
Various solder alloys having different liquidus temperatures as shown in Table 1 were heated to a temperature equal to or higher than the liquidus temperature indicated as the immersion temperature in the same table to be in a molten state. The formed gold bump was immersed. The state of solder supply and deposition on the gold bump was examined by scanning electron microscope (SEM) observation of the cross section of the gold bump after immersion.
From the results, for the sample that successfully supplied the solder to the gold bump and formed a solder film on the bump (the “Solder applied state” in Table 1 is indicated by “○”), the applied solder was melted by heating. By doing so, the gold bumps were joined on the copper electrodes of the circuit board, and the LSI chip was mounted on the board.
(The "X" in Table 1 indicates that the solder film on the bump was not sufficient.) The cross section of the joint after mounting was measured by an electron probe microanalyzer ( The state of bonding of the gold bumps to the substrate was examined by analysis using EPMA.
【００１９】得られた結果を表１に示す。基板への接合
状態が○で表示されているものは、はんだを介して金バ
ンブと銅電極との良好な接合が形成されたことを示して
おり、×で表示されているものは、接合部にクラックが
発生し、良好な接合が形成できなかったことを示してい
る。ＡｕＳｎ発生量が「少」と表示されているものは、
はんだ中のスズのうちのわずかなものだけがＡｎ−Ｓｎ
金属間化合物を形成していたことを示しており、「多」
と表示されているものは、はんだ中のスズの大半がＡｎ
−Ｓｎ金属間化合物を形成していたことを示していて、
矢印の左側がはんだをバンプへ被着時の状態であり、右
側が接合後の状態である。The results obtained are shown in Table 1. If the bonding state to the substrate is indicated by a circle, it indicates that a good connection between the gold bump and the copper electrode was formed via the solder. This indicates that cracks occurred and good bonding could not be formed. If the amount of generated AuSn is displayed as "low",
Only a small amount of tin in the solder is An-Sn
This indicates that an intermetallic compound was formed,
Indicates that most of the tin in the solder is An
-Sn intermetallic compound was formed,
The left side of the arrow is the state when the solder is applied to the bump, and the right side is the state after the bonding.
【００２０】[0020]
【表１】 [Table 1]
【００２１】液相線温度が１８０℃未満のはんだ３種に
ついて、はんだを金バンプへ供給及び被着する際の温度
（はんだ浴温度）を２００℃以下とした場合に、はんだ
の良好な供給・被着、チップの基板への良好な実装が行
なえた。一方、融点が１８０℃以上のはんだでは、Ａｕ
−Ｓｎ金属間化合物が多量に生成するため、基板への実
装がうまく行なえず、また、たとえ行なえても実装直後
に接合部は破断した。For three types of solder having a liquidus temperature of less than 180 ° C., when the temperature (solder bath temperature) at the time of supplying and applying the solder to the gold bumps (soldering bath temperature) is set to 200 ° C. or less, a good supply of solder is obtained. Good adherence and good mounting of the chip on the substrate. On the other hand, for a solder having a melting point of 180 ° C. or more, Au
Since a large amount of -Sn intermetallic compound was generated, mounting on the substrate could not be carried out well, and even if it could be carried out, the joint was broken immediately after mounting.
【００２２】[0022]
【発明の効果】以上説明したように、本発明によれば、
金バンプへのはんだの供給を低い温度で容易に行うこと
ができ、且つ、金とはんだ中のスズとの反応を効果的に
抑制できることから半導体チップの金バンプと回路基板
の電極との接合強度を向上させることができ、それゆえ
信頼性の高い電子回路を提供することが可能になる。As described above, according to the present invention,
The bonding strength between the gold bump of the semiconductor chip and the electrode of the circuit board can be easily controlled at a low temperature and the reaction between the gold and the tin in the solder can be effectively suppressed. Therefore, it is possible to provide a highly reliable electronic circuit.
───────────────────────────────────────────────────── フロントページの続き (72)発明者 北嶋 雅之 神奈川県川崎市中原区上小田中４丁目１番 １号 富士通株式会社内 (72)発明者 竹居 成和 神奈川県川崎市中原区上小田中４丁目１番 １号 富士通株式会社内 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Masayuki Kitajima 4-1-1, Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Prefecture Inside Fujitsu Limited (72) Inventor Nariwazu Takei 4-chome, Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa No. 1 in Fujitsu Limited
Claims (10)
て接合することにより電子回路を製造する方法であっ
て、半導体チップの電極上に形成された金バンプを液相
線温度が１２５℃以上且つ１８０℃未満のはんだの溶融
浴に浸漬して金バンプ上にはんだを供給及び被着し、次
いで半導体チップを回路基板上の所定の位置に配置し、
そして金バンプ上のはんだを溶融後再固化させて半導体
チップを回路基板に接合する電子回路の製造方法。1. A method of manufacturing an electronic circuit by bonding a semiconductor chip to a circuit board via solder, wherein a gold bump formed on an electrode of the semiconductor chip has a liquidus temperature of 125 ° C. or higher and Immersing in a molten bath of solder below 180 ° C. to supply and apply the solder on the gold bumps, and then place the semiconductor chip in a predetermined position on the circuit board;
Then, a method of manufacturing an electronic circuit in which a solder on a gold bump is melted and solidified again to join a semiconductor chip to a circuit board.
分とするはんだを使用する、請求項１記載の方法。2. The method according to claim 1, wherein a solder containing tin and bismuth as a main component is used as the solder.
びビスマスを４１〜６０重量％含む、請求項２記載の方
法。3. The method of claim 2 wherein said solder comprises 40-59% by weight tin and 41-60% by weight bismuth.
ビスマスを４１〜６０重量％含み、且つ２重量％以下の
銀を含む、請求項２記載の方法。4. The solder comprises 40 to 59% by weight of tin,
3. The method according to claim 2, comprising from 41 to 60% by weight of bismuth and up to 2% by weight of silver.
スを５７重量％、そして銀を１重量％含有している、請
求項４記載の方法。5. The method of claim 4 wherein said solder contains 42% by weight tin, 57% by weight bismuth, and 1% by weight silver.
金バンプをはんだを介して回路基板の電極に接合して当
該回路基板に搭載されている電子回路であって、当該は
んだが液相線温度が１２５℃以上且つ１８０℃未満のは
んだであることを特徴とする電子回路。6. An electronic circuit mounted on a circuit board by bonding a gold bump formed on an electrode of the semiconductor chip to an electrode of the circuit board via solder, wherein the solder is a liquid phase wire. An electronic circuit, wherein the temperature of the solder is 125 ° C. or more and less than 180 ° C.
するはんだである、請求項６記載の電子回路。7. The electronic circuit according to claim 6, wherein said solder is a solder containing tin and bismuth as main components.
びビスマスを４１〜６０重量％含むはんだである、請求
項７記載の電子回路。8. The electronic circuit according to claim 7, wherein said solder is a solder containing 40 to 59% by weight of tin and 41 to 60% by weight of bismuth.
ビスマスを４１〜６０重量％含み、且つ２重量％以下の
銀を含むはんだである、請求項８記載の電子回路。9. The solder comprises 40 to 59% by weight of tin,
The electronic circuit according to claim 8, wherein the solder is a solder containing 41 to 60% by weight of bismuth and not more than 2% by weight of silver.
マスを５７重量％、そして銀を１重量％含有するはんだ
である、請求項９記載の電子回路。10. The electronic circuit according to claim 9, wherein said solder is a solder containing 42% by weight of tin, 57% by weight of bismuth and 1% by weight of silver.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP34482197A JP3592054B2 (en) | 1997-12-15 | 1997-12-15 | Electronic circuit and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP34482197A JP3592054B2 (en) | 1997-12-15 | 1997-12-15 | Electronic circuit and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH11176881A true JPH11176881A (en) | 1999-07-02 |
| JP3592054B2 JP3592054B2 (en) | 2004-11-24 |
Family
ID=18372238
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP34482197A Expired - Fee Related JP3592054B2 (en) | 1997-12-15 | 1997-12-15 | Electronic circuit and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3592054B2 (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000141079A (en) * | 1998-09-04 | 2000-05-23 | Toyota Central Res & Dev Lab Inc | Leadless solder alloy |
| JP2011077308A (en) * | 2009-09-30 | 2011-04-14 | Fujitsu Ltd | Method for mounting semiconductor device |
| JP2017051984A (en) * | 2015-09-10 | 2017-03-16 | 株式会社弘輝 | Solder alloy and solder composition |
-
1997
- 1997-12-15 JP JP34482197A patent/JP3592054B2/en not_active Expired - Fee Related
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000141079A (en) * | 1998-09-04 | 2000-05-23 | Toyota Central Res & Dev Lab Inc | Leadless solder alloy |
| JP2011077308A (en) * | 2009-09-30 | 2011-04-14 | Fujitsu Ltd | Method for mounting semiconductor device |
| JP2017051984A (en) * | 2015-09-10 | 2017-03-16 | 株式会社弘輝 | Solder alloy and solder composition |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3592054B2 (en) | 2004-11-24 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6307160B1 (en) | High-strength solder interconnect for copper/electroless nickel/immersion gold metallization solder pad and method | |
| KR0124517B1 (en) | Lead-free, tin, antimony, bismtuh, copper solder alloy | |
| EP0629463B1 (en) | Lead-free, high-temperature, tin based multi-component solder | |
| US7709746B2 (en) | Pb-free solder-connected structure and electronic device | |
| US7344061B2 (en) | Multi-functional solder and articles made therewith, such as microelectronic components | |
| JP3232963B2 (en) | Lead-free solder for connecting organic substrates and mounted products using the same | |
| JP2516326B2 (en) | Ternary solder alloy, method of electrically connecting integrated circuit chip to substrate having circuit pattern formed thereon, and integrated circuit chip module | |
| US20050133572A1 (en) | Methods of forming solder areas on electronic components and electronic components having solder areas | |
| JPH0788680A (en) | Composition of high-temperature lead-free tin based solder | |
| JP2001196409A (en) | Semiconductor device | |
| JPH071179A (en) | Lead-free tin - bismuth solder | |
| JP3441220B2 (en) | Improved solder paste mixture | |
| JP5041102B2 (en) | Lead-free solder alloy, joining member and manufacturing method thereof, and electronic component | |
| JP2000307228A (en) | Solder jointing method containing no lead and electronic module manufactured thereby | |
| KR20010012083A (en) | Lead Free Solder | |
| JPH08164496A (en) | Sn-zn solder, sn-zn-bi solder, method for surface treatment of same, and mounted substrate using it | |
| JP2001168519A (en) | Mixed mounting structure, mixed mounting method, and electronic equipment | |
| JP3592054B2 (en) | Electronic circuit and manufacturing method thereof | |
| JP3460438B2 (en) | Lead-free solder and mounted products using it | |
| JPH0985484A (en) | Lead-free solder and packaging method using the same and packaged articles | |
| JP2001284785A (en) | Electric or electronic component and assembly | |
| JP3785822B2 (en) | ELECTRODE STRUCTURE, SILICON SEMICONDUCTOR ELEMENT HAVING THE ELECTRODE, MANUFACTURING METHOD THEREOF, CIRCUIT BOARD MOUNTING THE ELEMENT AND MANUFACTURING METHOD THEREOF | |
| JP3460442B2 (en) | Lead-free solder and mounted products using it | |
| JPH1080788A (en) | Fatigue resistant reinforced solder | |
| KR20060061327A (en) | Solder bump forming method and device using thin film heater formed on semiconductor chip or semiconductor chip wafer |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20040721 |
|
| TRDD | Decision of grant or rejection written | ||
| A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20040727 |
|
| A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20040824 |
|
| R150 | Certificate of patent (=grant) or registration of utility model |
Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
| FPAY | Renewal fee payment (prs date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20080903 Year of fee payment: 4 |
|
| FPAY | Renewal fee payment (prs date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20080903 Year of fee payment: 4 |
|
| FPAY | Renewal fee payment (prs date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20090903 Year of fee payment: 5 |
|
| FPAY | Renewal fee payment (prs date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20090903 Year of fee payment: 5 |
|
| FPAY | Renewal fee payment (prs date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20100903 Year of fee payment: 6 |
|
| FPAY | Renewal fee payment (prs date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20100903 Year of fee payment: 6 |
|
| FPAY | Renewal fee payment (prs date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20110903 Year of fee payment: 7 |
|
| FPAY | Renewal fee payment (prs date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20120903 Year of fee payment: 8 |
|
| FPAY | Renewal fee payment (prs date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20120903 Year of fee payment: 8 |
|
| FPAY | Renewal fee payment (prs date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20130903 Year of fee payment: 9 |
|
| LAPS | Cancellation because of no payment of annual fees |