JPH11176836A - Semiconductor device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device containing a high breakdown voltage bipolar transistor which is capable of coping with high speed operation and ensuring a specified breakdown voltage, and its manufacturing method. SOLUTION: In a base region 2 constituted of a bas layer 19 and a graft base layer 18 around the base layer 19, an epitaxial layer 12 containing the vicinity of the outer peripheral part, where the junction surface of the graft base layer 18 is bent, is etched by an anisotropic plasma etching method, and a new base region 3 having an island structure is formed. Thereby the junction surface in the vicinity of the outer peripheral part of the graft base layer 18 intersects almost perpendicularly the sidewall surface of the new base region 3 having the island type structure.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device having a high breakdown voltage bipolar transistor capable of operating at high speed and a method of manufacturing the same.

[0002]

2. Description of the Related Art An example of a conventional semiconductor device including a high-breakdown-voltage bipolar transistor compatible with high-speed operation and a method of manufacturing the same will be described with reference to FIG. First, as shown in FIG. 5A, selective ion implantation for forming an N ⁺ -type collector buried layer 13 and a first element isolation layer 14, which will be described later, on the surface of the P-type semiconductor substrate 11, A heat treatment for diffusing the implanted ions is performed.

Next, a low concentration, for example, 1E15, is deposited on the P-type semiconductor substrate 11 by vapor phase epitaxial crystal growth.
An N-type epitaxial layer having a large thickness, for example, about 10 μm, into which an impurity of about / cm ³ is introduced is formed. After the above diffusion heat treatment and epitaxial growth process,
The implanted ions diffuse into the semiconductor substrate 11 and the epitaxial layer 12 to form an N ⁺ -type collector buried layer 13 and a first element isolation layer 14 as shown in FIG. Then, a thin SiO ₂ film 15 is formed by thermal oxidation.
To form

[0004] Next, on the surface of the epitaxial layer 12, a collector extraction region 16 and a second element isolation layer 17 described later are formed.
Is selectively performed, and then thermal diffusion is performed for a long time to form the collector extraction region 16 and the second element isolation layer 17. The collector extraction region 16 and the collector buried layer 13 are formed. Are connected, and the second element isolation layer 17 and the first element isolation layer 14 are connected.

Next, as shown in FIG. 5B, selective ion implantation for forming the graft base layer 18 of the bipolar transistor portion 1 is performed on the surface of the epitaxial layer 12 and then thermal diffusion is performed. Then, a graft base layer 18 having a junction depth of about 3 μm is formed. Next, selective ion implantation for forming a base layer 19 described later is performed, and thereafter, heat treatment is performed to diffuse the implanted ions and activate the ions, thereby forming the base layer 19. .

Next, as shown in FIG. 5C, selective ion implantation for forming an emitter layer 20 and a collector electrode extraction layer 21 and the like, which will be described later, is performed. Is performed to form the emitter layer 20, the collector electrode extraction layer 21, and the like.

Thereafter, although not shown in the drawings, a CVD SiO ₂ film or the like is deposited as necessary, and then electrodes are formed on the upper insulating films such as the emitter layer 20, the graft base layer 18, and the collector electrode lead layer 21. A contact hole for connection is formed, then an electrode film is deposited, and the electrode film is patterned to form an emitter electrode, a base electrode, a collector electrode, and the like. Thereafter, a semiconductor device including a high-breakdown-voltage bipolar transistor is manufactured by forming a passivation film, forming a contact hole in a pad portion, and the like.

As the bipolar transistor of the bipolar transistor section 1 in the semiconductor device manufactured as described above, a resistance of the base layer 19 is reduced, a width of the base layer 19 is reduced, and an epitaxial layer is formed. The series resistance of the collector related to the thickness of the collector is reduced. On the other hand, in order to increase the breakdown voltage of the bipolar transistor of the bipolar transistor portion 1, the breakdown voltage between the base and the collector, particularly, the graft base layer 18 and the epitaxial layer In order to improve the breakdown withstand voltage in the vicinity of the surface of
μm to increase the radius of curvature of the bonding surface at the corner of the graft base layer 18 or optimize the impurity concentration of the base layer 19 and the width of the base layer 19 to reduce the punch-through breakdown voltage between the emitter and the collector. I am trying to improve it.

However, in increasing the breakdown voltage of the bipolar transistor described above, there is a limit to the method of making the thickness of the graft base layer 18 sufficiently large, and the increase in the radius of curvature of the junction surface at the corner portion of the graft base layer 18 increases. There is a problem that it is difficult to make the withstand voltage of the bipolar transistor equal to or higher than a predetermined withstand voltage by increasing the withstand voltage. this is,
If the depth of the graft base layer 18 is too large in order to ensure a predetermined withstand voltage, the distance between the graft base layer 18 and the collector buried layer 13 is reduced, and the portion between the graft base layer 18 and the collector buried layer 13 is opposed. If the withstand voltage is reduced, and if the epitaxial layer 12 is thickened to avoid this, the series resistance of the collector will increase, and the high frequency characteristics of the bipolar transistor will deteriorate. . As described above, in the conventional method of manufacturing a semiconductor device including a high-breakdown-voltage bipolar transistor, it is difficult to ensure that the collector breakdown voltage is equal to or higher than a predetermined withstand voltage while achieving both high speed and high breakdown voltage of the bipolar transistor. There was a problem.

[0010]

In the above-described conventional semiconductor device including a high-breakdown-voltage bipolar transistor and a method of manufacturing the same, the high-breakdown-voltage bipolar transistor maintains a high speed, that is, maintains a high-speed operation characteristic. There is a problem that it is difficult to reliably maintain a collector breakdown voltage higher than a predetermined breakdown voltage. SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and has as its object to provide a semiconductor device including a high-breakdown-voltage bipolar transistor capable of securing a predetermined withstand voltage at a high speed and a method of manufacturing the same. .

[0011]

SUMMARY OF THE INVENTION A semiconductor device and a method of manufacturing the same according to the present invention are proposed to solve the above-mentioned problems. The present invention relates to a semiconductor device including a high breakdown voltage bipolar transistor. A base region formed on the surface of the epitaxial layer on the semiconductor substrate, the base region including the base layer of the high breakdown voltage bipolar transistor and the graft base layer around the base layer is a predetermined region from the surface of the epitaxial layer around the base region. Have a height,
The side wall has a substantially vertical island-like structure, and the bonding surface of the graft base layer near the outer periphery of the graft base layer is:
It is characterized by being substantially orthogonal to the side wall surface.

Further, a method of manufacturing a semiconductor device according to the present invention
In a method for manufacturing a semiconductor device including a high breakdown voltage bipolar transistor, a step of forming a collector buried layer on a surface of a semiconductor substrate; and a step of forming an epitaxial layer.
Forming a base region comprising a base layer and a graft base layer around the base layer on the surface of the epitaxial layer; and an anisotropic plasma etching method in which the bonding surface of the graft base layer is curved, Etching the epitaxial layer including the outer edge, forming an island-shaped base region having a predetermined height from the surface of the etched epitaxial layer and having substantially vertical side walls; and Forming an insulating film on the surface of the etched epitaxial layer including the side wall of the above.

According to the present invention, the junction surface of the graft base layer in the base region can be made substantially perpendicular to the side wall surface of the base region in the island-like structure by configuring the high breakdown voltage bipolar transistor as described above. When a voltage is applied between the base layer and the collector of the bipolar transistor, the equipotential surface becomes substantially parallel in the vicinity of the junction surface of the graft base layer where the electric field becomes maximum, and the electric field is locally increased as in the conventional example. And a withstand voltage substantially equal to the withstand voltage between the base and the collector determined by the distance between the graft base layer and the collector buried layer and the impurity concentration of the epitaxial layer therebetween. Therefore, it is possible to increase the speed, that is, to manufacture a semiconductor device including a high-breakdown-voltage bipolar transistor capable of maintaining a favorable high-frequency characteristic and securing a predetermined withstand voltage.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, specific embodiments of the present invention will be described with reference to the accompanying drawings. The same components as those in FIG. 5 referred to in the description of the prior art are denoted by the same reference numerals.

Embodiment 1 In this embodiment, an example of a semiconductor device including a high breakdown voltage bipolar transistor compatible with high speed and an example of a method of manufacturing the semiconductor device will be described with reference to FIGS. First, FIG.
As shown in (a), after a thermal oxide film having a thickness of about 30 nm is formed on the surface of a semiconductor substrate, for example, a P-type semiconductor substrate 11, an N-type impurity is formed by ion implantation using a patterned photoresist as a mask. Ions, for example, P ions are implanted under ion implantation conditions of an implantation energy of about 50 keV and a dose of about 3E15 / cm ² ,
Subsequently, using the newly patterned photoresist as a mask, ions serving as P-type impurities, for example, B ions are implanted at an energy of about 30 keV and a dose of about 1E15 /
implantation under ion implantation conditions of about ² cm ^2,
By performing a heat treatment at 00 ° C. for about 300 minutes, the collector buried layer 13 and the first element isolation layer 14 are formed at predetermined locations.

Next, after the thermal oxide film formed on the surface of the semiconductor substrate 11 is removed, an N-type low concentration impurity, for example, an impurity of about 1E15 / cm ³ is formed on the semiconductor substrate 11 by a vapor phase epitaxial crystal growth method. Is formed to a thickness of about 10 μm. After the epitaxial layer 12 is formed, the collector buried layer 13 and the first element isolation layer 1 formed on the semiconductor substrate 11 are formed.
4 also diffuses to the epitaxial layer 12 side, forming a collector buried layer 13 and a first element isolation layer 14 as shown in FIG. Then, by the thermal oxidation method,
For example, an SiO ₂ film 15 having a thickness of about 30 nm is formed.

Next, ions serving as N-type impurities, for example, P ions are implanted into the surface of the epitaxial layer 12 by ion implantation using a photoresist patterned as a mask, with an energy of about 50 keV and a dose of about 2E1.
It is implanted under ion implantation conditions of about 5 / cm ² , and then, using a new patterned photoresist as a mask,
P-type impurities, for example, B ions are implanted under ion implantation conditions at an implantation energy of about 30 keV and a dose of about 1E15 / cm ² , and then at about 1100 ° C.
A heat treatment of about 500 minutes is performed to form the collector extraction region 16 and the second element isolation layer 17 and the like, connect the collector extraction region 16 to the collector buried layer 13, and form the second element isolation layer 17 and the first element isolation layer 17. Is connected to the element isolation layer 14.

Next, as shown in FIG. 1B, selective ion implantation into an epitaxial layer for forming a graft base layer 18 to be described later is performed by using an ion implantation method with a patterned photoresist as a mask. , For example B
Using F ₂ ions, implantation energy about 50 keV,
Ion implantation is performed at a dose of about 2E15 / cm ² .
After that, the implanted B ions are diffused by heat treatment,
A graft base layer 18 having a layer thickness, that is, a depth up to a joint, for example, about 3 μm is formed. Next, using a patterned photoresist as a mask by ion implantation, selective ion implantation into an epitaxial layer for forming a base layer 19 to be described later, for example, using BF ₂ ions at an implantation energy of about 50 keV and a dose of about 50 keV. About 1
An ion implantation of about E14 / cm ² is performed. Thereafter, for example, heat treatment is performed at 900 ° C. for about 30 minutes to form the base layer 19. The above-mentioned graft base layer 18
In order to reduce the base resistance related to the high-speed characteristics of a bipolar transistor, so-called high-frequency characteristics, the base layer 1
9 is formed. The base layer 19 described above and the graft base layer 1 around the base layer 19
8 form the base region 2.

Next, as shown in FIG.
For example, the SiN film 30 formed by the plasma CVD method has a thickness of about 2
Deposit about 00 nm. Thereafter, the SiN film 30, the SiO ₂ film 15, and the epitaxial layer 12 are etched by anisotropic plasma etching using the patterned photoresist as a mask.

By this etching, the curved portion of the bonding surface of the graft base layer 18 at the outer edge of the graft base layer 18 shown in FIG. 1B is etched, and the etched epitaxial layer outside the base region 2 is etched. A new base region 3 having an island-like structure having a predetermined height H from the surface 12 and a substantially vertical side wall is formed.
The predetermined height H is, for example, about 5 μm. In the new base region 3 having the island-like structure formed as described above, the bonding surface of the graft base layer 18 and the side wall surface are substantially orthogonal to each other. Here, when the distance from the surface of the graft base layer 18 to the bonding portion is L ₁ and the distance from the bonding surface of the graft base layer 18 to the collector buried layer 13 is L ₂ , the predetermined height H is , L ₁ + L ₂ /
It is desirable that 4 ≦ H ≦ L ₁ + L ₂ . This is because, by etching the epitaxial layer 12 below the bonding surface of the graft base layer 18, the equipotential surface near the bonding portion of the graft base layer 18 where the maximum electric field is generated becomes substantially parallel, and the local potential as in the conventional example is obtained. This is because generation of a place where the electric field is large can be suppressed.

Next, the surface of the epitaxial layer 12 including the side wall surface of the island-shaped base region 3 etched by the above-described anisotropic plasma etching method is formed on the surface of the epitaxial layer 12 by a thermal oxidation method, for example, to a thickness of about 20 nm. ₂ film 31
To form

Next, as shown in FIG. 2 (d), by a CVD method, for example, after depositing a CVD SiO ₂ film having a thickness of about approximately 7 [mu] m, the CVD SiO ₂ film, CMP (Ch
electrical Mechanical Polish
ng) method until the SiN film 30 in the base region 3 is exposed, and the SiO ₂ film 3 in the region of the epitaxial layer 12 etched by the anisotropic plasma etching method.
1, a CVD SiO ₂ film 32 is formed.

Next, as shown in FIG. 2E, the SiN film 30 in the base region 3 is removed by etching, for example, by a wet etching method. Thereafter, a photoresist 23 is applied, and the photoresist 33 is patterned to form an opening 34 of the photoresist 33. Thereafter, the patterned photoresist 33 as a mask, for example, using anisotropic plasma etching method to etch the CVD SiO ₂ film 32 and the SiO ₂ film 31 to form an opening 35.

Next, after removing the photoresist 33,
As shown in FIG. 2F, after a new photoresist 36 is applied, the photoresist 36 is patterned to form an opening 37 and an opening 38. Thereafter, ions serving as N-type impurities, for example, As ions are implanted into the surface of the base layer 19 of the base region 3 and the surface of the collector lead-out region 16 using the above-described patterned photoresist 36 as a mask by ion implantation. Then, implantation is performed under ion implantation conditions with a dose of about 1E16 / cm ² to form an ion implantation layer 39 for an emitter on the surface of the base layer 19 and an ion implantation layer 40 for a collector electrode on the surface of the collector extraction region 16.

Thereafter, although not shown in the drawings, the emitter ion implantation layer 39 and the collector electrode extraction ion implantation layer 40 on the surface of the collector extraction region 16 are subjected to a heat treatment for activating implanted ions, for example, at 950 ° C. 30
By performing about min, an emitter layer and a collector electrode leading layer are formed. After that, if necessary, C
A VDSiO ₂ film or the like is deposited, and thereafter, a contact hole for connecting an electrode to an upper insulating film such as an emitter layer, a graft base layer 18, a collector electrode lead layer, and the like is formed, and then an electrode film is deposited. The electrode film is patterned to form an emitter electrode, a base electrode, a collector electrode, and the like. Thereafter, a semiconductor device including a high-breakdown-voltage bipolar transistor is manufactured by forming a passivation film, forming a contact hole in a pad portion, and the like.

In the above-described semiconductor device and the method of manufacturing the same, the graft base of the bipolar transistor portion 1 is formed while adopting the structure of the bipolar transistor portion 1 adapted for high-speed operation by reducing the thickness of the epitaxial layer 12 and the base resistance. Since the junction surface of the layer 18 is substantially perpendicular to the side wall surface of the island-shaped base region 3, the graft base layer 18 has a maximum electric field when a voltage is applied between the base and the collector of the bipolar transistor. And the equipotential surface near the junction surface becomes substantially parallel, eliminating the occurrence of a locally large electric field as in the prior art. The distance between the graft base layer 18 and the collector buried layer 13 and the impurity concentration of the epitaxial layer 12 between them are reduced. , A breakdown voltage substantially equal to the breakdown voltage between the base and the collector determined by Therefore, speeding up, that is, maintaining good high frequency characteristics,
It is possible to manufacture a semiconductor device including a bipolar transistor with a high withstand voltage that can ensure a predetermined withstand voltage.

Embodiment 2 In this embodiment, an example of a semiconductor device which is compatible with high speed and includes a high breakdown voltage bipolar transistor and an example of a manufacturing method thereof will be described with reference to FIGS. First, FIG.
As shown in (a), as in the first embodiment, P
A buried collector layer 13 and a first element isolation layer 14 were formed at predetermined locations on the surface of a semiconductor substrate 11 of a mold type, an epitaxial layer 12 was formed on the semiconductor substrate 11, and an SiO ₂ film was formed on the surface of the epitaxial layer 12. Thereafter, a collector extraction region 16 connected to the collector buried layer 13 and a second element isolation layer 17 connected to the first element isolation layer 14 are formed.

Next, as shown in FIG. 3B, a graft base layer 18 and a base layer 19 are formed in the same manner as in the first embodiment.

Next, as shown in FIG.
For example, the SiN film 30 formed by the plasma CVD method has a thickness of about 2
Deposit about 00 nm. Thereafter, the SiN film 30, the SiO ₂ film 15, and the epitaxial layer 12 are etched by anisotropic plasma etching using the patterned photoresist as a mask.

By this etching, a region outside the curved portion of the bonding surface of the graft base layer 18 and inside the collector drawing region 16 at the outer edge of the graft base layer 18 shown in FIG. By forming the groove as shown in FIG. 3 (c), a new base region 3 having an island-like structure with a substantially vertical side wall and a predetermined height H from the bottom of the groove is formed. The predetermined height H is, for example, about 6 μm. In the new base region 3 having the island-like structure formed as described above, the bonding surface of the graft base layer 18 and the side wall surface are substantially orthogonal to each other. Here, when the distance from the surface of the graft base layer 18 to the bonding portion is L ₁ and the distance from the bonding surface of the graft base layer 18 to the collector buried layer 13 is L ₂ , the predetermined height H is _{, L 1 + L 2/4} ≦ H ≦ L 1 +
It is desirable that L _2. This is because, by etching the epitaxial layer 12 below the bonding surface of the graft base layer 18, the equipotential surface near the bonding portion of the graft base layer 18 where the maximum electric field is generated becomes substantially parallel, and the local potential as in the conventional example is obtained. This is because generation of a place where the electric field is large can be suppressed.

Next, on the surface of the epitaxial layer 12 in the groove including the side wall surface of the base region 3 having the island structure, which is etched by the above-described anisotropic plasma etching method,
By thermal oxidation, for example, SiO _{2 having a} thickness of about 20 nm
A film 31 is formed. Thereafter, a CVD SiO ₂ film 41 having a thickness of, for example, about 2 μm is formed by the CVD method.

Next, as shown in FIG.
The iO ₂ film 41 is coated with the Si of the base region 3 by the CMP method.
Polishing is performed until the N film 30 is exposed, and the groove is filled in the region etched by the anisotropic plasma etching method. After that, the SiN film 30 in the base region 3 is removed by etching, for example, by a wet etching method.

Next, ions serving as N-type impurities, for example, As ions, are implanted into the surface of the base layer 19 of the base region 3 and the surface of the collector extraction region 16 by ion implantation using a patterned photoresist as a mask. 50 keV, dose amount about 1E16 / cm
The implantation is performed under the ion implantation conditions of ² , and then heat treatment for activating the implanted ions, for example, 950 ° C., 30 mi
By performing a heat treatment of about n, an emitter layer 20 and a collector electrode lead layer 21 are formed.

Thereafter, although not shown in the drawings, a CVD SiO ₂ film or the like is deposited as necessary, and then electrodes are formed on the upper insulating films such as the emitter layer 20, the graft base layer 18, and the collector electrode lead layer 21. A contact hole for connection is formed, then an electrode film is deposited, and the electrode film is patterned to form an emitter electrode, a base electrode, a collector electrode, and the like. Thereafter, a semiconductor device including a high-breakdown-voltage bipolar transistor is manufactured by forming a passivation film, forming a contact hole in a pad portion, and the like.

In the above-described semiconductor device and the method of manufacturing the same, the graft base of the bipolar transistor portion 1 is adopted while adopting the structure of the bipolar transistor portion 1 adapted for high-speed operation by reducing the thickness of the epitaxial layer 12 and the base resistance. Since the junction surface of the layer 18 is substantially perpendicular to the side wall surface of the island-shaped base region 3, the graft base layer 18 has a maximum electric field when a voltage is applied between the base and the collector of the bipolar transistor. And the equipotential surface near the junction surface becomes substantially parallel, eliminating the occurrence of a locally large electric field as in the prior art. The distance between the graft base layer 18 and the collector buried layer 13 and the impurity concentration of the epitaxial layer 12 between them are reduced. , A breakdown voltage substantially equal to the breakdown voltage between the base and the collector determined by Therefore, speeding up, that is, maintaining good high frequency characteristics,
It is possible to manufacture a semiconductor device including a high breakdown voltage bipolar transistor capable of securing a predetermined breakdown voltage.

Although the present invention has been described with reference to the two embodiments, the present invention is not limited to these embodiments. For example, in the embodiments of the present invention, the high breakdown voltage bipolar transistor has been described as an NPN type bipolar transistor. However, it is obvious that the high breakdown voltage bipolar transistor may be a PNP type bipolar transistor. Further, in the embodiment of the present invention, although an insulating film formed on the epitaxial layer surface of the etched regions in an anisotropic plasma etching process is described as SiO ₂ film by thermal oxidation method, SiO ₂ by a high temperature CVD method It may be a membrane. In addition, the process conditions can be appropriately changed within the scope of the technical idea of the present invention.

[0037]

As is apparent from the above description, the semiconductor device including the high-breakdown-voltage bipolar transistor of the present invention and the method of manufacturing the same have a high-speed bipolar device with reduced epitaxial layer thickness and base resistance. Since the junction surface of the graft base layer of the bipolar transistor portion is substantially orthogonal to the side wall surface of the island-shaped base region while employing the transistor portion configuration, a voltage is applied between the base and the collector of the bipolar transistor. When an electric field is applied, the equipotential surfaces near the junction surface of the graft base layer where the electric field becomes maximum become substantially parallel, and there is no place where the electric field is locally large as in the conventional example. The breakdown voltage between the base and collector is determined by the distance and the impurity concentration of the epitaxial layer between them. The breakdown voltage can be obtained. Therefore, speedup,
That is, it is possible to manufacture a semiconductor device including a high withstand voltage bipolar transistor that can maintain good high-frequency characteristics and maintain a predetermined withstand voltage.

[Brief description of the drawings]

FIGS. 1A and 1B are schematic cross-sectional views of a bipolar transistor portion of a semiconductor device in which the first half of a process according to a first embodiment of the present invention is described in the order of processes. FIG. Is formed, a SiO ₂ film is formed, (b) is a state in which a graft base layer or a base layer is formed, and (c) is a SiN film, a SiO ₂ film and an epitaxial layer are etched to form an island-like base. In this state, a region is formed, and then a SiO ₂ film is formed on the surface of the etched epitaxial layer.

[Figure 2] explaining the second half in the order of steps of the present invention the applied example of the embodiment 1, step a schematic cross-sectional view of a bipolar transistor portion of the semiconductor device, (d) is deposited CVD SiO ₂ film, the CVD SiO ₂ The state in which the film is polished and flattened by the CMP method, and FIG.
An opening is formed in a VDSiO ₂ film or the like, and FIG. 7F shows a state in which an ion implantation layer for an emitter and an ion implantation layer for extracting a collector electrode are formed by an ion implantation method.

FIGS. 3A and 3B are schematic cross-sectional views of a bipolar transistor portion of a semiconductor device in which the first half of a process according to a second embodiment of the present invention is described in the order of processes; FIG. Is formed, a SiO ₂ film is formed, (b) is a state in which a graft base layer or a base layer is formed, and (c) is a SiN film, a SiO ₂ film and an epitaxial layer are etched to form an island-like base. In this state, a region is formed, a SiO ₂ film is formed on the surface of the etched epitaxial layer, and a CVD SiO ₂ film is deposited.

[4] will be described later in the present invention the applied example of the embodiment 2 steps in the order of steps, in schematic cross-sectional view of a bipolar transistor portion of the semiconductor device, the (d) of CVD SiO ₂ film C
The state in which the SiN film is removed after polishing and flattening by the MP method, and the state (e) in which an emitter layer and a collector electrode lead layer are formed.

FIGS. 5A and 5B are schematic cross-sectional views of a bipolar transistor portion of a semiconductor device, illustrating manufacturing steps of a semiconductor device including a high breakdown voltage bipolar transistor according to a conventional example, in which FIG. 5A is a collector leading region and a second element isolation layer; Is formed, a state in which an SiO ₂ film is formed, (b) is a state in which a graft base layer and a base layer are formed, and (c) is a state in which an emitter layer and a collector electrode lead layer are formed.

[Explanation of symbols]

1 ... Bipolar transistor part, 2,3 ... Base region,
11 semiconductor substrate, 12 epitaxial layer, 13 collector buried layer, 14 first element isolation layer, 15, 3
1: SiO ₂ film, 16: Collector lead-out area, 17:
Second element isolation layer, 18: graft base layer, 19: base layer, 20: emitter layer, 21: collector electrode lead layer, 30: SiN film, 32, 41: CVDSiO
₂ films, 33, 36 ... photoresist, 34, 35, 3
7, 38: opening, 39: ion implantation layer for emitter, 40
... Ion-implanted layer for extracting collector electrode

Claims (6)

[Claims] 1. A semiconductor device including a high breakdown voltage bipolar transistor, comprising: a base layer of the high breakdown voltage bipolar transistor formed on a surface of an epitaxial layer on a semiconductor substrate; and a graft base layer around the base layer. A base region having a predetermined height from the surface of the epitaxial layer at an outer peripheral portion of the base region and an island-like structure having substantially vertical side walls, and a bonding surface of the graft base layer near an outer peripheral portion of the graft base layer; Is a semiconductor device substantially orthogonal to the side wall surface. 2. The semiconductor device according to claim 1, wherein an insulating film is formed on at least a surface of the side wall of the island-shaped base region. Wherein the distance to the joint surface of the graft base layer made substantially parallel to the collector buried layer from the surface of the graft base layer and L _1, the distance to the collector buried layer than the bonding surface of the graft base layer when was the L _2, wherein the predetermined height _{H, L 1 + L 2/4} ≦ H ≦ L 1
The semiconductor device according to claim 1, wherein + L ₂ . 4. A method for manufacturing a semiconductor device including a high breakdown voltage bipolar transistor, comprising: forming a collector buried layer on a surface of a semiconductor substrate; forming an epitaxial layer; and forming a base layer and the base on the surface of the epitaxial layer. Forming a base region consisting of a graft base layer around the layer; and the epitaxial layer including an outer edge of the graft base layer in a region where a bonding surface of the graft base layer is curved by an anisotropic plasma etching method. Etch
Forming an island-shaped base region having a predetermined height from the surface of the etched epitaxial layer and having a substantially vertical side wall; and Forming an insulating film on the surface of the epitaxial layer. 5. An etching region of the epitaxial layer including an outer edge portion of the graft base layer is only an outer peripheral region of the graft base layer between the graft base layer and a collector extraction region connected to the collector buried layer. The method for manufacturing a semiconductor device according to claim 4, wherein: 6. The distance to the joint surface of the graft base layer made substantially parallel to the collector buried layer from the surface of the graft base layer and L _1, the distance to the collector buried layer than the bonding surface of the graft base layer when was the L _2, wherein the predetermined height _{H, L 1 + L 2/4} ≦ H ≦ L 1
The method for manufacturing a semiconductor device according to claim 4, wherein the value is + L ₂ .