JPH1117540A - Semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To attain a D/A conversion circuit in the same semiconductor integrated circuit whose output characteristic is settled within an error of 0.1% or below. SOLUTION: A current mirror circuit 102 receives a current given by an external reference current source 101, the current is distributed into three signals, which are fed to current mirror fine-adjustment circuits 103. Each D/A conversion circuit 104 converts a digital input signal into an analog signal based on an output current of each current mirror fine-adjustment circuits 103 as a reference current and provides an output of the analog signal. The signal from each D/A converter circuit 104 is compared with a reference signal at a comparator circuit 105, and a current mirror fine-adjustment control circuit 106 outputs a control signal to apply negative correction to a higher channel output or to apply positive correction to a lower channel output to each current mirror fine-adjustment circuits 103. The comparison is made again and the correction loop is used repetitively.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a plurality of digital
The present invention relates to a semiconductor integrated circuit having an analog conversion circuit, and particularly to a method for achieving high accuracy.

[0002]

2. Description of the Related Art Conventionally, as shown in FIG. 5, a semiconductor integrated circuit having a plurality of digital-to-analog conversion circuits 501 generally includes a digital-to-analog converter 501 in the same semiconductor integrated circuit.
Although the output characteristics of the analog conversion circuit are almost equal to the difference within 1% to 2%, it is difficult to obtain a higher accuracy. In general, in a semiconductor integrated circuit, a current value of a desired ratio is generally obtained by using a circuit called a current mirror. The current mirror circuit can obtain extremely high accuracy in principle, but in reality, the operating point differs due to a difference in load conditions or uneven temperature, and therefore, an error occurs in the current mirror output current. There are cases. In particular, with the recent increase in the scale, miniaturization, and speeding up of semiconductor integrated circuits, there have been cases in which an output current error of 1% to 2% occurs mainly due to uneven temperature.

[0003]

SUMMARY OF THE INVENTION The present invention seeks to correct the above-mentioned error, and has a higher accuracy, approximately 0.1.
The purpose is to achieve an accuracy of 1% or less.

[0004]

A semiconductor integrated circuit according to the present invention includes a current mirror circuit for receiving an external reference current source and generating a current proportional thereto, and a distribution circuit for distributing the current mirror circuit current to each channel. A current mirror fine adjustment circuit for finely adjusting the distribution circuit current; and a plurality of digital / analog conversion circuits for receiving the digital signal and converting the current mirror fine adjustment circuit current into an analog signal as a reference current. A comparison circuit for comparing the output of the analog conversion circuit with the output of another channel, and a current mirror fine adjustment control circuit for receiving the output of the comparison circuit and generating a control signal for finely adjusting the current for each channel. Features.

[0005]

As described above, in the case of a configuration having a plurality of digital-to-analog conversion circuits, the outputs of the digital-to-analog conversion circuits are compared for the plurality of channels by the comparison circuit, and then the control signals of the current mirror fine adjustment control circuit are used. Since the error can be corrected by finely adjusting the current mirror current, a plurality of digital / analog conversion circuit outputs can be obtained with high accuracy.

[0006]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the operation of the present invention will be described in detail based on embodiments.

FIG. 1 shows an embodiment of the present invention. The current mirror circuit 102 receives a current supplied from the external reference current source 101 from an external reference current source input terminal. Distribution circuit 10 that distributes the current received by current mirror circuit 102
The current is input to the current mirror fine adjustment circuit 103 by dividing into two by two. At this point, the current mirror fine adjustment circuit 103 does not function yet, and the current received by the distribution circuit 102 is directly input to the digital / analog conversion circuit 104. The digital / analog conversion circuit 104 converts the digital signal input into an analog signal using the output current of the current mirror fine adjustment circuit 103 as a reference current, and outputs the analog signal. The signal output from the digital / analog conversion circuit 104 is switched by a built-in switch so that the same channel is not selected, and the two channel outputs are compared by the comparison circuit 1
The control signal is output from the current mirror fine-adjustment control circuit 106 to perform a negative correction for the larger channel output or to perform a positive correction for the smaller channel output. Is input to The comparison is performed again, and the above-described correction loop is repeated. When the output state of the comparison circuit 105 is inverted, the above-described loop is terminated, so that the digital / digital conversion is performed.
The two channel outputs of the analog conversion circuit 104 are almost at the same level, and the correction is completed. Digital
The output residual error of the analog conversion circuit 104 is at most equal to or less than the correction component, and a highly accurate output can be obtained.

FIG. 2 shows a configuration example of a current mirror circuit and a distribution circuit according to an embodiment of the present invention.

From the external reference current source input terminal, the PMOS transistor 201 that converts the current supplied from the external reference current source 101 into a current usable by the digital / analog conversion circuit 104 flows the current i21 in the direction of the arrow. The plurality of PMOS transistors 202 that perform a current mirror operation in response to the voltage generated by the current i21 are connected to the currents i22 and i2.
3. Generate and distribute i24. The current flowing through each PMOS at this time is as follows: i21 = i22 = i23 = i24. The NMOS transistors 203 that invert the currents i22, i23, and i24 respectively and current mirror again generate currents i25, i26, and i27, respectively, and use the current mirror fine adjustment circuit 1 as a current mirror current.
03 is input.

FIG. 3 shows a configuration example of a current mirror fine adjustment control circuit according to an embodiment of the present invention.

The current mirror current 204 shown in FIG.
205 and 206 are current mirror current regeneration PMOS transistors 304 that generate a current i31. Current i31
The current mirror current fine-tuning PMOS transistor control signal line 302 controls whether the voltage generated in step (1) is received by the gate 305 of each current mirror current fine-adjustment PMOS transistor 301 or is passed as it is. Current mirror small current generation PMOS
When the transistor control signal line 302 is at logic 1,
Current mirror current fine adjustment PMOS transistor 301
Is connected to the current mirror current 204 and the current i32 can be added to the current mirror current 204. When the current mirror minute current generating PMOS transistor control signal line 302 is logic 0, the gate 3 of the current mirror current minute adjusting PMOS transistor 301
05 is connected to the VDD potential, and the current mirror current fine adjustment PMOS transistor is turned off.
Is not added to the current mirror current 204.
Here, the current capability of the current mirror current fine adjustment PMOS transistor 301 is the current mirror current regeneration PMOS transistor
The current mirror current fine-adjustment PMOS transistor 301 has a current capacity of about one thousandth to one hundredth of the current capacity of the S transistor 304, and the total number of the PMOS transistors 301 is five to five.
It is assumed to be zero.

FIG. 4 shows a configuration example of a digital / analog conversion circuit according to an embodiment of the present invention.

When the channel 1 reference level signal line 204 is input to a plurality of arbitrary current generating PMOS transistors 401, an arbitrary current is generated, and a digital signal input line 405 is generated.
Digital-to-analog converter output switch 4
02 is turned on, the outputs of all the turned on digital / analog conversion circuit output switches 402 are added to respective arbitrary currents on a digital / analog conversion circuit output line 404,
A desired output current can be obtained. Alternatively, when the digital / analog conversion circuit non-output switch 403 is turned on, the output of the arbitrary current generating PMOS transistor 401 can be supplied to VSS, and the output can be made non-output.

Similarly, the channel 2 reference level signal line 205 and the channel 3 reference level signal line 206 of FIG. 2 operate as described above.

[0015]

As described above, according to the semiconductor integrated circuit of the present invention, the error in which the output characteristic of the digital-to-analog conversion circuit within the same semiconductor integrated circuit is within 1% to 2% is the same by comparing the outputs. Digital-to-analog conversion circuit output characteristics in semiconductor integrated circuit is 0.1
% Or less, and high accuracy can be achieved.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a semiconductor integrated circuit according to an embodiment of the present invention.

FIG. 2 is a diagram of a configuration example of a current mirror circuit and a distribution circuit indicated by reference numeral 102 in FIG.

FIG. 3 is a diagram of a configuration example of a current mirror current fine adjustment circuit indicated by reference numeral 103 in FIG. 1;

FIG. 4 is a diagram of a configuration example of a digital / analog conversion circuit indicated by 104 in FIG. 1;

FIG. 5 is a configuration diagram of a conventional semiconductor integrated circuit.

[Explanation of symbols]

101: external reference current source 102: current mirror circuit and distribution circuit 103: current mirror current fine adjustment circuit 104: digital / analog conversion circuit 105 ... Comparison circuit (comparator) 106... Current mirror current fine adjustment control circuit 201... Current mirror current generation PMOS transistor 202... Current mirror current distribution PMOS Transistor 203: Current mirror current inverting NMOS transistor 204: Channel 1 reference level signal line 205: Channel 2 reference level signal line 206: Channel 3 reference Level signal line 301: current mirror weak current generation PMOS
Transistor 302: Current mirror small current generation PMOS
Transistor control signal line 303: Current mirror weak current generation PMOS
Transistor control signal logic inversion circuit 304 PMOS transistor for current mirror current regeneration
Transistor 401 ... Any current generating PMOS transistor 402 ... Digital / analog conversion circuit output switch 403 ... Digital / analog conversion circuit non-output switch 404 ... Digital・ Analog conversion circuit output line 405 ・ ・ ・ ・ ・ ・ Digital signal input line 406 ・ ・ ・ ・ ・ ・ Digital signal input logic inversion circuit

Claims (1)

[Claims] 1. A current mirror circuit for receiving an external reference current source and generating a current proportional thereto, a distribution circuit for distributing the current mirror circuit current to each channel, and a current mirror fine for finely adjusting the distribution circuit current. An adjustment circuit, and a plurality of digital / analog conversion circuits for receiving the digital signal and converting the current mirror fine adjustment circuit current into an analog signal as a reference current, and comparing the output of the digital / analog conversion circuit with the output of another channel A comparison circuit;
A semiconductor integrated circuit comprising a current mirror fine adjustment control circuit for generating a control signal for finely adjusting a current for each channel in response to the output of the comparison circuit.