JPH11175345A - Programmable controller - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a programmable controller capable of changing an OS while keeping a unit mounted on a base. SOLUTION: In this programmable controller for which respective units provided with the respective functions of a CPU unit part 1 for controlling the entire device and an intelligent unit part 2 for realizing an additional function are connected through a bus line, a down-loading unit 3 for writing an operation system to an operating system write object unit to be an object through the bus line by mounting a master 5 storing the operating system of the unit is provided.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a programmable controller for writing an operating system of a programmable controller.

[0002]

2. Description of the Related Art Programmable controllers (hereinafter referred to as P
The operating system (hereinafter, referred to as OS) of the C is stored in a ROM in advance, and the PC is controlled based on the OS stored in the ROM. This OS is
Rewriting may be required due to a function change, version upgrade, removal of a bug, or the like.

FIG. 6 shows two cases of rewriting the OS.
This will be described with reference to FIGS. FIG. 6 is a diagram illustrating a method of writing an OS in a conventional PC. In the figure, reference numeral 6 denotes a master ROM preliminarily storing an OS which is the basis of the operation of an OS writing target unit such as a CPU unit or an intelligent unit, 8 denotes a ROM writer which reads data from the master ROM and copies it to another ROM, and 7 denotes an OS. Is a ROM that is written into the CPU unit or the intelligent unit.

Next, a procedure for writing an OS will be described with reference to FIG. First, the master ROM 6 in which the OS of the target unit is stored in advance is mounted on the ROM writer 8, and the contents of the master ROM 6 are read into the ROM writer 8. Also, the ROM 7 storing the OS to be rewritten is removed from the target unit, and
7 is mounted on the ROM writer 8 from which the contents of the master ROM 6 have been read. Next, the contents of the master ROM read into the ROM writer by the ROM writer 8 are copied to the ROM 7, and the ROM 7 is mounted on the target unit again, so that the target unit can operate based on the OS written in the ROM. Become.

FIG. 7 is a diagram showing a method of writing an OS to a conventional intelligent unit by serial communication.
In the figure, reference numeral 2A denotes an intelligent unit, and 5A denotes a master in which an OS is stored in advance, and examples of the medium include a memory card floppy disk and a CD-ROM. Reference numeral 9 denotes a personal computer connected to the intelligent unit 2A by a dedicated cable 10.

[0006] Next, the operation when the OS is written by serial communication will be described. The OS of the intelligent unit 2A is stored in the master 5A in advance. The master 5A is mounted on the personal computer 9, and the contents of the master 5A are read into the personal computer 9. Next, the dedicated cable 10 is connected to the serial port of the personal computer 9 and connected to the intelligent unit 2A. The serial data transmitted from the serial port of the PC 9 is transmitted to the intelligent unit 2
A receives and writes to the internal flash memory,
It becomes operable based on the OS.

FIG. 8 is a diagram showing an internal block diagram of the intelligent unit in FIG. In the figure, reference numeral 101 denotes a CPU for controlling the intelligent unit, 102 denotes a ROM storing a program for performing serial control, 103 denotes a flash ROM for storing an OS, and 104 denotes data written from the personal computer 9. UART to convert to serial signal, 1
Reference numeral 05 denotes a receiver for shaping data received from the personal computer 106 into a waveform. These are connected to the CPU by an internal bus.

The internal operation of the intelligent unit will be described with reference to FIG. The personal computer 9 reads data from the master 5A in which the OS of the intelligent unit is stored, and writes the data to the UART 104. UA
The RT 104 converts the written data into serial data, and transmits the data through the dedicated cable 10 to the intelligent unit 2A connected thereto. The intelligent unit 2A shapes the waveform of the data received from the personal computer 9 by the receiver 105 and sends it to the UART 104 in the intelligent unit. UART104
Converts serial data to parallel data. The CPU 101 sequentially reads the data converted into the parallel data, and writes the data into the F / ROM (flash ROM) 103. This operation is repeated. All OSs required for the operation are F / R
Write to OM103. Normally, to perform these actions,
A predetermined procedure and control of the UART 104 are required, and the program is stored in the ROM 102. The CPU 101 operates based on the contents of the ROM 102 until the OS is completely written in the F / ROM 103.

[0009]

Since the conventional OS writing is performed as described above, in order to change the OS, it is necessary to use a ROM.
If the unit needs to be replaced and the unit is mounted on the base, remove the unit from the base
When U or an intelligent unit is incorporated in the case, it is necessary to disassemble the unit once and take out the printed circuit board from the case, and the OS cannot be easily rewritten. Further, in the case of writing an OS by serial communication, there is a problem in that if the amount of the OS increases, it takes a very long time to write the OS, thereby lowering productivity.

A first object of the present invention is to provide a programmable controller capable of changing an OS while a unit is mounted on a base. A second object is to provide a programmable controller capable of writing an OS at high speed.

[0011]

A programmable controller according to the present invention has a CPU unit for controlling the entire apparatus and an intelligent unit for implementing additional functions, each unit having each function connected via a bus line. The programmable controller has a download unit that writes the operating system to a target operating system writing target unit via the bus line by mounting a master storing the operating system of the unit.

Further, by changing the connection between each unit and the bus line and directly connecting the download unit and the unit to which the operating system is to be written, the operating system is written from the download unit.

Further, the connection between each unit and the bus line is changed by a download signal generated when the download unit is attached to the bus line.

In a programmable controller in which each unit having each function of a CPU unit for controlling the entire apparatus and an intelligent unit for implementing additional functions is connected via a bus line,
The unit unit includes an interface unit for mounting a master in which the operating system of the operating system writing target unit is stored, and a writing unit that writes the operating system to the operating system writing target unit via the bus line. It is.

Further, a command to switch the internal bus is issued to the unit to be written to the operating system,
The PU unit connects to the ROM inside the operating system write target unit.

Further, a download signal is supplied to a plurality of units to be written with an operating system, and the operating system is written into the plurality of units collectively.

[0017]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiment 1 FIG. 1 is a configuration diagram showing a configuration of a PC according to the first embodiment. In the figure, 1 is a CPU unit for controlling the entire PC device, 2 is an intelligent unit for realizing additional functions such as network connection, analog input / output, positioning, etc., and 3 is for writing an OS to the CPU unit 1 or the intelligent unit 2. Download unit, 4 is CP
The base unit is a bus line including a data bus, an address bus, and a control signal wiring for transmitting and receiving data between units to be mounted, such as the U unit 1, the intelligent unit 2, and the download unit 3. Reference numeral 5 denotes a master in which the OS of the CPU unit 1 or the intelligent unit 2 is stored in advance, for example, a memory card, a CD-ROM, an FD
And the like.

The download unit 3 has a CPU
A data bus, an address bus, a control signal, and a download signal are connected via the unit 1 or the intelligent unit 2 and the base unit 4.

FIG. 2 is a block diagram showing the internal configuration of the intelligent unit 2, download unit 3, and base unit 4 when writing the OS. In the intelligent unit 2, 21 is a CPU for controlling the intelligent unit, 22 is a flash ROM for storing the OS of the intelligent unit 2, 23 is a 2-port memory for exchanging data with the CPU 21 during normal operation, and 24 is an intelligent memory. Unit 2
, The data bus 25, the address bus, and the O
A gate circuit for controlling the address bus 7 and the data bus 8 of the base unit during S download and during normal operation, and includes a gate circuit 26a for controlling the address bus and a gate circuit 26b for controlling the data bus.
Reference numeral 27 denotes a selector for switching between use of a control signal in the intelligent unit and use of a control signal on the base unit in accordance with the download signal 9, and reference numeral 28 denotes a gate.

In the download unit 3, reference numeral 31 denotes a CPU for controlling the download unit 3, and reference numeral 32 denotes a ROM in which a program for controlling the download unit 3 is stored. In the base unit 4, 41 is an address bus, 42 is a data bus, and 43 is a download signal.

Next, with reference to FIGS. 1 and 2, writing of an OS based on the download unit 3, particularly, writing of an OS of the intelligent unit 2 in this embodiment will be described. OS in intelligent unit 2
Due to changes in functions, version upgrades, removal of bugs, etc.,
When it is necessary to rewrite the data, a reset is performed based on the reset switch of the CPU unit 1 to stop the operation of the intelligent unit 2, and the bus of the base unit 4 is released to change to the OS write mode. O
In the writing mode of S, the intelligent unit 3 is mounted on the base unit 4 by a service person who writes an OS such as a manufacturer. Therefore, a circuit for transmitting the download signal 43 of the base unit 4 is connected to the ground, and the download signal 43 is supplied to the gate 26 and the selector 27 of the intelligent unit. As a result, the gates 26a and 26b are opened,
The data bus 24 and the address bus 25 inside the intelligent unit 2 are connected to the address bus and the data bus inside the download unit 3 via the address bus 41 and the data bus 42 inside the base unit 4. On the other hand, the gate 28 is closed (high impedance), and the connection with the CPU 21 is cut off. Also,
In the selector 27, the control signal supplied from the download unit 3 via the base unit 4 becomes effective, and
/ ROM 22 is notified that the OS is to be written.

The CPU 31 of the download unit 3
Intelligent unit 2 via base unit 4
When the access to the address bus, the data bus, and the control signal becomes possible, the OS stored in the master 5 is transferred to the base unit 4 based on the program in the ROM 32.
Address bus 25 of the intelligent unit 2 via the internal buses of the address bus 41 and the data bus 42.
The data is supplied to the data bus 24 and written to the F / ROM 22.

When the OS writing to the F / ROM 22 is completed, the control signal supplied from the download unit 3 to the intelligent unit 2 disappears, and the CPU 21
Shifts to control based on. In the intelligent unit 2, when the end of the OS writing is notified, the service person releases the reset and the mounting of the download unit 3 to the base unit 4, and the supply of the download signal 43 via the base unit 4 is stopped. Therefore, on the intelligent unit 2 side, the gates 26a and 26b close and the gate 28 opens, so that predetermined data is connected to the two-port memory 23 based on the control of the CPU 21 via the address bus 25,
Normal operation becomes possible. That is, the control signal output from the CPU 21 in the intelligent unit is selected by the selector 3, and the address bus, the data bus, and the control signal supplied from the base are not connected to the F / ROM 22.
The program is executed based on the OS written in the.

According to the first embodiment, the OS provided by the service person on the manufacturer side via the download unit 3
The user does not need to prepare a download unit in advance for writing. In addition, it is free from the troublesome work of removing and writing the ROM, and the OS writing via the communication unit, and the OS writing via the internal bus of the base unit. improves. Further, since the service unit connects the download unit to the base unit and writes the OS, the download unit is not required during normal operation, and the device of the programmable controller can be formed compact.

Embodiment 2 FIG. 3 is a block diagram showing an intelligent unit 2 for writing an OS according to Embodiment 2.
FIG. 3 is a block diagram showing an internal configuration of a download unit 3A and a base unit 4. In the first embodiment, the OS writing to the intelligent unit 2 has been described.
CPU unit 1
In the download unit 3A, based on the input address, the OS writing to the
A decoding circuit 33 for controlling output of a download signal to a unit to be written into S is added.

Next, the operation of the second embodiment will be described. The decode circuit 33 in the download unit 3A stores the OS address of the write target unit stored in the master 5 or the download unit 3A.
The output destination of the download signal 43 is changed based on an input or the like based on a switch or the like for selecting which of the units provided for the OS writing is performed. Each unit is
The corresponding download signal is determined (for example, the CPU unit 1 has the download signal 43b,
The intelligent unit 1 has a download signal 43
a) Since the download signal 43c is supplied to the intelligent unit 2, the unit to which the download signal 43 is supplied performs the operation of the above-described first embodiment, thereby enabling the OS writing from the download unit 3A. In other words, the OS can be written collectively for the target units to which the download signal is output. In the second embodiment, the decoding circuit 33
As explained in the example created in the download device 3A,
The same operation can be performed even when a similar circuit is provided inside the intelligent unit 2.

According to the present embodiment, in addition to the effects of the first embodiment, the decoding destination can be determined by the decoding circuit 33 based on the selection switch of the downloading destination, information from the mask 5, and the like. By supplying a download signal to a plurality of units, the download unit and the unit to be written are connected by the bus of the base unit, and the OS can be written to the plurality of units at a time. , OS writing becomes easier.

Embodiment 3 FIG. 4 is a configuration diagram showing a configuration of a PC according to Embodiment 2. In the figure, 1A
Is the CPU unit or intelligent unit 2
C which has an input I / F of the master 5 to perform a download function for writing the OS to the PC and controls the entire PC device
The PU unit 2 is an intelligent unit for realizing additional functions such as network connection, analog input / output, positioning, and the like, and the data bus 4 is for transmitting and receiving data between the mounted units such as the CPU unit 1A and the intelligent unit 2. , An address bus, and wiring for control signals. 5
Is a master in which the OS of the CPU unit 1A or the intelligent unit 2 is stored in advance, and is formed of, for example, a memory card, a CD-ROM, an FD, or the like.

FIG. 5 is a block diagram showing the internal configuration of the intelligent unit 2, download unit 3, and base unit 4 when writing the OS. In the CPU unit 1A, 11 is a CPU, 12 is a ROM,
A control IC 3 generates a download signal for bringing the data bus and the address bus of the intelligent unit 2 into a high impedance state. In addition,
The intelligent unit 2 and the base unit 4
The description is omitted because it is the same as the first embodiment.

Next, the operation of the third embodiment will be described. The CPU 11 of the CPU unit 1A usually has a ROM
A predetermined program is executed based on the OS stored in the OS 12. Here, when rewriting the OS by changing the function of the OS, upgrading the version, removing a bug, etc., the CP
The U unit 1A stops the operation of the PC by performing a specific operation, such as a switch input or any means such as a program, and writes a command to supply a download signal to the target unit to the control IC 13. As a result, the control IC 13 generates a download signal 43 for the target unit. The download signal 43 is supplied to the intelligent unit 2 to be rewritten by the OS via the base unit 4, whereby the gates 26a and 26b are opened and the data bus 2 inside the intelligent unit 2 is opened.
4 and an address bus 25 are connected to an address bus and a data bus inside the CPU unit 1A via an address bus 41 and a data bus 42 inside the base unit 4. On the other hand, the gate 28 is closed (high impedance), and the connection with the CPU 21 is cut off. Also,
In the selector 27, the control signal supplied from the CPU unit 1A via the base unit 4 becomes effective, and the F / R
The OM 22 is notified that the OS is to be written.

When the CPU 11 can access the address bus, the data bus, and the control signal with the intelligent unit 2 through the base unit 4, the CPU 12
The OS stored in the master 5 is supplied to the address bus 25 and the data bus 24 of the intelligent unit 2 through the internal buses of the address bus 41 and the data bus 42 of the base unit 4 based on the program in the master unit 5. Then, the data is written to the F / ROM 22.

When the OS writing to the F / ROM 22 is completed, the control signal supplied from the CPU unit 1A to the intelligent unit 2 disappears, and the target intelligent unit 2 shifts to the control based on the CPU 21. When the intelligent unit 2 is notified of the end of the OS writing, it is reset again by a service person, and the download signal 43 via the base unit 4 is output.
Supply stops. Therefore, on the intelligent unit 2 side, the gates 26a and 26b close and the gate 28 opens, so that predetermined data is connected to the two-port memory 23 based on the control of the CPU 21 via the address bus 25, and the normal operation is performed. Becomes possible. That is, the selector 3 selects C
The control signal output from the PU 21 is selected, the address bus and the data bus supplied from the base, and the control signal are not connected to the F / ROM 22, and the intelligent unit 2 executes the program based on the OS written in the F / ROM 22. Execute

In the third embodiment, the CPU unit 1A
, An input I / F for inputting a master 5 is provided.
Since the rewriting of the OS inputted from F can be controlled from the CPU unit 1A which controls the entire PC, the unit to be rewritten by the OS can be arbitrarily selected and the OS rewritten.
S can be rewritten. Further, as in the second embodiment, by supplying the download signal from the control IC 13 to a plurality of units to be written, it is needless to say that the OS can be simultaneously written to the plurality of units at a time. In addition, the RO
It is also free from the troublesome work of removing and writing M and the OS writing via the communication unit, and the OS writing via the internal bus of the base unit can shorten the working time and improve the workability.

[0034]

According to the programmable controller of the present invention, the OS can be written from the download unit or the master mounted on the CPU unit while the unit is connected to the bus line without replacing the ROM in which the OS is written. The workability of the OS writing is improved, and the processing can be performed at a high speed because of the OS writing via the bus line. Further, the download unit is connected only in the case of OS writing, and is not necessary during normal operation, and the size of the programmable controller device can be reduced. Further, writing can be performed collectively from the download unit or the CPU unit to a plurality of units to which the OS is to be written, thereby further improving work efficiency.

[Brief description of the drawings]

FIG. 1 is a configuration diagram showing a configuration of a PC according to a first embodiment.

FIG. 2 is a block diagram showing an internal configuration of an intelligent unit, a download unit, and a base unit.

FIG. 3 is a block diagram showing an internal configuration of an intelligent unit, a download unit, and a base unit according to a second embodiment.

FIG. 4 is a configuration diagram showing a configuration of a PC according to a third embodiment.

FIG. 5 is a block diagram showing an internal configuration of an intelligent unit, a download unit, and a base unit.

FIG. 6 is a diagram showing a method of writing an OS in a conventional PC.

FIG. 7 is a diagram showing a method of writing an OS to a conventional intelligent unit by serial communication.

FIG. 8 is an internal block diagram of the intelligent unit.

[Explanation of symbols]

1, 1A CPU unit, 2 intelligent unit, 3, 3A download unit, 4 base unit, 5 master, 24 data bus, 25 address bus, 26 gate, 27 selector, 28 gate,
41 address bus, 42 data bus, 43 download signal.

Claims (6)

[Claims] A CPU unit for controlling the entire apparatus;
In a programmable controller in which each unit having each function of an intelligent unit unit that realizes an additional function is connected via a bus line, a master storing an operating system of the unit is mounted on the programmable controller, and the unit is connected via the bus line. A programmable controller comprising a download unit for writing the operating system in a target operating system write target unit. 2. The writing of the operating system from the download unit by changing the connection between each unit and the bus line and directly connecting the download unit and the unit to which the operating system is to be written. 2. The programmable controller according to 1. 3. The programmable controller according to claim 2, wherein a connection between each unit and the bus line is changed by a download signal generated when the download unit is attached to the bus line. 4. A CPU unit for controlling the entire apparatus.
In a programmable controller in which each unit having each function of an intelligent unit unit for realizing an additional function is connected via a bus line, the CPU unit unit mounts a master in which an operating system of an operating system writing target unit is stored. A programmable controller comprising: an interface unit; and a writing unit that writes the operating system to the operating system writing target unit via the bus line. 5. A command for switching an internal bus to a unit to be written to an operating system,
5. The programmable controller according to claim 4, wherein a unit is connected to a ROM inside the operating system writing target unit. 6. The programmable controller according to claim 3, wherein a download signal is supplied to a plurality of units to which an operating system is to be written, and the operating system is written to the plurality of units collectively.