JPH11175334A - Program data protective circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a program data protective circuit capable of preventing program data stored in a memory cell from being recognized by an outsider. SOLUTION: This circuit is constituted of a word line decoder 1 for outputting word line signals by the input of address signals, a bit line decoder 2 for outputting bit line signals by the input, a program memory cell array 3 for reading the program data based on the word line signals from the word line decoder, a sense amplifier 40 for selectively outputting the program data from the program memory cell array based on the bit line signals from the bit line decoder, an address scramble part 60 for converting the output position of input address signals so as to be different from the time of a normal mode and outputting it to the word line decoder and the bit line decoder at the time of a protective mode and the scramble control part 50 of the output position conversion of the respective address signals inputted to the address scramble part based on protection enable signals.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a program data protection circuit for protecting program data stored in a semiconductor memory device. More specifically, the present invention relates to a program data protection circuit for storing program data stored in a memory cell. The present invention relates to a program data protection circuit that can prevent recognition by a program data protection circuit.

[0002]

2. Description of the Related Art In a conventional program data protection circuit, as shown in FIG.
, A bit line decoder 2, a sense amplifier 4,
A program memory cell array 3 storing so-called code data, which is program data, and an encryption memory cell array storing encryption data for encrypting each code data stored in a memory cell of the program memory cell array 3 5 is provided.

The sense amplifier 4 performs an exclusive NOR operation on code data stored in each memory cell of the program memory cell array 3 and encryption data stored in a memory cell of the encryption memory cell array 5. An exclusive NOR (ExNOR) gate was provided. Hereinafter, the operation of encrypting the code data stored in the program memory cell array 3 in the conventional program data protection circuit thus configured will be described with reference to FIG.

First, a read enable signal RE is
Drain decoder 1 and bit line decoder 2
When input, the word line decoder 1 has m bits
To decode the address signal of^mWord wrapper
An in signal is output to the program memory cell array 3.
Thereby, in the program memory cell array 3, 2 ^m
A word line of bits is selected. In addition, bit line
Decoder 2 decodes an n-bit address signal.
Do 2ⁿThe bit line signal of the bit is
Output to the array 5. As a result, the encryption memory cell
For ray 5, 2 ⁿThe bit line of the bit is selected.

After that, the code data and the encrypted data are
The exclusive-NOR is amplified by the sense amplifier 4 and amplified, and is put on the data bus. Here, a state in which the code data is not output to the outside via the data bus during the operation of the program data protection circuit is referred to as a “normal mode”, and a state in which the code data is output to the outside via the data bus is referred to as “protection mode”. "

In the "protection mode", that is, when the stored code data is output to the outside, the code data is encrypted and output in order to prevent the code data from being externally identified. The encryption process for encrypting the code data is performed according to the logic state of the encryption enable signal ENC input to the encryption memory cell array 5. As shown in FIG. 8, the encryption enable signal ENC is always at the low level in the normal mode, and is in the middle of the read enable signal RE being output as a pulse signal to the word line decoder 1 in the protection mode in the protection mode. Output to the memory cell array 5.

According to the output encryption enable signal ENC,
Output from the bit line decoder 2ⁿBit
Memory cell array based on the
The memory cell of (a) is selected, and the selected memory cell is selected.
Is output to the sense amplifier 4
You. On the other hand, 2 output from the word line decoder 1
^mThe program memory is based on the word line signal of bits.
A memory cell of the memory cell array 3 is selected, and the selected memory cell is selected.
The code data stored in the memory cell
4 is output. The selected cryptographic memory cell array 5
Of the encrypted data and program memory cell array 3
The data is sent to the exclusive NOR gate of the sense amplifier 4.
Is exclusive-NORed.

[0008] Such an encryption process is performed during one cycle of the read enable signal RE shown in FIG. 8, and is sequentially repeated, so that the code data stored in all the memory cells of the program memory cell array 3 is obtained. Is encrypted. The encrypted code data is output to the outside via a data bus. The original code data stored in the program memory cell array 3 can be restored by performing an exclusive NOR operation on the encrypted code data and the encrypted data again.

On the other hand, when the code data is not stored in all the memory cells of the program memory cell array 3, the data stored in the memory cells where the code data is not stored are all "1". The data stored in the memory cell where the code data is not stored, that is, the encrypted data obtained by exclusive-NORing “1” and the encrypted data was stored in the encrypted memory cell array 5. This is the same data as the encrypted data.

[0010] Here, when the encrypted data output to the outside is searched, the data stored in the memory cell in which the code data is not stored has a certain rule. This fixed rule is based on the fact that the encryption data stored in the encryption memory cell array 5 is repeatedly arranged. Therefore, when a certain rule can be found from the encrypted data output to the outside, the encrypted data used for encrypting the data can be recognized, and the recognized encrypted data is used. Thus, the code data stored in the program memory cell array 3 can be traced in reverse.

[0011]

As described above, in the conventional program data protection circuit, the code data stored in the program memory cell array 3 can be tracked and recognized based on the encrypted data. Therefore, there is an anxiety in protecting the stored code data, that is, the program data.

Therefore, an object of the present invention is to prevent externally recognizing code data stored in a program memory cell array when code data is not stored in all memory cells of the program memory cell array. A program data protection circuit is provided.

[0013]

In order to achieve the above object, a program data protection circuit according to the first aspect of the present invention comprises a word line decoder for outputting a word line signal in response to an input of an address signal; A bit line decoder for outputting a bit line signal in response to a signal input; a program memory cell array for storing program data and reading the program data based on a word line signal from the word line decoder; A sense amplifier that selects and outputs program data from the program memory cell array based on a bit line signal from a coder, and a program data protection circuit that protects the program data of the semiconductor memory device. , Each of the above An address scrambler for converting the output position of the dress signal to be different from the output position in the normal mode and outputting the converted signal to the word line decoder and the bit line decoder, and a protection input in the protection mode. A scramble control unit that controls conversion of an output position of each address signal input to the address scramble unit based on an enable signal;
It is comprised including.

According to a second aspect of the present invention, there is provided a program data protection circuit comprising: a word line decoder for outputting a word line signal when an address signal is input; and a bit line decoder for outputting a bit line signal when an address signal is input. A program memory cell array for storing program data and reading the program data based on an input word line signal, and selecting and outputting program data from the program memory cell array based on an input bit line signal. And a sense amplifier, wherein the program data protection circuit for protecting the program data of the semiconductor memory device comprises: a word line signal from the word line decoder and a bit line from the bit line decoder in a protection mode. The output position of the signal is converted so as to be different from the output position in the normal mode, based on an address scramble section for outputting to the program memory cell array and the sense amplifier, and a protection enable signal inputted in the protection mode. A scramble control unit for controlling the conversion of the output position of the word line signal and the bit line signal input to the address scramble unit.

According to the third aspect of the present invention, the scramble control section includes a first AND gate for performing an AND operation on the protection enable signal and a read enable signal of the word line decoder and the bit line decoder. An inverter for inverting a logic state of the protection enable signal; and a second AND gate for performing an AND operation on an output of the inverter and the read enable signal, and an output signal from the first AND gate and the second AND gate. An output signal from the 2AND gate is input to the address scramble unit.

In the invention described in claim 4, the address scramble unit is a second AN of the scramble control unit.
A plurality of first switches that pass or block an input signal according to an output signal of the D gate; and a plurality of first switches that pass or block an input signal according to an output signal of a first AND gate of the scramble control unit. A plurality of second switches corresponding to one switch, wherein each of the first switch and the second switch corresponding to the first switch has one end connected to a common input terminal and the other end connected to a different output terminal. In the protection mode, the input signal is output to one output terminal through the second switch, and in the normal mode, the input signal is output through the first switch. Output to the other output terminal.

In the invention described in claim 5, the second AN
The output signal from the D gate is output in synchronization with the read enable signal in the normal mode, and the first A
The output signal from the ND gate is output in synchronization with the read enable signal in the protection mode.

[0018]

Embodiments of the present invention will be described below with reference to the drawings. First embodiment of the program data protection circuit according to the present invention, as shown in FIG. 1, when the protected mode, the address signal A ₀ to A _m to be input, B ₀
To the output positions of _Bn , _respectively , so as to be different from the output positions in the normal mode, and output to the word line decoder 1 and the bit line decoder 2, and the address scrambler 60, which is input in the protection mode. Each of the address signals A ₀ -A _m , B ₀ input to the address scramble unit 60 based on the protection enable signal PRO
A scramble control unit 50 for controlling the conversion of the output position of .about.B _n, the word line decoder 1 outputs a word line signal by the input of the address signal A ₀ '~A _m' from the address scramble unit 60, the A bit line decoder 2 for outputting a bit line signal in response to the input of address signals B ₀ ′ to B _n ′ from the address scrambler 60; a semiconductor memory device for storing program data; A program memory cell array 3 from which the program data is read based on a word line signal from
A sense amplifier 4 for selecting and outputting program data from the program memory cell array 3 based on a bit line signal from the bit line decoder 2;
It is provided with.

The scramble control unit 50
As shown in FIG. 2, a first AND operation for performing an AND operation on the protection enable signal PRO and the read enable signal RE is performed.
A gate AND1, an inverter INV for inverting the logical state of the protection enable signal PRO, and an inverter INV
And a second AND gate AND2 that performs a logical AND operation on the output of V and the read enable signal RE. An output signal B from the first AND gate AND1 and an output signal A from the second AND gate AND2 are
The address is input to the address scramble unit 60.

The address scrambler 60
Is the scramble control unit 50 as shown in FIG.
The output signal A of the second AND gate AND2 of
Input address signal A₀~ A_m, B₀~ B_nPass through
Is a switch S which is a plurality of first switches to be cut off_1A0~
S_1Am, S_1B0~ S_1BnAnd the scramble control unit
According to the output signal B of the first AND gate AND1, the input signal
Address signal A₀~ A_m, B₀~ B_nThrough or
Switch S as a plurality of second switches to be cut off_{2A 0}~ S
_2Am, S_2B0~ S_2BnAnd a switch S_1A0~ S
_1Am, S_1B0~ S _1BnAnd the switch S_1A0~ S_1Am,
S_1B0~ S_1BnSwitch S corresponding to_2A0~ S_2Am, S
_2B0~ S_2BnConnect one end to a common input and
The terminals are connected to different output terminals.
Input address signal A₀~ A_m, B₀~ B_nHa sui
Switch S_2A0~ S_2Am, S_2B0~ S_2BnOne out through
Output to the input end, and in normal mode,
Signal A₀~ A_m, B₀~ B _nIs the switch S_1A0~ S
_1Am, S_1B0~ S_1BnOutput to the other output terminal
You.

Hereinafter, the operation of the first embodiment configured as described above will be described. First, the read enable signal RE is input to the word line decoder 1 and the bit line decoder 2, and the read enable signal RE and the protection enable signal P are sent to the scramble control unit 50.
RO inputs. As shown in FIG. 4, the protection enable signal PRO is at a low level in a normal mode in which program data stored in the memory cells of the program memory cell array 3, that is, code data is not output to the outside via a data bus. It is at the high level in the protection mode in which data is output to the outside.

The operation in the normal mode will be described below. Protection enable signal PRO and read enable signal RE
Is the first AN in the scramble control unit 50 shown in FIG.
AND operation is performed by the D gate AND1. Here, as shown in FIG. 4, since the protection enable signal PRO is at a low level, the output signal B of the first AND gate AND1 is always at a low level. Output signal B is outputted to the address scramble unit 60, a plurality of switches S of the address scramble unit 60 _2A0 to S _2Am, S _2B0 to S
_2Bn by being open, the address signal A ₀ to A _m to be input, B ₀ .about.B _n is blocked.

On the other hand, an output signal A obtained by performing an AND operation of the protection enable signal PRO and the read enable signal RE inverted by the inverter INV of FIG. 2 by the second AND gate AND2 is synchronized with the read enable signal RE. Output. That is, when the read enable signal RE is at a high level, the output signal A also becomes at a high level. The output signal A is outputted to the address scramble unit 60, a plurality of switches S _1A0 to S _1AM address scramble unit 60, S _1B0 ~S _1Bn by being short-circuited, the address signal A ₀ to A _m input ,
B ₀ .about.B _n is passed.

The plurality of switches S described above_1A0~ S_1Am, S
_1B0~ S_1Bn, S_2A0~ S_2Am, S _2B0~ S_2BnSwitching
Due to the operation, the input to the address scrambler 60 is performed.
Address signal A₀~ A_m, B₀~ B_nIs the address
The position of the output end changes when output from the rumble unit 60
Instead, the address signal A₀'~ A_m’, B₀’~
B _n′, And the word line decoder 1 and
The data is input to the bit line decoder 2. That is,
Address signal A₀~ A_m, B₀~ B_nAnd correspondingly
Output address signal A₀'~ A_m’, B₀’~
B_n'Are signals indicating the same address.

Then, in the word line decoder 1,
Input address signal A₀'~ A _m’Is decoded
2^mThe bit word line signal is
Output to the recell array 3. In addition, bit line
In the coder 2, the input address signal B₀’-B_n’
Is decoded and 2ⁿBit line signal of bit
Output to the sense amplifier 4.

In the program memory cell array 3, data is read from the memory cells based on the input word line signal and output to the sense amplifier 4. In the sense amplifier 4, the data from the program memory cell array 3 is selected and amplified based on the bit line signal from the bit line decoder 2, and then sent to the data bus.

Next, in the protection mode, that is, when the stored data
The operation when data is output to the outside will be described. First,
A high level protection enable signal PRO is
Is inverted by the inverter INV of the
Argument with read enable signal RE by ND gate AND2
The output signal A obtained by the logical operation is always
The address scramble part of FIG.
60 switches S_1A0~ S _1Am, S_1B0~ S_1Bn
Is released and the input address signal A₀~ A_m, B₀
~ B_nIs shut off.

On the other hand, the first AN of the scramble control unit 50
The output signal B from the D gate AND1 is synchronized with the read enable signal RE. That is, when the read enable signal RE is at a high level, the output signal B is also at a high level, and the address scramble unit 60
A plurality of switches _{S 2A0 ~S 2Am, S 2B0 ~S} 2Bn is shorted, the address signal A ₀ to A _m to be input, B ₀ .about.B
_n is passed.

The plurality of switches S described above_1A0~ S_1Am, S
_1B0~ S_1Bn, S_2A0~ S_2Am, S _2B0~ S_2BnSwitching
By the operation, the input address signal A₀~ A_m, B₀
~ B _nChanges the output position so that it differs from the input position.
Address signal A ₀'~ A_m’, B₀’-B
_n', And the word line decoder 1 and the video
Input to the input line decoder 2.

For example, the address signal _Am is applied to the switch S
The output position from the address scrambler 60 is changed by _2Am, and is input to the word line decoder ₁ as an address signal _Am-1 '. The address signal A
_m-1, the output position of the address scramble unit 60 by the switch S _2Am-1 is changed, the address signal A _m '
Is input to the word line decoder 1. Similarly, the other address signals A ₀ -A _m-2 and B ₀ -B _n are output from the word lines while the output positions are changed by the switches S _{2A0 -S 2Am-2} and S _{2B0 -S 2Bn.} The data is input to the decoder 1.

Thereafter, the word processing is performed in the same manner as in the normal mode.
In the decoder 1, the input address signal A
₀'~ A_m’Is decoded to 2^mWord of bits
A line signal is output to program memory cell array 3.
You. In the program memory cell array 3, the input
Data is read from the memory cell based on the data line signal.
Output to the sense amplifier 4. Where the output
Address signal A whose location has been changed₀'~ A_m'On the basis of
Memory of the selected program memory cell array 3
The output position of the cell is not changed in normal mode
Address signal A ₀'~ A_m’Note selected
Different from resell.

On the other hand, in the bit line decoder 2, the input address signals B ₀ ′ to B _n ′ are decoded, and a bit line signal of 2 ⁿ bits is output to the sense amplifier 4. In the sense amplifier 4, program data from the program memory cell array 3 is selected and amplified based on a bit line signal from the bit line decoder 2. Here, program data is selected based on the address signal B ₀ '~B _n' the output position is changed, in the normal mode, the address signal B ₀ '~B _n' the output position is not changed It is different from the program data selected based on this.

Thereafter, the program data selected by the sense amplifier 4 is output to the outside via the data bus. As described above, when the program data stored in the program memory cell array 3 is read in the protection mode, first, the output position is changed so that the order is different from the order in which the program memory cell array 3 is written. The program data stored in the program memory cell array 3 is read according to the word line signal. Then, the read program data is selected and output by the sense amplifier 4 based on the bit line signal whose output position has been changed. Thus, it is possible to prevent the original stored program data from being recognized using the data output to the outside.

Next, the second embodiment will be described with reference to the drawings. Data protection circuit for a semiconductor device of the second embodiment, as shown in FIG. 5, an address signal A ₀ to A _m of m bits input to de-code and outputs a word line signal of 2 ^m bits A word line decoder 1; a bit line decoder 2 for decoding an input n-bit address signal B _{0 to} B _m to output a 2 ^n- bit bit line signal; The output position of the word line signal from the coder 1 and the output position of the bit line signal from the bit line decoder 2 are respectively converted so as to be different from the output position in the normal mode, and are converted to the program memory cell array 3 and the sense amplifier 4. Output address scramble section 600
A scramble control unit 50 for controlling conversion of output positions of word line signals and bit line signals input to the address scramble unit 600 based on a protection enable signal input in a protection mode, and a semiconductor memory device. A program memory cell array 3 configured to store program data and read out the program data based on a word line signal from the address scrambler 600; and to store the program data based on a bit line signal from the address scrambler 600. And a sense amplifier 4 for selecting and outputting the program data from the memory cell array 3.

The scramble control unit 50 is shown in FIG.
The configuration is the same as that of the scramble control unit 50. Soshi
The address scrambler 600 is shown in FIG.
As described above, the second AND gate of the scramble control unit 50
The word line signal is output by the output signal A of the gate AND2.
Signal and a plurality of signals for passing or blocking the bit line signal.
Switch S which is the first switch_W1, 2⁰~ S_W1, 2^m,
S_V1, 2⁰~ S_V1, 2ⁿAnd the scramble control unit 50
According to the output signal B of the first AND gate AND1, the signal
Pass or block the data line signal and the bit line signal.
Switches S as a plurality of second switches to be turned off_W2, 2⁰~ S
_W2, 2^m, S_V2, 2⁰~ S_V2, 2ⁿAnd a switch
S_W1, 2 ⁰~ S_W1, 2^m, S_V1, 2⁰~ S_V1, 2ⁿAnd the switch
Chi S_W1, 2⁰~ S_W1, 2^m, S_V1, 2 ⁰~ S_V1, 2ⁿCorresponding to
Switch S_W2, 2⁰~ S_W2, 2^m, S_V2, 2⁰~ S_V2, 2ⁿIs
Each end is connected to a common input, and each other is connected to a different output
To the input word in the protection mode.
The line signal and the bit line signal are supplied to the switch S_W2, 2⁰~
S_W2, 2^m, S_V2, 2⁰~ S_V2, 2ⁿTo one output end via
The word line that is output and input in normal mode
The signal and the bit line signal are switched S_W1, 2⁰~ S_W1, 2
^m, S_V1, 2⁰~ S_V1, 2ⁿOutput to the other output terminal via
Is done.

That is, in the address scrambler 600 of the second embodiment, a plurality of switches S based on the protection enable signal PRO from the scramble controller 50 are provided in the same manner as the address scrambler 60 of the first embodiment. ^{_{W1, 2 0 ~S W1, 2}} m, S V1, 2 0 ~S V1, 2 n and S _W2, 2
⁰ to S _W2, 2 ^m, the ^{_{S V2, 2 0 ~S V2,}} 2 n and switching control, converts the output position of the word line signal and a bit line signal.

[0037] However, the address scrambler 60 of the first embodiment, the address signal _{A 0 ~A m, B 0 ~B} n
In the address scrambler 600 of the second embodiment, the output positions of the 2 ^m- bit word line signal and the 2 ^n- bit bit line signal are changed. The operations of the program memory cell array 3 and the sense amplifier 4 by the word line signal and the bit line signal output from the address scramble unit 600 are the same as the operation of the program data protection circuit of the first embodiment.

The number of switches of the address scrambling unit 60 of the first embodiment of the present invention is twice the number of address signals, and the number of switches of the address scrambling unit 600 of the second embodiment of the present invention is the number of word line signals. And twice the number of bit line signals.

[0039]

As described above, in the program data protection circuit according to the present invention, when the stored code data is output to the outside, the stored program data is stored in a memory cell different from the original memory cell of the program memory cell array. Since the code data is read, that is, read in a different order from the order in which the code data was written, there is an effect that it is possible to prevent the original code data from being recognized using the data output to the outside. .

The read operation of the program data has conventionally been based on the encryption enable signal output during one cycle of the read enable signal. However, in the present invention, the read operation is performed by the output signal synchronized with the read enable signal. . Therefore, unlike the related art, it is not necessary to set one period of the read enable signal as a period in which the encryption enable signal can be generated.
The period between cycles can be shorter than before. Thus, there is an effect that the read operation speed of the program data can be further increased.

Further, since a conventional sense amplifier having an exclusive NOR gate is unnecessary, the structure can be simplified.

[Brief description of the drawings]

FIG. 1 shows a first example of a program data protection circuit according to the present invention.
It is a schematic structure figure of an embodiment.

FIG. 2 is a configuration diagram of a scramble control unit of FIG. 1;

FIG. 3 is a configuration diagram of an address scramble unit of FIG. 1;

FIG. 4 is a waveform diagram of each signal in a scramble control unit of FIG. 2;

FIG. 5 shows a second example of the program data protection circuit according to the present invention.
It is a schematic structure figure of an embodiment.

FIG. 6 is a configuration diagram of an address scramble unit of FIG. 5;

FIG. 7 is a schematic configuration diagram of a conventional program data protection circuit.

FIG. 8 is a waveform diagram of the read enable signal RE and the encryption enable signal ENC of FIG. 7;

[Explanation of symbols]

 Reference Signs List 1 word line decoder 2 bit line decoder 3 program memory cell array 40 sense amplifier 50 scramble control unit 60,600 address scramble unit

Claims (5)

[Claims] 1. A word line decoder for outputting a word line signal in response to an input of an address signal, a bit line decoder for outputting a bit line signal in response to an input of an address signal, and the word line decoder storing program data. A program memory cell array from which the program data is read based on a word line signal from the memory, a sense amplifier that selects and outputs program data from the program memory cell array based on a bit line signal from the bit line decoder, A program data protection circuit for protecting the program data of the semiconductor memory device, wherein in the protection mode, the output position of each address signal is converted so as to be different from the output position in the normal mode, and line An address scrambler for outputting to the decoder and the bit line decoder; and controlling a conversion of an output position of each of the address signals input to the address scrambler based on a protection enable signal input in the protection mode. And a scramble control unit. 2. A word line decoder for outputting a word line signal in response to an input of an address signal, a bit line decoder for outputting a bit line signal in response to an input of an address signal, and a word line for storing and inputting program data A semiconductor memory device comprising: a program memory cell array from which the program data is read based on a signal; and a sense amplifier that selects and outputs program data from the program memory cell array based on an input bit line signal. In a program data protection circuit for protecting the program data, in a protection mode, an output position of a word line signal from the word line decoder and a bit line signal from the bit line decoder are different from an output position in a normal mode. And an address scrambler that converts each to the program memory cell array and the sense amplifier, and a word line signal input to the address scrambler based on a protection enable signal input in the protection mode. A program data protection circuit, comprising: a scramble control unit that controls conversion of an output position of a bit line signal. 3. A first AND gate for performing an AND operation on the protection enable signal and a read enable signal of the word line decoder and the bit line decoder, and a logic state of the protection enable signal. And a second AND gate for performing an AND operation on the output of the inverter and the read enable signal. The output signal from the first AND gate and the second AN
3. The output signal from the D gate is input to the address scramble unit.
4. The program data protection circuit according to 1. 4. An address scrambler comprising: a plurality of first switches for passing or blocking an input signal according to an output signal of a second AND gate of the scramble controller; and an output of a first AND gate of the scramble controller. A plurality of second switches corresponding to the plurality of first switches, which pass or block an input signal by a signal, wherein the first switch and the second switch corresponding to the first switch are: One end is connected to a common input terminal, and the other end is connected to a different output terminal. In the protection mode, the input signal is the second signal.
The signal is output to one output terminal via a switch. In the normal mode, the input signal is the first signal.
4. The program data protection circuit according to claim 1, wherein the program data is output to the other output terminal via a switch. 5. The output signal from the second AND gate is:
The output signal from the first AND gate is output in synchronization with the read enable signal in a protection mode in a normal mode. Item 5. The program data protection circuit according to any one of Items 4.