JPH11174132A - Device and method for detecting test mode - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a detection device for avoiding an erroneous operation where an integrated circuit enters a test mode by mistake. SOLUTION: A detection device 101 that is applied to an integrated circuit 10, and is provided corresponding to a test device 11 for generating a first rearrangement signal, is provided with a signal rearrangement circuit 1011 that has a specific signal input terminal and rearranges the specific signal and outputs a second rearrangement signal when the specific signal is inputted; and a discrimination circuit 1012 for discriminating whether the integrated circuit 10 enters a test mode or not by entering the first and the second rearrangement signals.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a detection apparatus and method, and more particularly to a test mode detection apparatus and method.

[0002]

2. Description of the Related Art Hitherto, quality of integrated circuits in mass production processes has been usually determined by mass production tests. Therefore, in order to improve the accuracy and test speed of the data measured during the program of the mass production test, some test lines are provided in the integrated circuit so that the mass production quality is confirmed at the time of the mass production test.

When the integrated circuit is in the normal operation mode, the circuit designer mistakenly enters the test mode, and in order to prevent the normal operation of the actual circuit from being affected by the test line, the integrated circuit is integrated by the circuit designer. Various methods are employed to identify whether a circuit is in a normal operating mode or a test mode, such that the test circuit is capable of performing normal production testing on the integrated circuit. The operation was not affected. However, the conventional method for distinguishing between the normal operation mode and the test mode has disadvantages, and a more stable and reliable apparatus and method for distinguishing between the normal operation mode and the test mode are demanded.

In the conventional test mode detection method which has been most often performed in the conventional method, the normal operation mode and the test mode are switched by increasing one or more test pins. The specific test mode in the mode mode is divided. For example, the test pin is normally fixed to a high level (/ low level) state, but once the test pin is forcibly switched to a low level (/ high level) state from the outside, even if the integrated circuit is in a normal operation mode. The integrated circuit derives internal signals via the test line even when the test mode is switched to the test mode, and allows external control of these internal signals directly. That is, an external tester uses these characteristics to measure these internal signals and input control signals inside the integrated circuit.

[0005]

As described above, the advantage of the conventional method is that the normal operation mode and the test mode are clearly separated from each other, so that the normal operation mode is erroneously set in the test mode. Never enter. However, on the other hand, a large number of test pins for switching must be designed, which always causes trouble in a small-pack integrated circuit. This is because the test pins on the small-package integrated circuit have their own uses, and it is not easy to draw out a specific test pin from among them and use them for testing. Furthermore, since the user enters the test mode and derives internal information only by applying a fixed-level signal to a specific pin for test by the user, the confidentiality of the circuit cannot be sufficiently protected.

Further, in order to eliminate the drawback that it is necessary to provide a large number of test pins, a special combination of serial (or parallel) signals is inputted from a certain pin, and the integrated circuit is operated in a normal operation mode or a test mode. It is possible to distinguish the operations that enter. The advantage of these methods is that the normal operation mode or the test mode can be distinguished without increasing the number of test pins, but on the other hand, the generation of some kind of special combination of serial (or parallel) signals, This signal must not be generated when the circuit is in normal operation mode. Otherwise, the integrated circuit which is originally in the normal operation state is erroneously switched to the test mode because the normal operation signal is the same as the signal of these special combinations, and conversely causes a malfunction. In other words, due to the wide variety of normal operation signals of integrated circuits,
It is not easy to ensure that these special combination signals are not the same. Therefore, the conventional method of inputting a special combination signal from a certain pin is not very reliable.

[0007] In addition, a method has been adopted for identifying whether an integrated circuit is in a normal operation mode state or a test mode state based on whether or not a detection oscillator is oscillating. As with the method of inputting a special combination signal from a certain specific pin, it is not possible to avoid a malfunction that enters the test mode by mistake.

SUMMARY OF THE INVENTION It is a primary object of the present invention to provide a detection apparatus and method for preventing a malfunction in which an integrated circuit enters a test mode by mistake.

It is another object of the present invention to provide a detection apparatus and method capable of highly protecting secrets.

Another object of the present invention is to provide a test mode detecting apparatus and method for measuring an integrated circuit without increasing the number of test pins.

[0011]

According to the present invention, there is provided a test mode detecting apparatus which is applied to an integrated circuit and is provided corresponding to a test apparatus for generating a first recombination signal. A signal recombination circuit having a specific signal input terminal, receiving a specific signal and recombining the specific signal to output a second recombined signal; A determination circuit for determining whether or not the integrated circuit has entered the test mode when a second recombination signal is input.

Preferably, the integrated circuit is further electrically connected to the signal recombination circuit and the discrimination circuit,
A start signal input terminal for inputting a start signal is provided.

Preferably, the start signal input terminal is a reset signal input terminal, and the start signal is a reset signal.

[0014] Preferably, both the signal recombination circuit and the discrimination circuit can be used according to a start signal (enabl
e) A usable operation occurs when the state is changed to a state, and an operation for setting the signal recombination circuit and the determination circuit to a usable state is stopped when the activation signal is disabled. It is configured as follows.

The usable state may be a high level state. Further, the usable state may be a low level state.

[0016] Preferably, the test device is an integrated circuit tester for measuring internal characteristics and quality of the integrated circuit.

Preferably, the test apparatus has another specific signal input terminal, and another specific signal is input from the specific signal input terminal, and the first specific signal is recombined with the first specific signal. Another signal recombination circuit for generating the output of the recombination signal is provided.

Preferably, the other signal recombination circuit further includes another delay code circuit for dividing and recombining all or some of the other specified signals to obtain the first recombined signal. ing.

Preferably, the other signal recombination circuit comprises:
A first flip-flop that receives the other specific signal and uses the other specific signal as a time pulse signal; and a first flip-flop that is electrically connected to the first flip-flop. A second flip-flop that uses the output signal as its time pulse signal, and is electrically connected to the second flip-flop;
And a third flip-flop that uses an output signal of the second flip-flop as its time pulse signal.

Preferably, the first, second and third flip-flops are all T-type flip-flops, and the output signals of these flip-flops are used as the first recombination signal.

[0021] The first recombination signal may be a serial recombination signal. Further, the first recombination signal may be a parallel recombination signal.

Preferably, the signal recombination circuit further comprises:
A delay code circuit is provided for dividing and recombining all or a part of the specific signal to obtain the second recombined signal.

Preferably, the signal recombination circuit receives the specific signal and uses the specific signal as a time pulse signal of the fourth flip-flop, and electrically connects the fourth flip-flop to the fourth flip-flop. Connected
A fifth flip-flop using the output signal of the fourth flip-flop as its time pulse signal, and an output signal of the fifth flip-flop electrically connected to the fifth flip-flop. A sixth flip-flop used as a signal, and the output signals of the fourth, fifth and sixth flip-flops are used as the second recombination signal.

Preferably, the fourth, fifth and sixth flip-flops are all T-type flip-flops.

[0025] The second recombined signal may be a serial recombined signal. Further, the second recombination signal may be a parallel recombination signal.

Preferably, said discriminating circuit is a comparator.

Preferably, the discriminating circuit compares the first and second recombination signals and generates a test mode signal when they are the same, and drives a test line provided inside the integrated circuit to drive the test line. To enter the test mode,
Otherwise, the integrated circuit will still maintain the normal operating mode state.

Preferably, the test mode detecting device is provided inside the integrated circuit.

Preferably, the test mode detecting device further generates the other specific signal and the specific signal so that the other signal recombination circuit and the signal recombination circuit respectively have the first and second signal recombination circuits. And a signal generation circuit for generating a recombination signal of

Preferably, said signal generating circuit is a signal generator for generating a source signal output, a state generator electrically connected to said signal generator for converting said source signal to a state signal output, A signal encoder electrically connected to the generator and encoding the status signal to generate the another specific signal or the specific signal output.

[0031] The other specific signal or the specific signal may be a serial specific signal. Further, the other specific signal or the specific signal may be a parallel specific signal.

Preferably, the signal generation circuit is electrically connected to the start signal input terminal, and when the start signal becomes available in response to the start signal, a usable operation occurs, and the start signal is used. When the prohibition state is set, the operation for making the signal generation circuit usable is stopped.

Preferably, the another specific signal and the specific signal are the same specific signal.

Preferably, the signal generation circuit is provided inside the integrated circuit, and the test mode detection device further includes a normal operation signal of the specific signal and the integrated circuit for outputting an output pin of the integrated circuit. A multiplex device is provided to enable sharing.

Preferably, the multiplex device comprises:
The multiplexer is a two-to-one multiplexer, and a selection signal terminal of the multiplexer has a multiplex enable input from the signal generation circuit such that the operation mode of the integrated circuit corresponds to a test mode or a normal operation mode. The specific signal or the normal operation signal is output to the output pin according to the selection signal.

Preferably, the normal operation signal is a system oscillation output signal of a system oscillator in the integrated circuit,
The output pin is an output pin of the system oscillator.

The present invention also relates to a method for detecting a test mode, and more particularly to a method for detecting a test mode applied to an integrated circuit provided corresponding to a test apparatus for generating a first recombined signal. a) inputting a specific signal, causing the integrated circuit to perform division and recombination in accordance with the specific signal, and to generate a second recombination signal; and (b) the first recombination signal. Inputting a signal to the integrated circuit; and (c) determining whether the integrated circuit is in the test mode by performing an operation of determining the first and second recombined signals. Is provided.

Preferably, before step (a),
(D) providing a start signal to the integrated circuit.

Preferably, the steps (a) to (c) are performed only when the activation signal is in a usable state, and the steps (a) to (c) are advanced when the activation signal is in an inhibited state. To stop.

The usable state can be a high level state. Further, the usable state may be a low level state.

Preferably, the start signal is a reset signal.

Preferably, the test device is an integrated circuit tester for measuring internal characteristics and quality of the integrated circuit.

Preferably, the test apparatus performs division and recombination in order to receive another specific signal and generate and output the first recombination signal.

[0044] The first recombination signal may be a serial recombination signal. Further, the first recombination signal may be a parallel recombination signal.

[0045] The second recombination signal in the step (a) can be a serial recombination signal. Further, the second recombination signal in the step (a) may be a parallel recombination signal.

Preferably, in the step (c), if the first recombined signal and the second recombined signal are discriminated and compared to be the same, a test mode signal is generated and provided in the integrated circuit. The test circuit is driven to enter the test mode, or the integrated circuit is still maintained in the normal operation mode.

The other specific signal or the specific signal may be a serial specific signal. Further, the other specific signal or the specific signal may be a parallel column type specific signal.

Preferably, the another specific signal and the specific signal are the same specific signal.

Preferably, after step (a),
(E) switching the integrated circuit from a position where a normal operation signal is output to an output of the specific signal according to the start signal and the multiplex enable selection signal; and (f) converting the specific signal to the specific signal. Generating said first recombination signal by inputting to said test device.

According to the test mode detecting apparatus and the detecting method of the present invention, it is possible to avoid a malfunction in which the integrated circuit enters the test mode by mistake, to protect the secret highly, and to increase the number of test pins. Since the integrated circuit is measured without the need, the waste of cost due to the large number of pins, low security and low reliability in the conventional integrated circuit can be significantly and effectively improved.

[0051]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of a test mode test apparatus and a test method according to the present invention will be described below with reference to the accompanying drawings.

FIG. 1 is a block diagram of a test mode detecting apparatus according to a first preferred embodiment of the present invention. In FIG. 1, reference numeral 10 denotes an integrated circuit, which includes a test mode detection device 101 and a test line 102. The test mode detecting apparatus 101 includes a signal recombination circuit 1011 having a specific signal input terminal P11 and a discriminating circuit 1012, and the discriminating circuit 1012 uses, for example, a comparator. The integrated circuit 10 further includes a start signal input terminal P12 for inputting a start signal S15. The start signal input terminal P12 is a reset signal input terminal, and the start signal S15 is a reset signal. In the figure, reference numeral 11 denotes a test device, which is another specific signal input terminal P1.
3 is provided. The test apparatus 11 is a tester that measures internal characteristics and quality of the integrated circuit 10. Hereinafter, the operation principle shown in FIG. 1 will be described.

First, in order to prevent the integrated circuit 10 from arbitrarily entering the test mode, the test mode detecting device 1 is required after the start signal S15 is surely enabled.
01 is designed to be driven and it is determined whether or not it is in the test mode. In other words, since both the signal recombination circuit 1011 and the discrimination circuit 1012 are electrically connected to the activation signal input terminal P12, the signal recombination circuit 1011 and the discrimination circuit 1012 are in a state where the activation signal S15 can be used. A usable state occurs accordingly. Of course, when the activation signal S15 is in the disable state (disable), the signal recombination circuit 1011 and the determination circuit 1012
Can be stopped so that the integrated circuit 10 does not arbitrarily enter the test mode and malfunction does not occur.

When the specific signal S11 is input from the specific signal input terminal P11 and a usable operation occurs in accordance with the usable state of the activation signal S15, the signal recombination circuit 1011 sets the specific signal S11. Perform the replacement operation,
Alternatively, a part (or all) of the specific signal S11 is converted into a second recombined signal S12 and output to the discrimination circuit 1012. On the other hand, another signal recombination circuit 111 receives another specific signal S13 from another specific signal input terminal P13, generates a first recombined signal S14, and outputs it to the discrimination circuit 1012. Then, in the determination circuit 1012, the activation signal S1
5, an enable signal is generated according to the enable state of
When the recombined signal S14 and the second recombined signal S12 are the same, the test mode signal S16 is generated and output, and the test line 102 provided inside the integrated circuit 10 is driven. Enter during test mode. Otherwise, if the signal is different or the activation signal S15 returns to the disabled state, the integrated circuit 10 maintains the normal operation mode and achieves the original integrated circuit function of the integrated circuit 10.

The discrimination circuit 1012 includes a serial (or parallel) first recombined signal S14 and a second recombined signal S1.
2 can be discriminated and compared, and the first recombinant signal S1
One or a plurality of bit signals in the fourth and second recombination signals S12 can be selectively compared.

Regardless of the signal recombination circuit 1011 or the other signal recombination circuit 111, the purpose is to reinforce the security protection function of the integrated circuit 10. Only when the same signal recombination circuit as that of the detection device 101 is employed, the same comparison signal can be output. The complementary concept is adopted as another method of increasing the degree of secret protection. The signal recombination circuit 1011 and the other signal recombination circuit 111 are designed as complementary circuits, and the specific signal S11 and the other specific signal S13 are combined. Is a complementary signal, after processing another specific signal S13 and another specific signal S11 via the other signal recombination circuit 111 and the signal recombination circuit 1011 respectively, and then the first recombined signal S14 and the A second recombination signal S12 is obtained, which allows the test mode detector to detect the test mode signal 1 at the correct timing.
Then, the test line 102 is driven to enter the test mode.

Further, once the integrated circuit 10 changes, the test mode detecting device 10 provided inside the integrated circuit 10
In 1, the signal recombination circuit 1011 therein is also changed or adjusted, and as a result, the other signal recombination circuits 111 inside the test apparatus also need to perform corresponding changes or adjustments. Although the task of changing or adjusting these other signal recombination circuits 111 is extremely easy for the designer, it can be understood by the imitator after executing various complicated programs, for example, the reduction process program. Things. Thus, more reliable compensation for the protection of the integrated circuit can be provided.

Further, as for the other signal recombination circuits 111 and 1011, the other specific signals S 13 and S 11 are directly transmitted to the discriminating circuit 1012 by a simple method, or complicated signals are transmitted. Some bit signals are arbitrarily decomposed, delayed, coded after the design, and then transmitted to the discriminating circuit 1012. Others
Other signal recombination circuits 111 and 1011
Are other specific signals S13 in series (or parallel), respectively.
And the specific signal S11, and can output the first (second) recombined signal S14 and the second recombined signal S12 of a serial (or parallel) type, respectively.

The other internal circuits of the signal recombination circuit 111 and the signal recombination circuit 1011 are illustrated in FIGS. 2 and 3 as examples in which a serial signal is converted into a parallel signal. In FIG. 2, another signal recombination circuit 111 receives another specific signal S13 and is electrically connected to a first flip-flop FF1 used as a time pulse signal and the first flip-flop FF1. A second flip-flop FF2 using the output signal Q0 of the flip-flop FF1 as a time pulse signal, and an output signal Q1 of the second flip-flop FF2 electrically connected to the second flip-flop FF2. Third flip-flop F used as time pulse signal Q1
F3, and the output signal of the third flip-flop FF3 is Q2. The signal (Q0, Q1, Q2) obtained by recombining the other specific signal S13 in this way is output as the first recombined signal S14, and is input via the input pin of the regular signal inherently provided in the integrated circuit 10. Thus, the first recombined signal S14 can be input to the integrated circuit 10 very easily. Further, the first, second and third flip-flops F
The available operations of F1, FF2, and FF3 are all controlled by a flip-flop enable signal SE, which is sent from inside the test apparatus 11.

Similarly, the signal recombination circuit 1 shown in FIG.
011 is provided with flip-flops (fourth, fifth, and sixth flip-flops FF4, FF5, FF6) having the same function as the other signal recombination circuits shown in FIG. The signal (Q
3, Q4, Q5) are output as the second recombination signal S12. Here, the usable operations of the fourth, fifth and sixth flip-flops FF4, FF5 and FF6 are all controlled by the start signal S15.

Each of the first to sixth flip-flops shown in FIGS. 2 and 3 is a T-type flip-flop. Each of the T-type flip-flops has a signal input terminal T,
It has a time pulse input terminal CK, a signal input terminal Q, and a flip-flop usable end E.

For example, when the specific signal S11 is a serial signal (11001010) shown in FIG. 4, the flip-flops FF4 to FF6 are used as the second recombined signal S12.
The waveforms of the output signals of (Q3, Q4, Q
In the case of the parallel signal shown in 5), it is possible to provide a test function for an integrated circuit with higher security than the conventional technology.

Therefore, the specific signal S shown in FIG.
Since only one test pin is required to input "11", it is possible to prevent the integrated circuit from erroneously entering the test mode without increasing the number of pins of the conventional integrated circuit, and to further protect the secret. It is possible to provide a test mode detection device with high reliability and reliability.

FIG. 5 is a diagram showing another preferred embodiment of the test mode detecting apparatus according to the present invention. The test device 21, the test line 202, and the specific signal input terminal P in FIG.
Signal recombination circuit 2011 having 21 and discrimination circuit 201
2. Start signal input terminal P22, other specific signal input terminal P23
The functions of the signal recombination circuit 211 and the activation signal S25 having the functions of the test apparatus 11, the test line 102, the signal recombination circuit 1011 having the specific signal input terminal P11, the determination circuit 1012, and the activation signal input terminal P1 in FIG.
2. Since it is the same as the other signal recombination circuit 111 having another specific signal input terminal P13 and the activation signal S15, detailed description thereof will be omitted. The difference between the test mode detecting device 201 in FIG. 5 and the test mode detecting device 101 in FIG.
Further includes a signal generator 2013 provided outside the integrated circuit 20. The other specific signal S23 and the specific signal S23 according to the usable state of the activation signal S25.
21 is generated and output.
11 and the signal recombination circuit 2011 generate and output a first recombined signal S24 and a second recombined signal S22 having the same function. Then, the discrimination circuit 20
In step 12, a usable operation is generated in accordance with a usable state of the start signal 25. If the first recombined signal S24 and the second recombined signal S22 are discriminated and compared, a test mode signal S26 is generated. The test line 202 provided inside the integrated circuit 20 is driven to enter the test mode. Otherwise the signal is different or the activation signal S2
When 5 returns to the use prohibited state, the integrated circuit 20 maintains the normal operation mode and achieves the original normal circuit function of the integrated circuit 20.

FIG. 6 is a diagram showing a preferred embodiment of the internal circuit of the signal generator 2013. In the figure, a signal generator 2013 includes a signal generator 20131 for generating and outputting a source signal S27, and a source signal S27.
Generator 2 which converts the signal into a state signal S28 and outputs it
0132 and a signal code circuit (encoder) 20133 for encoding the state signal S28 to generate and output another specific signal S23 or another specific signal S21. Needless to say, the other specific signal S23 and the specific signal S
21 can be the same specific signal.

FIG. 7 is a diagram showing another preferred embodiment of the test mode detecting apparatus according to the present invention. 7, a test circuit 31, a test line 302, a signal recombination circuit 3011 having a specific signal input terminal P31, and a determination circuit 30
12, start signal input terminal P34, other specific signal input terminal P3
Recombination circuit 311 having signal 3 and signal generator 301
3 and the start signal S36 respectively function as the test device 21, the test line 202, and the specific signal input terminal P in FIG.
Signal recombination circuit 2011 having 21 and discrimination circuit 201
2. Start signal input terminal P22, other specific signal input terminal P23
Signal recombination circuit 211 having
13 and the activation signal S25, so that the detailed description thereof will be omitted.

The difference between the test mode detecting device 301 in FIG. 7 and the test mode detecting device 201 in FIG. 5 is that the test mode detecting device 301 in FIG. Device 20
13 is provided inside the integrated circuit 30 of FIG. 7 to form a signal generating device 3013, and a multiplexing device, for example, a multiplexer 3014 is additionally provided thereto.
3 and the normal operation signal S34 of the integrated circuit 30 are output from the output pin P3 of the integrated circuit 30.
2 is to share. By doing so, the number of pins of the integrated circuit 30 can be further reduced.

In other words, the multiplex device 3014
Is a two-to-one multiplexer, and the selection signal terminal S of the multiplexer 3014 outputs a specific signal S31 or a normal operation signal S34 to an output pin terminal P32 according to the multiplex enable selection signal S33 input from the signal generator 3013. This is for outputting an output signal corresponding to whether the operation mode of the integrated circuit 30 is the test mode or the normal operation mode. In this case, if the signal output from the output pin P32 is the specific signal S31, the specific signal S31 is the first recombined signal S3 of the other recombining circuit 311.
5 and is input to the determination circuit 3012. At the same time, the signal recombination circuit 3011 generates the second recombination signal S32 in response to the specific signal S31, so that the discriminating circuit performs a usable operation in accordance with the usable state of the activation signal S36, and the first operation is performed. Recombination signal S35 and second
The test mode signal S37 is generated and output, and the integrated circuit 3
The test line 302 provided inside 0 is driven to enter the test mode. Otherwise, if the signal is different or the activation signal S36 returns to the use prohibited state,
The signal generation circuit 3013 stops the output or changes the state of the multiplex enable selection signal S32, and switches the multiplexer 3014 at the output pin P32 to the mode of the normal operation signal S34. That is, the integrated circuit 3
0 is maintained in the normal operation mode to achieve the original normal circuit function of the integrated circuit 30. As a relatively preferable method, the normal operation signal S34 can be a system oscillation output signal of the system oscillator in the integrated circuit 30, and the output pin can be the output pin of the system oscillator. FIG. 8 and FIG. 9 are flowcharts showing a test mode detection method according to the first and second embodiments of the present invention, respectively. The difference between FIG. 8 and FIG.
7 and FIG. 5 or FIG. 5 and FIG. 7, the explanation is omitted here.

[0069]

As described above, according to the test mode detecting apparatus and the detecting method of the present invention, it is possible to avoid a malfunction in which the integrated circuit enters the test mode by mistake, and to protect the confidentiality to a high degree. By measuring the integrated circuit without increasing the number of pins, it is possible to significantly and effectively improve the waste of cost, high pin count, low security, and low reliability in the conventional integrated circuit. .

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of a test mode detection device according to the present invention.

FIG. 2 is a diagram showing an example of the inside of a signal recombination circuit and another signal recombination circuit in the embodiment shown in FIG. 1;

FIG. 3 is a diagram showing an example of the inside of a signal recombination circuit and another signal recombination circuit in the embodiment shown in FIG. 1;

FIG. 4 is a diagram showing an example of a waveform of the signal recombination circuit in the embodiment shown in FIG.

FIG. 5 is a block diagram showing a second embodiment of the test mode detection device according to the present invention.

FIG. 6 is a diagram showing an example of the inside of a signal generation circuit in the embodiment shown in FIG. 5;

FIG. 7 is a block diagram showing a third embodiment of the test mode detection device according to the present invention.

FIG. 8 is a flowchart showing a first embodiment of a test mode detection method according to the present invention.

FIG. 9 is a flowchart illustrating a test mode detection method according to a second embodiment of the present invention.

[Explanation of symbols]

 11, 21, 31 Test device 101, 201, 301 Test mode detection device 102, 202, 302 Test line 1012, 2012, 3012 Discrimination circuit 1011, 2011, 3011 Signal recombination circuit 111, 211, 311 Other signal recombination circuit

Claims (9)

[Claims] 1. A test mode detecting device applied to an integrated circuit and provided in correspondence with a test device for generating a first recombination signal, comprising a specific signal input terminal, and receiving a specific signal. A signal recombination circuit for recombining the specific signal and outputting a second recombined signal; and whether the integrated circuit enters the test mode when the first and second recombined signals are input. And a determination circuit for determining whether or not the test mode is present. 2. The integrated circuit further includes a start signal input terminal electrically connected to the signal recombination circuit and the discriminating circuit, for inputting a start signal. A reset signal input terminal, wherein the start signal is a reset signal, and when both of the signal recombination circuit and the determination circuit are enabled according to the start signal, a usable operation occurs. On the other hand, the activation signal is disabled.
When the state becomes a state, the operation of making the signal recombination circuit and the determination circuit usable is stopped, and the usable state is a high level state or a low level state. The test mode detection device according to claim 1. 3. The test apparatus is an integrated circuit tester for measuring the internal characteristics and quality of an integrated circuit, and has another specific signal input terminal. And another signal recombination circuit that recombinates the other specific signal and generates an output of the first recombination signal, wherein the other signal recombination circuit further includes the other signal recombination circuit. It is provided with another delay code circuit that divides or recombines all or a part of the specific signal to obtain the first recombined signal, wherein the other signal recombining circuit is configured such that the other specific signal is A first flip-flop that is input and uses the other specific signal as a time pulse signal, and is electrically connected to the first flip-flop and outputs an output signal of the first flip-flop to the time pulse. signal And a third flip-flop electrically connected to the second flip-flop and using an output signal of the second flip-flop as a time pulse signal thereof. And the first,
2. The test mode according to claim 1, wherein the second and third flip-flops are both T-type flip-flops, and an output signal of these flip-flops is used as the first recombination signal. Detection device. 4. The first recombined signal is a serial or parallel recombined signal, and the signal recombining circuit further divides and recombines all or a part of the specific signal to produce the second recombined signal. The signal recombination circuit receives the specific signal, and uses the specific signal as its time pulse signal, a fourth flip-flop, The fifth flip-flop electrically connected to the fourth flip-flop and using the output signal of the fourth flip-flop as its time pulse signal.
And a sixth flip-flop electrically connected to the fifth flip-flop and using an output signal of the fifth flip-flop as its time pulse signal. The fifth and sixth flip-flops are both T
2. The test mode detecting device according to claim 1, wherein the test mode detecting device is a flip-flop. 5. The second recombined signal is a serial or parallel recombined signal, and the discriminating circuit is a comparator, and compares the first and second recombined signals and is identical. Generating a test mode signal to drive a test line provided inside the integrated circuit to enter the test mode, otherwise, the integrated circuit still maintains a normal operation mode state. The test mode detection device according to claim 1, wherein 6. The test mode detection device further comprises:
The other specific signal and the specific signal, the other signal recombination circuit and the signal recombination circuit includes a signal generation circuit that generates the first and second recombination signals, respectively, A signal generator for generating a source signal output; a state generator electrically connected to the signal generator for converting the source signal to a state signal output; and a state generator electrically connected to the state generator. A signal encoder for encoding the status signal to generate the other specific signal or the specific signal output, wherein the other specific signal or the specific signal is a serial or parallel specific signal; The signal generating circuit is electrically connected to the start signal input terminal, and when the start signal becomes available in response to the start signal, a usable operation occurs, and the start signal is used. When the state becomes the stop state, the operation of making the signal generation circuit usable is stopped, the signal generation circuit is provided inside the integrated circuit, and the test mode detection device further includes: A multiplexing device for allowing the specific signal and a normal operation signal of the integrated circuit to share an output pin of the integrated circuit, wherein the multiplexing device is a two-to-one multiplexer; The selection signal end of the specific signal or the multiplex enable selection signal input from the signal generation circuit so that the operation mode of the integrated circuit corresponds to a state where the operation mode is a test mode or a normal operation mode. The normal operation signal is output to the output pin, and the normal operation signal is a system in the integrated circuit. A system oscillation output signal of oscillator, the output pins detector test mode according to claim 1, characterized in that the output pin of the system oscillator. 7. A method for detecting a test mode applied to an integrated circuit provided corresponding to a test device for generating a first recombination signal, the method comprising: (a) inputting a specific signal; To carry out division and recombination according to the specific signal,
(B) inputting the first recombined signal to the integrated circuit; and (c) performing a discriminating operation of the first and second recombined signals. Judging whether or not the integrated circuit is in the test mode. 8. The method according to claim 1, further comprising: (d) applying a start signal to the integrated circuit before the step (a), wherein the steps (a) to () are performed only when the start signal is enabled. c) performing the steps (a) to (c) when the activation signal is in the prohibition state, and the usable state is a high level state or a low level state; The method according to claim 7, wherein the signal is a reset signal. 9. The test device is an integrated circuit tester for measuring internal characteristics and quality of the integrated circuit, wherein the test device receives another specific signal and generates the first recombination signal. Split, to output
The first recombination signal is a serial or parallel recombination signal, and the first and second recombination signals are discriminated and compared in the step (c). If they are the same, a test mode signal is generated to drive a test line provided inside the integrated circuit to enter the test mode, otherwise, the integrated circuit is still in the normal operation mode. The other specific signal or the specific signal is a serial or parallel specific signal, and the other specific signal and the specific signal are the same specific signal. And (e) switching the integrated circuit from a point where a normal operation signal is output to an output of the specific signal according to the start signal and the multiplex enable selection signal. A step of, (f) the method of detecting a test mode according to claim 7, wherein the specific signal comprising a step of generating the Enter first recombination signal to the test device.