JPH11174131A - Semiconductor-testing device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a semiconductor-testing device with a pattern rearrangement circuit, for rearranging a plurality of groups of pattern signals that have already been created in an external memory to continuous pattern signals without any joint, and then for transferring them to a pattern generator for storage. SOLUTION: A testing device transfers a pattern signal from an external memory for storing a pattern object that has been created in advance to a pattern storage memory 46 of a pattern generator, connects the pattern signal, outputs a test pattern from the pattern generator, gives it to DUT, and tests the DUT by a response signal from the DUT and an expectation value. Also, it has a pattern rearrangement circuit 10 for rearranging the pattern signal to form a continuously connected pattern object and then for storing the pattern object into the patter storage memory 46 when storing the pattern signal being transferred from the external memory into the pattern storage memory.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor test apparatus for transferring a plurality of pattern objects created in advance from an external memory to a pattern generator, storing the pattern objects, generating a test test pattern, and testing a DUT. More particularly, the present invention relates to a semiconductor test apparatus having a scan pattern generator for connecting and generating a plurality of scan patterns.

[0002]

2. Description of the Related Art First, an outline of a semiconductor test apparatus will be described. FIG. 4 shows a basic configuration diagram of the semiconductor test apparatus. The test processor 31 controls the entire apparatus,
A control signal is given to each unit by a tester bus. The pattern generator 32 generates an application pattern applied to the DUT 39 which is a semiconductor IC and an expected value pattern applied to the pattern comparator 37. The timing generator 33 generates a test pulse signal for obtaining a test period signal and a test timing of the entire apparatus, and supplies it to the waveform shaper 34, the comparator 36, the pattern comparator 37, and the like, and takes a test timing.

The waveform shaper 34 shapes the applied pattern from the pattern generator 32 into a test signal waveform, and forms a test signal waveform.
After 5, a test signal is given to the DUT 39. DUT3
9 is compared with a voltage by the comparator 36,
The resulting logic signal is provided to the pattern comparator 37. The pattern comparator 37 logically compares the logical pattern of the test result from the comparator 36 with the expected value pattern from the pattern generator 32 to detect a match / mismatch.
Is determined. Fail memory 38 if defective
And the information is stored together with the information from the pattern generator 32, and a failure analysis is performed later.

In this semiconductor test apparatus, the DUT 39
Test throughput by increasing throughput
Since the cost can be reduced, the development for it has been continued. One of the developments is to diversify and speed up the pattern generator 32. The pattern generator 32 has a DU
SQPG (SeQuential Patter)
n Generator) and ALPG (ALgorithmic Pattern Gene
rator). SQPG is a pattern generator for a logic LSI, and ALPG is a pattern generator for a memory LSI. These are used depending on the type of the DUT 39.

[0005] Meanwhile, semiconductor ICs have been remarkably developed, and are becoming more and more highly integrated. In recent LSIs (large-scale integrated circuits), LSIs in which a combinational circuit and a storage element are composed of a complex sequential circuit have appeared. To test these complex LSIs, LSSD (Level Sensitive Scan Des
ign) technique is used. As described above, with the development of the LSI as the DUT 39, the semiconductor test apparatus is also developing. Recent pattern generators 32 include SCPG (SCan Patt.
ern Generator) is prepared. SCPG is for scan test.

The SCPG stores and generates a scan pattern necessary to realize the LSSD test, and is a so-called pattern generator 32 for performing a scan test. As described above, the LSSD is one of the scan design techniques, in which an IC circuit composed of a combinational circuit and a storage element is formed by an extremely complicated sequential circuit. Therefore, a flip-flop capable of scanning so that the storage element can be accessed from an external pin is used. Use of flops and directly connecting them to access more flip-flops than a limited number of external pins. The test data of this scan pattern is a long and large amount of data.

[0007] The scan pattern test data is generally enormous. Therefore, usually, the external memory 40 such as the external disk 41 or the external magnetic tape 42 in FIG.
When a specific DUT 39 to be tested is determined, a pattern signal from each selected group for the DUT 39 is transmitted from the external memory 40 via the test processor 31 or The data is directly transferred to the table of the SCPG which is the pattern generator 32, that is, the pattern storage memory.

FIG. 5A shows an external memory 40 as an example.
FIG. 5B is a memory status diagram of the external disk 41,
FIG. 5C shows a schematic configuration diagram of an SCPG which is one of the pattern generators 32, particularly a memory status diagram of the pattern storage memory 46 and a configuration diagram of test pattern generation. FIG. 5C shows the generation of test patterns from the formatter 47 of the SCPG. FIG. In the external memory 40, for example, the external disk 41,
As shown in FIG. 5A, in the case of a fixed width of 64 bits per row, a large number of pattern objects having a width of 64 bits are stored in the memory. Each bit width of the pattern signal is 1
There are 6 bits, 64 bits and 32 bits. FIG.
(A) As shown in (a), in the case of 16 bits, four pattern signals are in one row, in (b), 64 bits are in one row, and in (c), a 32-bit pattern signal is Two signals are stored consecutively. The fixed width of one bit is 6
The number of bits may be doubled to 128 bits instead of four bits. In this specification, one row bit fixed width refers to the width of the maximum number of bits of data that can be stored in one row of the storage memory. Therefore, in the case of 64 bits, it is expressed as a fixed width of 64 bits per row.

Here, the pattern storage memory 46 has one row and six rows.
The maximum width is 4 bits. As shown in FIG. 5B, the pattern object of the external disk 41 is an SCPG
Is transferred to the pattern storage memory 46 as is. When a test is performed, parallel transfer is performed from the pattern storage memory 46 to the formatter 47 for each row of 64 bits under the control of the controller 48. As shown, the output line 49 from the formatter 47 is output for each pattern signal to generate a test pattern. In other words, the SCPG arbitrarily expands data of a fixed width of 64 bits per row into a 1-bit width to a 64-bit width when a test pattern is generated and outputs the data in parallel in order to correspond to a pattern signal of an arbitrary channel width.

[0010]

As described above, the SCP
In G, one row 64 of the pattern storage memory 46 is used as an example.
When a test pattern is generated, pattern data having a fixed bit width is developed for each pattern signal having an arbitrary channel width of 1 bit to 64 bits, such as 16 bits, 32 bits, or 64 bits, and a test pattern is output. Therefore, if pattern data having a fixed width of 64 bits per row is always recorded in the pattern storage memory 46, a test pattern can be smoothly generated.

However, the external disk 41
The various groups of pattern objects that have been created
Is generated by connecting the pattern storage memory
46 always has pattern data of a fixed width of 64 bits per row.
Not always memorized. FIG. 6 shows an example. Figure
6 (A) shows various patterns stored in the external disk 41.
It is a turn object.
Group and each block of (b) group and (c) group
To generate test patterns by connecting pattern signals to
And SCPG pattern storage memory 4 as it is
When you transfer to (6), each group of (a), (b) and
Loop data is concatenated for each block. One
Is smaller than the fixed width of one row bit
Has an empty pattern signal in the last line of most blocks.
Issue has occurred. When this connection pattern signal is read,
The output test pattern from the formatter 47 is shown in FIG.
(B). That is, the next of the test pattern A5
Pattern 50₁, 50_Two, 50 _ThreeIs meaningless, so-called
It occurs as an empty pattern. Next to test pattern B6
Pattern 51₁, 51_TwoThe same is true for Sky pattern
Only worsens test throughput
However, it can also cause malfunction. The ideal test
As shown in FIG. 6C, no pattern is generated
And are generated continuously.

According to the present invention, the pattern object of the SCPG is stored in the external disk 41 by connecting the pattern objects of a plurality of groups, each of which has already been created.
6 is transferred to the pattern storage memory 46 at the time of transfer.
An object of the present invention is to rearrange patterns and store them in a pattern object having no blank pattern and no empty pattern with a fixed width of 64 bits per row. On this occasion,
Since the transfer speed is reduced and the test throughput is deteriorated by using a computer program, it is executed at high speed by a hardware structure.

[0013]

According to a first aspect of the present invention, a pattern signal is transferred between an external memory and a pattern generator when transferring a pattern signal. Is also provided with a pattern rearrangement circuit for continuously connecting to a fixed width of one row bit of the pattern storage memory.

The second invention is an embodiment of an optimum configuration for the pattern rearrangement circuit. This pattern rearrangement circuit
The transfer D (data) register, the immediately preceding D (data) register, the shifter, the selector, and the remaining transfer controller are configured. First, the transferred pattern signal is received by a transfer D register having a fixed width of one row bit, and it is checked whether the pattern signal has been input to all bits. At this time, the pattern signal having the minimum number of bits is checked as one unit. For example,
Assuming that the fixed bit width of one row is 64 bits and the pattern signal having the minimum number of bits is 16 bits, the pattern signal of four units has been input to all the bits of one row. If there is only one unit of pattern signal in the transfer D register, the remaining transfer number, that is, the transfer remainder meaning that only one unit is effective, is set to 1 as the transfer remainder. In the case of a two-unit pattern signal, the remaining transfer number is two. In the case of a 4-unit pattern signal, all bits are valid, so
And This transfer remainder is set in the transfer remainder controller. The remaining transfer number after the second time is set in consideration of the effective pattern signal of the immediately preceding D register.

Next, the pattern signal transferred to the transfer D register is transferred to the shifter and the immediately preceding D register. When the remainder to be transferred is 0, the pattern signal is output from the shifter via the selector and transferred to the pattern storage memory. . When the remaining transfer number changes from 0 to 1, the transfer to the pattern storage memory is interrupted once, the pattern signal is sent from the transfer D register to the immediately preceding D register, the transfer D register inputs a new pattern signal, and the remaining transfer controller Is set to 1.

Next, the selector selects and outputs the first one unit from the immediately preceding D register and the remaining three units from the transfer D register under the control of the transfer remainder controller, and transfers them to the pattern storage memory. In the same way, the pattern signal is transferred under the appropriate control of the remaining transfer controller, and even if the pattern signal is transferred from various blocks in the external memory, it is continuously connected without blanks and the pattern of the pattern generator is stored. Transfer to memory.

The structure of the first invention is as follows. A pattern signal is transferred from an external memory storing a pattern object created in advance to a pattern storage memory of a pattern generator, a pattern pattern is connected, a test pattern is output from the pattern generator, and given to a DUT. A pattern generator for testing a DUT based on a response signal from an external device and an expected value. When a pattern signal transferred from an external memory is stored in a pattern storage memory, the pattern signal is rearranged and continuously connected. This is a semiconductor test apparatus having a pattern rearrangement circuit for storing a pattern object in a pattern storage memory.

The configuration of the second invention is as follows. The pattern rearrangement circuit according to the first aspect of the present invention includes the pattern storage memory,
A transfer D register for temporarily storing the pattern signal transferred with the fixed width of the row bit and outputting the pattern signal to the shifter and the immediately preceding D register; a shifter for inputting the pattern signal of the transfer D register and outputting the signal to one a input terminal of the selector; A D register immediately before inputting a pattern signal of the transfer D register and outputting it to the other b input terminal of the selector, a selector for selecting an a input terminal or b input terminal and outputting an input pattern signal to the pattern storage memory, This is a semiconductor test apparatus including a transfer remainder controller in which the transfer remainder of a register is set and the operation of the shifter and the selector is controlled by the transfer remaining number.

[0019]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described based on embodiments with reference to the drawings. FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is an explanatory view of transferring a pattern object of the present invention, and FIG. 3 is a pattern signal stored from an external disk via a pattern rearrangement circuit of the present invention. FIG. 3 shows several explanatory diagrams transferred to a memory. Here, the arrangement of the pattern signals in the rows in the memories of FIGS. 2 and 3 is opposite to the arrangement of FIGS. 5 and 6, but this is for ease of explanation and understanding. When the direction is reversed, they become the same. First, FIG. 2 will be described.

FIG. 2A is a memory status diagram in which pattern objects in the external memory 40 are stored. The external memory may be the external disk 41 or the external magnetic tape 42. For the sake of explanation, in this specification, the external disk 4 is mainly used.
1 will be described. In the external disk 41, the created pattern objects are stored by being segmented for each group. For example, they are separately recorded as shown in the group (a) and the group (b) in FIG. The last line of each group is not always full. Rather, as in (a) groups, there are usually several units available. When the data is transferred, the data is sequentially transferred rightward for each row. FIG.
(B) shows the pattern storage memory 4 of the pattern generator 32.
6 is a diagram showing a desirable memory condition stored in the memory 6 after the transfer of the pattern signal performed by the present invention. Input from left and output to right.

FIG. 1 shows a pattern rearrangement circuit 1 according to the present invention.
0 is a configuration diagram of an embodiment. FIG. In FIG. 1, a transfer D (data) register 11, a previous D (data) register 12, a shifter 13, a selector 14, and a transfer remainder controller 15 are provided. The data of the pattern signal transferred from the external memory 40 is input to the transfer D register 11, and if there is a remaining transfer, the remaining transfer is set in the remaining transfer controller 15, and the rearranged pattern signal is output to the pattern generator 32.
Is output to the pattern storage memory 46. This operation will be described with reference to FIG.

FIG. 3A shows (a) of the external disk 41.
FIG. 9 is an explanatory diagram for transferring the first line of a group to the first line of a pattern storage memory 46; Pattern signals A1, A in the first row
Since 2, A3 and A4 are pattern signals of 4 units,
The data is transferred to the transfer D register 11 and the remaining transfer controller 15 is set to 0, and the remaining transfer controller 15 controls the shifter 13 to connect to the entire path and the selector 14 to connect to the a input terminal of the shifter 13. Accordingly, the pattern signals A1, A2, A3, and A4 are not
Through the selector 14 and stored in the first row of the pattern storage memory 46.

FIG. 3B is an explanatory diagram for transferring the second line of the external disk 41 to the second line of the pattern storage memory 46. Second row pattern signals A5, A6, A7, A8
Is a pattern signal in units of four, so that it is transferred to the transfer D register 11 and 0 is set in the remaining transfer controller 15 as in the first row.
5 is a 100% pass to the shifter 13 and a shifter 1 is to the selector 14.
Control is performed so as to connect to the a input terminal on the third side. Last one
The pattern signal of the row has been transferred to the immediately preceding D register 12, but becomes unnecessary. Therefore, the pattern signals A5, A6,
A7 and A8 are directly stored in the second row of the pattern storage memory 46 via the shifter 13 and the selector 14.

FIG. 3C is an explanatory diagram for transferring the third line. The pattern signal in the third row is A9, /, /, / and one unit of the pattern signal, and three units are empty. Therefore, the data is transferred to the transfer D register 11 and the remaining transfer controller 15
Is set to 1. The remaining transfer controller 15 controls the shifter 13 and the selector 14 to temporarily stop.
The pattern signal of the immediately preceding second row has been transferred to the immediately preceding D register 12, but is unnecessary. There is no input pattern signal of the pattern storage memory 46. Here, when the change of the remaining transfer number is larger than the immediately preceding number, one pause is performed, and when the change is the same as the smaller number, the exchange operation for that number is performed.

FIG. 3D shows (b) of the external disk 41.
FIG. 11 is an explanatory diagram for transferring the first line of a group to a pattern storage memory 46; (B) The pattern signals B1, B2, B3, and B4 in the first row of the group are pattern signals of four units, but since the last transfer remainder 1 remains, it is set to the same 1 as before. In the immediately preceding D register 12, signals of A9, /, /, /, which are the immediately preceding pattern signals, are registered. Therefore, the remaining transfer controller 15 controls the selector 14 so that one unit is connected to the b input terminal of the immediately preceding D register 12 and the subsequent three units are connected to the a input terminal of the shifter 13. Accordingly, the pattern signal is stored in the third row of the pattern storage memory 46 for A9 from the immediately preceding D register 12 and for B1, B2, and B3 from the transfer D register 11 via the selector 14. Therefore, 3 of the pattern storage memory 46
In the row, A9, B1, B2, and B3 are stored.

FIG. 3E is an explanatory diagram for transferring the second row of the group (b). (B) The pattern signals B5, B6, B7, and B8 in the second row of the group are pattern signals of four units, but since the last transfer remainder 1 remains, the same as before. In the immediately preceding D register 12, signals of B4, /, /, /, which are the remainder of the immediately preceding pattern signal, are registered. Therefore, the remaining transfer controller 15 controls the selector 14 so that one unit is connected to the b input terminal of the immediately preceding D register 12 and the subsequent three units are connected to the a input terminal of the shifter 13. Therefore, the pattern signal is B4
Is transferred from the immediately preceding D register 12 and B5, B6, and B7 are transferred D
B4, B5, B6, and B7 are stored in the fourth row of the pattern storage memory 46 from the register 11 through the selector 14. Thereafter, pattern signals are continuously transferred from the external disk 41 to the pattern storage memory 46 in the same manner.

In this specification, the external disk 41 is mainly described as the external memory 40, but the present invention can be applied to the transfer of a pattern signal from the external magnetic tape 42 in the same manner. Although the pattern generator 32 has been mainly described by using the SCPG, the pattern generator 32 can be applied to both the SQPG and the ALPG, and is advantageously used.

[0028]

As described above in detail, according to the present invention, when transferring a pattern object from the external memory 40 of the semiconductor test apparatus to the pattern storage memory 46 of the pattern generator 32, it is divided into groups. By providing the pattern rearrangement circuit 10 of the present invention, the pattern objects thus created can be continuously combined and connected.

Therefore, unnecessary so-called empty patterns are not generated when connecting and generating signal patterns, so that the test throughput is improved and elements that cause malfunctions are eliminated. This is an effective technique for practical use.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of an embodiment of the present invention.

FIG. 2 is an explanatory diagram for transferring a pattern object according to the present invention. FIG. 2A is a diagram showing the memory status of the external memory 40, and FIG. 2B is a diagram showing the memory status of the pattern storage memory 46.

FIG. 3 is an explanatory diagram in which a pattern signal is transferred from an external disk (41) to a pattern storage memory 46 via the pattern rearrangement circuit 10 of the present invention. 3A is a transfer diagram of the first line A1, A2, A3, A4, FIG. 3B is a transfer diagram of the second line A5, A6, A7, A8, and FIG. 3C is a third line. A9, /, /, / are transfer diagrams, and FIG.
1, B2, B3, and B4. FIG. 3E is a transfer diagram of the fifth row B5, B6, B7, and B8.

FIG. 4 is a configuration diagram of an example of a conventional semiconductor test apparatus.

FIG. 5 is an explanatory diagram for transferring a pattern object and generating a test pattern. FIG. 5A shows the external memory 4.
FIG. 5 is a memory status diagram of the external disk 41 which is 0.
FIG. 5B is a diagram showing a memory situation of the pattern storage memory 46 and a configuration diagram of test pattern generation, and FIG. 5C is an explanatory diagram of test pattern generation order.

FIG. 6 is a diagram illustrating the order in which test patterns are generated. FIG.
FIG. 6A is a memory situation diagram stored in the pattern storage memory 46, FIG. 6B is a diagram in the order of generation of test patterns in the state of FIG. 6A, and FIG. It is a figure of the order of generation of a desirable test pattern.

[Explanation of symbols]

 Reference Signs List 10 pattern rearrangement circuit 11 transfer D register 12 last D register 13 shifter 14 selector 15 transfer remainder controller 31 test processor 32 pattern generator 33 timing generator 34 waveform shaper 35 driver 36 comparator 37 pattern comparator 38 fail memory 39 DUT ( (Device under test) 40 external memory 41 external disk 42 external magnetic tape 46 pattern storage memory 47 formatter 48 controller 49 output line

Claims (2)

[Claims] 1. A pattern signal is transferred from an external memory (40) storing a plurality of pattern objects created in advance to a pattern storage memory (46) of a pattern generator (32), and the pattern signals are connected. Then, the test pattern is stored in the pattern generator (32), the test pattern is output from the pattern generator (32) and given to the DUT (39), and the response signal and the expected value signal from the DUT (39) are obtained. In the semiconductor test apparatus for testing the DUT (39), when storing the pattern signals transferred from the external memory (40) in the pattern storage memory (46), the pattern signals are rearranged and continuously connected. A semiconductor test comprising a pattern rearrangement circuit (10) for converting an object into an object and storing the converted object in a pattern storage memory (46). Location. 2. A pattern rearranging circuit (10) temporarily stores a pattern signal transferred with a fixed width of one row bit in a pattern storage memory (46) and temporarily stores the pattern signal with a shifter (13).
Transfer D register (11) to output to register (12)
And a shifter (13) for inputting a pattern signal of the transfer D register (11) and outputting it to one input terminal (a) of the selector (14), and a selector (14) for inputting a pattern signal of the transfer D register (11). ) And a selector (12) for selecting an input terminal (a) or an input terminal (b) and outputting an input pattern signal to a pattern storage memory (46) by immediately preceding the output to the other input terminal (b). 14)
2. The controller according to claim 1, further comprising: a transfer remainder controller for setting a transfer remainder of the transfer D register and controlling the operation of the shifter and the selector by the transfer remainder. Semiconductor test equipment.