JPH1117143A - Semiconductor device and manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To contrive a miniaturization of a lower electrode, by a method wherein a capacitor is formed of the lower electrode, and a dielectric film and an upper electrode which are formed on this lower electrode. SOLUTION: An interlayer insulating film 15 is etched back with the mixed gas of carbon tetrafluoride and oxygen, for example, as the condition for etching the film 15, the upper part of a polysilicon film is made to protrude from the upper surface of the film 15, and the polysilicon film is used as a conductor plug 17. Then, the plug 17 is made to protrude from the upper surface of the film 15, a polysilicon film is laminated on the film 15 in such a way as to cover the upper part of this plug 17, and the polysilicon film is subjected to anisotropic etching, whereby a lower electrode 18 is formed. Then, a dielectric film 19 and an upper electrode 20 are laminated on the electrode 18, whereby a capacitor is formed. As a result, the electrode 18 can be formed without using a photoengraving technique and the formation of the electrode 18 can correspond to a miniaturization of the electrode 18 without the need to take a superposition margin into consideration.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing a semiconductor device, in which a margin of a space between lower electrodes of a plurality of capacitors is reduced.

[0002]

2. Description of the Related Art In a memory array occupying a large area on a semiconductor chip, a plurality of memory cell arrays for storing unit storage information are arranged in a matrix. Generally, one memory cell is composed of one MOS transistor and one capacitor connected thereto. This type of memory cell is called a one-transistor one-capacitor type memory cell. Since this type of memory cell has a simple configuration, it is easy to improve the degree of integration of the memory cell array.

[0003] Therefore, it is widely used in large-capacity DRAMs. Further, the memory cells of the DRAM can be classified into several types according to the structure of the capacitor. Among these, there is a so-called stacked capacitor. In the stacked capacitor, the capacitor portion is three-dimensionally enlarged to increase the facing area between the electrodes of the capacitor. Since the stacked capacitor has such characteristics, it is possible to secure the capacitance of the capacitor even when the element is miniaturized with the integration of the semiconductor device.

[0004] As a result, stacked capacitors have come to be widely used as semiconductor devices become more highly integrated.
However, a stacked capacitor requires a plug to be electrically connected to a silicon substrate. And
When the element is further miniaturized, a margin for overlapping the plug and the capacitor lower electrode is reduced. Further, there is a concern that the long-term reliability of the capacitor dielectric film of the stacked capacitor may be reduced due to the electric field concentration at the edge. This effect becomes relatively large due to miniaturization of the element.

In order to solve this problem, a semiconductor device as described in Japanese Patent Application Laid-Open No. 8-23036 has been conventionally provided. FIG. 16 is a cross-sectional view showing a configuration of a conventional semiconductor device. In the drawing, 1 is a substrate made of, for example, Si, 2 is an insulating film made of, for example, SiO ₂ formed in an element isolation region on the substrate 1, 3 is an interlayer insulating film made of, for example, SiO ₂ formed on the substrate 1, Reference numeral 4 denotes an impurity diffusion layer formed on the substrate 1.

Reference numeral 5 denotes a gate electrode as a word line formed on the substrate 1 sandwiched between the impurity diffusion layers 4 via a gate insulating film 6, 7 denotes a gate side wall insulating film formed on the side wall of the gate electrode 6, 8 is a gate upper insulating film formed on the upper surface of the gate electrode 6, 9 is an impurity diffusion layer 4 between the gate electrodes 6.
Bit lines formed to be electrically connected to
Is a contact hole formed in the interlayer insulating film 3 up to the impurity diffusion layer 4 of the substrate 1.

Reference numeral 11 denotes a storage electrode made of, for example, tungsten as a conductive film having an upper surface formed in a dome-like and uneven shape in the contact hole 10 and on the interlayer insulating film 3;
Reference numeral 12 denotes, for example, SiN formed on the storage electrode 11,
The dielectric film is made of SiO ₂ , a compound of Ta and O, or the like.

Next, a method of manufacturing the conventional semiconductor device having the above-described structure will be described with reference to FIGS. First, an insulating film 2 is formed on a substrate 1, and a gate insulating film 6 and a gate electrode 5 are formed at desired positions on the substrate 1 surrounded by the insulating film 2. Next, using the gate electrode 5 as a mask, impurities are diffused into the substrate 1 by a desired area to form an impurity diffusion layer 4. Next, insulating films 7 and 8 are formed on the gate electrode 5, and a bit line 9 is formed between the gate electrodes 5.

Next, an interlayer insulating film 3 is laminated on the substrate 1,
The interlayer insulating film 3 is etched down to the impurity diffusion layer 4 of the substrate 1 to form a contact hole 10, for example, HCl
And washing with an aqueous solution of H ₂ SO ₄ and NH ₃ . Then, for example, a dilute solution of HF is used to completely remove the SiO ₂ that is normally formed on the substrate 1 at the bottom of the contact hole 10 by several to several tens angstroms in the pre-cleaning step, thereby exposing the substrate 1 (FIG. 17A). ).

Next, using a selective CVD method, conditions are set as follows: forming temperature: 250 ° C. to 300 ° C .; gas: SiH ₄ / WF ₆ , WF
₆ partial pressure: 5 to 10 Pa, flow rate ratio of SiH ₄ / WF ₆ : 1 to 1
W13 is laminated as a condition of being laminated on Si of 1.5 and not being laminated on SiO ₂ . In the initial stage, W13 is stacked only in the contact hole 10 and is stacked in a state where the contact hole 10 is buried (FIG. 17B).

After W13 is buried in the contact hole 10, the W13 is laminated in a dome shape centering on the contact hole 10. Next, the storage electrode 11 is formed by controlling the film thickness of the W13 layer by the conventional time control (FIG. 17C). Next, a dielectric film 12 is laminated on the storage electrode 11 at a temperature of, for example, 400 to 500 ° C. by, for example, a low-temperature CVD method or a low-temperature sputtering method (FIG. 16).

[0012]

According to the semiconductor device configured as described above, the storage electrode 11 is formed without using photolithography by forming W13 by the selective CVD method. The present invention can be applied to miniaturization without having to consider the margin of superposition.

However, if a semiconductor device is to be formed by the above-described conventional method for manufacturing a semiconductor device, there is only a selective CVD method for a W film as a material in the current technology.
When an oxidizing atmosphere is used in laminating the dielectric film in the subsequent step of the W film, the W film is oxidized and cannot be used. Therefore, the raw materials are limited to those that can be stacked in a reducing atmosphere.

As described above, when the material of the storage electrode is limited, the material used in the subsequent process is naturally limited, and it is difficult to form a semiconductor device with a desired material. There is a point.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and has as its object to provide a semiconductor device which can be formed of a desired material and a method of manufacturing the semiconductor device.

[0016]

Means for Solving the Problems Claim 1 according to the present invention.
Has an interlayer insulating film formed on a semiconductor substrate, a contact hole formed in the interlayer insulating film up to the semiconductor substrate, and a portion embedded in the contact hole and protruding from the upper surface of the interlayer insulating film. A conductor plug; and a lower electrode covering the conductor plug and having a dome-shaped upper surface, wherein the lower electrode, a dielectric film formed on the lower electrode, and an upper electrode form a capacitor. is there.

According to a second aspect of the present invention, in the semiconductor device, an interlayer insulating film formed on the semiconductor substrate, a contact hole formed in the interlayer insulating film up to the semiconductor substrate, and embedded in the contact hole. A conductor plug, and a lower electrode covering the conductor plug and having an upper surface formed in a dome shape by surface tension, wherein a lower electrode, a dielectric film formed on the lower electrode and an upper electrode form a capacitor. Is formed.

According to a third aspect of the present invention, in the semiconductor device according to the second aspect, the upper surface of the interlayer insulating film is formed in a shape having irregularities, and the lower electrode is formed in a concave portion of the interlayer insulating film. Is what it is.

According to a fourth aspect of the present invention, there is provided the semiconductor device according to any one of the first to third aspects, wherein a barrier metal is provided between the conductor plug and the lower electrode.

According to a fifth aspect of the present invention, there is provided the semiconductor device according to any one of the first to fourth aspects, wherein the lower electrode is formed of platinum, iridium, palladium, ruthenium, or an alloy film containing these elements. Is what you do.

According to a sixth aspect of the present invention, in the method of manufacturing a semiconductor device, an interlayer insulating film is formed on a semiconductor substrate;
A contact hole is formed at a desired position in the interlayer insulating film up to the semiconductor substrate, and a first conductive film is stacked so as to fill the contact hole. Then, the first conductive film is etched back and the first conductive film is etched. Is left only in the portion buried in the contact hole, the interlayer insulating film is etched back, the upper portion of the first conductive film is projected from the upper surface of the interlayer insulating film, and the first conductive film is used as a conductor plug. A second conductive film is laminated so as to cover the body plug, and the second conductive film is anisotropically etched back to expose a part of the interlayer insulating film;
Is used as the lower electrode.

According to a seventh aspect of the present invention, in the method of manufacturing a semiconductor device according to the sixth aspect, a barrier metal is laminated between the conductor plug and the second conductive film. At the time of anisotropic etch back, the barrier metal is removed so that a part of the interlayer insulating film is exposed.

According to a second aspect of the invention, there is provided a method of manufacturing a semiconductor device, comprising: forming an interlayer insulating film on a semiconductor substrate;
A contact hole is formed at a desired position of the interlayer insulating film up to the semiconductor substrate, a first conductive film is laminated so as to fill the contact hole, and the first conductive film is etched back. The first conductive film is used as a conductor plug, and the second conductive film is laminated so as to fill the contact hole, so that the upper surface of the film is lower than the desired position of the upper surface of the interlayer insulating film. The second conductive film is etched back so as to be exposed, the interlayer insulating film is etched back, the second conductive film is exposed from the upper surface of the interlayer insulating film, and the second conductive film is heated and deformed. The second conductive film is a lower electrode that covers the conductor plug and has a dome-shaped upper surface due to the surface tension of the second conductive film.

According to a ninth aspect of the present invention, in the method of manufacturing a semiconductor device, an interlayer insulating film is formed on a semiconductor substrate.
A contact hole is formed at a desired position of the interlayer insulating film up to the semiconductor substrate, a first conductive film is laminated so as to fill the contact hole, and the first conductive film is etched back. The upper surface of the film is lower than the upper surface of the interlayer insulating film by a desired position, the first conductive film is used as a conductor plug, and the second conductive film is laminated so as to fill the contact hole. The second conductive film is etched back so as to lower the desired position, the interlayer insulating film is isotropically etched, the size of the upper portion of the contact hole is increased, and the unevenness is formed on the upper surface of the interlayer insulating film. When the insulating film is anisotropically etched to expose the second conductive film from the upper surface of the interlayer insulating film, the second conductive film is deformed by heating, and the second conductive film is placed in a concave portion of the interlayer insulating film. Cover the conductor plug and Upper surface by the surface tension of the conductive film in which a lower electrode composed of at dome.

According to a tenth aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising the steps of:
After a barrier metal is laminated between the conductor plug and the second conductive film, and the second conductive film is exposed from the upper surface of the interlayer insulating film, the barrier metal formed on the side wall of the second conductive film is formed. Is to be etched.

[0026]

BEST MODE FOR CARRYING OUT THE INVENTION

Embodiment 1 FIG. Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a sectional view showing a configuration of the semiconductor device according to the first embodiment of the present invention. In the figure, the same parts as those in the conventional case are denoted by the same reference numerals, and description thereof will be omitted.
14 is an insulating film formed so as to cover the bit line 9;
Is an interlayer insulating film formed so as to cover the insulating film 14,
Reference numeral 16 denotes a contact hole formed in the interlayer insulating film 15 up to the impurity diffusion layer 4 of the substrate 1.

Reference numeral 17 denotes a conductor plug buried in the contact hole 16 and has a portion protruding from the upper surface of the interlayer insulating film 15. Reference numeral 18 denotes a conductor plug 1
A lower electrode 19 covering the base 7 and having a dome-shaped upper surface, a dielectric film 19 formed on the lower electrode 18, and an upper electrode 20 formed on the dielectric film 19.

Next, a method of manufacturing the semiconductor device according to the first embodiment configured as described above will be described with reference to FIGS. First, as in the conventional case, the substrate 1
An insulating film 2 is formed thereon, and a gate insulating film 6 and a gate electrode 5 are formed at desired positions on the substrate 1 surrounded by the insulating film 2.

Next, using the gate electrode 5 as a mask, impurities are diffused into the substrate 1 by a desired area to form an impurity diffusion layer 4. Next, insulating films 7 and 8 are formed on the gate electrode 5, a bit line 9 is formed between the gate electrodes 5, and an insulating film 14 is formed so as to cover the bit line 9.

Next, an interlayer insulating film 15a is laminated on the substrate 1 to a thickness of, for example, 15,000 angstroms. Next, a resist is applied on the interlayer insulating film 15a, and is patterned by using photolithography to form a resist film 21. Then, using the resist film 21 as a mask, the interlayer insulating film 15a is etched down to the impurity diffusion layer 4 of the substrate 1. Then, a contact hole 16a having an opening having a diameter of, for example, 0.2 μm is formed to expose the substrate 1 (FIG. 2A).

Next, the resist film 21 is removed (FIG. 2).
(B)). Next, using, for example, a low pressure CVD method, the film forming conditions are as follows: temperature: 550 ° C .;
sccm and phosphine were flowed at 20 sccm, respectively, under the condition of pressure: 5 Torr and contact hole 1
A polysilicon film 22 as a first conductive film is formed so as to fill the inside of 6a (FIG. 2C).

Next, the polysilicon film 22 is formed, for example, by RI
Using an E magnetron etcher, the etching conditions were as follows: etching gas: oxygen at 10 sccm, carbon tetrafluoride at 50 sccm, pressure: 20 mTo
Etchback is performed under the conditions of rr and output: 500 W, and only the polysilicon film 22a embedded in the contact hole 16a remains (FIG. 3A).

Next, the interlayer insulating film 15a is etched back with an etching condition, for example, an etching gas: a mixed gas of carbon tetrafluoride and oxygen to a thickness of, for example, 5000 angstroms, and the upper portion of the polysilicon film 22a is etched. The polysilicon film 22a is made to project 5000 angstroms from the upper surface of the interlayer insulating film 15, and the polysilicon film 22a is used as the conductor plug 17 (FIG.
(B)).

Next, as an isotropic film forming method, for example, a low pressure CVD method is used, and as a film forming condition, a raw material gas: silane is flowed at 300 sccm and phosphine is flowed at 20 sccm. : 550 ° C
Under the condition of holding, the second
A polysilicon film 23 doped with, for example, phosphorus as a conductive film is laminated with a thickness of, for example, 5000 angstroms (FIG. 3C).

Next, the polysilicon film 18a is, for example, R
Using an IE magnetron etcher, etching conditions were as follows: etching gas: chlorine at 40 sccm, helium at 10 sccm, and pressure: 10 mTorr.
r, output: 500 W, anisotropic etch-back is performed at a thickness of, for example, 7000 angstroms, exposing a part of the interlayer insulating film 15, and reliably separating the polysilicon film to form the lower electrode 18. (FIG. 4).

The lower electrode 18 thus formed is formed by anisotropically etching back the polysilicon film 18a.
Is formed in a dome shape having a circle on the bottom surface having the radius of the thickness of the polysilicon film 18a that covers the polysilicon film 18a. That is, by controlling the thickness of the polysilicon film 18a, the size of the lower electrode 18 and the height of the protruding portion of the conductor plug 17 are controlled, whereby the lower electrode 1
8 can be controlled.

In this example, since the height of the protruding portion of the conductor plug 17 is 5,000 Å and the polysilicon film 18a is laminated at 5,000 Å, the lower electrode 18 is formed in a hemispherical shape having a diameter of 1 μφ. The Rukoto. Next, a capacitor is formed by laminating the dielectric film 19 and the upper electrode 20 on the lower electrode 18 (FIG. 1).

In the semiconductor device of the first embodiment configured as described above, the conductor plug 17 is projected from the upper surface of the interlayer insulating film 15 and the polysilicon film 2 is formed so as to cover the upper portion.
3 and anisotropically etching the lower electrode 1
Since the lower electrode 8 is formed, the lower electrode 18 can be formed without using a photoengraving technique, and it is possible to cope with miniaturization without having to consider a margin for superposition.

The material of the lower electrode 18 is the same as that of the above embodiment.
As shown in Embodiment 1, the polysilicon film was formed.
Alternatively, the conductor plug 17 is made of a tungsten film.
Or titanium nitride film,
The electrode 18 is made of, for example, aluminum other than the polysilicon film.
It can be formed of a film or a copper film. These materials
When the lower electrode 18 is formed by
Si made of non-oxide _ThreeN_FourCan be used.

When the conductor plug 17 is formed of a tungsten film or a titanium nitride film, as another example, platinum, iridium, palladium, ruthenium, or an alloy film containing these elements can be used. When formed of such a material, the material of the dielectric film to be used later is not limited, and besides the above-mentioned Si ₃ N ₄ , for example, BaSrTiO ₃ , PdZrT
A dielectric film 19 made of an oxide such as iO ₃ can also be used.

Embodiment 2 FIG. 5 is a sectional view showing a configuration of the semiconductor device according to the second embodiment of the present invention. In the figure, the same parts as those in the first embodiment are denoted by the same reference numerals, and description thereof is omitted. 24 is a barrier metal formed so as to cover the conductor plug 17, 25 is a lower electrode which covers the barrier metal 24 and has a dome-shaped upper surface, 26 is a dielectric film formed on the lower electrode 25,
27 is an upper electrode formed on the dielectric film 26.

Next, a method of manufacturing the semiconductor device of the second embodiment configured as described above will be described with reference to FIGS. First, a conductor plug 17 having a protruding portion from the upper surface of the interlayer insulating film 15 is formed through the same steps as in the first embodiment.

Next, for example, using a reactive sputtering method,
As film forming conditions, temperature: 400 ° C., power: 500 W,
Source gas: Flow nitrogen at 100 sccm, pressure: 20
Under a condition of mTorr, a titanium target is sputtered to laminate the barrier metal 24a to a thickness of, for example, 300 Å (FIG. 6A).

Next, for example, an aluminum film 28 as a second conductive film is formed by an isotropic film forming method, for example, to a thickness of 5000.
The layers are laminated with a thickness of on-demand (FIG. 6B). next,
The aluminum film 28 is etched back with a thickness anisotropy of, for example, 7000 angstroms. Next, the barrier metal film 24a is, for example, sputter-etched under an etching condition of flowing an etching gas: argon at 50 sccm, a pressure: 20 mTorr, an RF: 500 W, 30
Etching back is performed at 0 gauss to expose a part of the interlayer insulating film 15, and the aluminum film is surely separated to form the lower electrode 25 (FIG. 6C).

The size of the lower electrode 25 thus formed can be controlled in the same manner as in the first embodiment. In this example, as in the first embodiment, the lower electrode 25 is formed in a hemispherical shape having a diameter of 1 μφ. Next, a capacitor is formed by laminating the dielectric film 26 and the upper electrode 27 on the lower electrode 25 (FIG. 5).

In the semiconductor device of the second embodiment configured as described above, similarly to the first embodiment, the lower electrode 25 can be formed without using photolithography.
It is possible to cope with miniaturization without having to consider the margin of superposition.

The material of the lower electrode 25 is that the barrier metal 24 is formed on the conductor plug 17 even if the conductor plug 17 is formed of a polysilicon film.
As described in the first embodiment, a copper film, platinum, iridium, palladium, ruthenium, an alloy film containing any of these elements, or the like may be used as appropriate depending on the material of the dielectric film 26.

Embodiment 3 FIG. 7 is a sectional view showing a configuration of the semiconductor device according to the third embodiment of the present invention. In the figure, the same parts as those in the above embodiments are denoted by the same reference numerals, and description thereof will be omitted. Reference numeral 29 denotes an interlayer insulating film formed so as to cover the insulating film 14, and reference numeral 30 denotes a contact hole formed in the interlayer insulating film 29 to reach the impurity diffusion layer 4 of the substrate 1.

Reference numeral 31 denotes a conductor plug buried in the contact hole 30; 32, a barrier metal formed on the upper surface of the conductor plug 31;
1 is a lower electrode having a dome-shaped upper surface, 34 is a dielectric film formed on the lower electrode 33, and 35 is an upper electrode formed on the dielectric film 34.

Next, a method of manufacturing the semiconductor device of the third embodiment configured as described above will be described with reference to FIGS. First, as in the above embodiments, an insulating film 2 is formed on a substrate 1, and a gate insulating film 6 and a gate electrode 5 are formed at desired positions on the substrate 1 surrounded by the insulating film 2. .

Next, using the gate electrode 5 as a mask, impurities are diffused into the substrate 1 by a desired area to form an impurity diffusion layer 4. Next, insulating films 7 and 8 are formed on the gate electrode 5, a bit line 9 is formed between the gate electrodes 5, and an insulating film 14 is formed so as to cover the bit line 9.

Next, an interlayer insulating film 29a is laminated on the substrate 1 to a thickness of, for example, 15,000 angstroms. Next, a resist is applied on the interlayer insulating film 29a and is patterned by using a photolithography technique to form a resist film 36. Then, using the resist film 36 as a mask, the interlayer insulating film 29a is etched down to the impurity diffusion layer 4 of the substrate 1. Then, a contact hole 30a having an opening having a diameter of, for example, 0.2 μm is formed to expose the substrate 1 (FIG. 8A).

Next, the resist film 36 is removed (FIG. 8).
(B)). Next, using, for example, a low pressure CVD method, the film forming conditions are as follows: temperature: 550 ° C .;
sccm and phosphine were flowed at 20 sccm, respectively, and the contact hole 3 was formed under the condition of pressure: 5 Torr.
A polysilicon film 37 as a first conductive film is formed so as to bury the inside of Oa (FIG. 8C).

Next, the polysilicon film 37 is formed, for example, by RI
Using an E magnetron etcher, the etching conditions were as follows: etching gas: oxygen at 10 sccm, carbon tetrafluoride at 50 sccm, pressure: 20 mTo
Etch back under the condition of rr, output: 500 W, so as to be lower than the upper surface of the contact hole 30 a by a desired position, for example, 5000 angstroms, and this polysilicon film is used as the conductor plug 31 (FIG. 9A). ).

Next, for example, using a reactive sputtering method,
As film forming conditions, temperature: 300 ° C., power: 500 W,
Source gas: Nitrogen flows at 50 sccm, pressure: 5 mT
Under the conditions of orr, a titanium target is sputtered to laminate the barrier metal 32a to a thickness of, for example, 300 angstroms.

Next, for example, using a reactive sputtering method,
As film forming conditions, temperature: 300 ° C., power: 400 W,
Source gas: Argon is flowed at 20 sccm, pressure: 5
At mTorr, a platinum target was sputtered, and the second
Platinum film 38 as a conductive film of contact hole 30a
Are laminated so as to be embedded (FIG. 9B).

Next, the platinum film 38 and the barrier metal 32a laminated on the interlayer insulating film 29a are etched by, for example, a chemical mechanical polishing method (hereinafter, abbreviated as CMP method) to remove the platinum film 38 embedded in the contact hole 30a. Only the film 38a and the barrier metal 32b remain (FIG. 9C).

Next, the interlayer insulating film 29a is etched back with an etching condition of, for example, an etching gas: a mixed gas of carbon tetrafluoride and oxygen to a thickness of, for example, 5000 angstroms to form the platinum film 38a and the barrier metal 3a.
2b is, for example, 5000
An on-demand projection is made (FIG. 10A).

Next, the barrier metal 32b formed on the side wall of the platinum film 38a projected on the interlayer insulating film 29
Is removed under the conditions of, for example, an etching gas: chlorine flowing at 40 sccm, a pressure: 10 mTorr, and an output: 500 W, and the barrier metal 32 is formed only at a portion between the conductor plug 31 and the platinum film 38 a. (FIG. 10B).

Next, the platinum film 38a is heated at, for example, 800 ° C. for 5 minutes, thereby deforming the platinum film 38a and causing the lower electrode 3 having a dome-shaped upper surface by surface tension.
Form 3 The lower electrode 33 thus formed is
Since the platinum film 38a is deformed and formed by the surface tension, the lower electrode 33 is formed by the interlayer insulating film 2 of the platinum film 38a.
The deposit corresponding to the height protruding from 9 is formed in a shape that forms a hemispherical deposit. That is, the size of the lower electrode 33 can be controlled by controlling the height of the protruding portion of the platinum film 38a.

In this example, since the protruding portion of the platinum film 38a is formed of a column having a height of 5000 angstroms and a diameter of 0.2 μm, the lower electrode 33 is, for example, a hemisphere having a diameter of 0.4 μm. Will be formed. Next, a capacitor is formed by laminating the dielectric film 34 and the upper electrode 35 on the lower electrode 33 (FIG. 7).

In the semiconductor device of the third embodiment configured as described above, the platinum film 38a protrudes from the upper surface of the interlayer insulating film 29, and this is deformed by heating to form a dome-shaped lower electrode 33 by surface tension. Therefore, the lower electrode 33 can be formed without using a photoengraving technique, and the present invention can be applied to miniaturization without having to consider a margin for superposition.

The material of the lower electrode 33 can be formed of platinum or another material as described in the third embodiment. As a condition of the material, the deformation due to heating of the second conductive film is formed in a process prior to the lower electrode formed by the deformation.
For example, any material may be used as long as it can be formed in a range where no problem occurs in the impurity diffusion layer 4. It is considered that any material that can be substantially heated and deformed at 900 ° C. or less is suitable.

As an example, it can be formed of, for example, an aluminum film or a copper film. When the lower electrode 33 is formed of these materials, the dielectric film 19 may be made of non-oxide Si ₃ N ₄ .

As another example, iridium, palladium, ruthenium, an alloy film containing these elements, an alloy film containing platinum, or the like can be used. When formed of such a material, similarly to the platinum film described in the third embodiment, the material of the dielectric film to be used later is not limited, and other than Si ₃ N ₄ described above. For example, a dielectric film 34 made of an oxide such as BaSrTiO ₃ or PdZrTiO ₃ can be used.

In the third embodiment, the barrier metal 32 is provided between the conductor plug 31 and the lower electrode 33.
Although the example which forms is shown, it is not limited to this,
If the conductor plug is formed of, for example, tungsten or titanium nitride, any of the above-mentioned materials can be formed as shown in the third embodiment without providing a barrier metal. .

Embodiment 4 FIG. 11 is a sectional view showing a configuration of a semiconductor device according to a fourth embodiment of the present invention.
In the figure, the same parts as those in the above embodiments are denoted by the same reference numerals, and description thereof will be omitted. Reference numeral 39 denotes an interlayer insulating film formed so as to cover the insulating film 14, which is formed to have irregularities on the upper surface. Reference numeral 40 denotes a contact hole formed in the recessed portion of the interlayer insulating film 39 up to the impurity diffusion layer 4 of the substrate 1.

Reference numeral 41 denotes a conductor plug buried in the contact hole 40, reference numeral 42 denotes a barrier metal formed on the upper surface of the conductor plug 41, and reference numeral 43 denotes a recess formed in the interlayer insulating film 39 to cover the conductor plug 41. The lower electrode 44 has a dome-shaped upper surface, a dielectric film 44 formed on the lower electrode 43, and an upper electrode 45 formed on the dielectric film 44.

Next, a method of manufacturing the semiconductor device of the fourth embodiment configured as described above will be described with reference to FIGS.
It will be described based on the following. First, as in the above embodiments, an insulating film 2 is formed on a substrate 1, and a gate insulating film 6 and a gate electrode 5 are formed at desired positions on the substrate 1 surrounded by the insulating film 2. .

Then, using the gate electrode 5 as a mask, impurities are diffused into the substrate 1 by a desired area to form an impurity diffusion layer 4. Next, insulating films 7 and 8 are formed on the gate electrode 5, a bit line 9 is formed between the gate electrodes 5, and an insulating film 14 is formed so as to cover the bit line 9.

Next, an interlayer insulating film 39a is laminated on the substrate 1 to a thickness of, for example, 17000 angstroms. Next, a resist is applied on the interlayer insulating film 39a, and is patterned by using photolithography to form a resist film 46. Then, using the resist film 46 as a mask, the interlayer insulating film 39a is etched down to the impurity diffusion layer 4 of the substrate 1. Then, a contact hole 40a having an opening having a diameter of, for example, 0.2 μm is formed to expose the substrate 1 (FIG. 12A).

Next, the resist film 46 is removed (FIG. 12).
(B)). Next, using, for example, a low pressure CVD method, the film forming conditions are as follows: temperature: 550 ° C .;
sccm and phosphine at a flow rate of 20 sccm, respectively.
A polysilicon film 47 as a first conductive film is formed so as to bury the inside of Oa (FIG. 12C).

Next, the polysilicon film 47 is formed, for example, by RI
Using an E magnetron etcher, the etching conditions were as follows: etching gas: oxygen at 10 sccm, carbon tetrafluoride at 50 sccm, pressure: 20 mTo
Etching back under the condition of rr, output: 500 W, and a desired position from the upper surface of the contact hole 40a, for example, 70
The polysilicon film is used as the conductor plug 41 so as to be lower by 00 angstroms (FIG. 13A).

Next, for example, using a reactive sputtering method,
As film forming conditions, temperature: 300 ° C., power: 500 W,
Source gas: Nitrogen flows at 50 sccm, pressure: 5 mT
Under the conditions of orr, a titanium target is sputtered to laminate the barrier metal 42a to a thickness of, for example, 300 angstroms.

Next, for example, using a reactive sputtering method,
As film forming conditions, temperature: 300 ° C., power: 400 W,
Source gas: Argon is flowed at 20 sccm, pressure: 5
At mTorr, a platinum target was sputtered, and the second
Platinum film 48 as a conductive film is formed in contact hole 40a.
Are laminated so as to be embedded (FIG. 13B).

Next, the platinum film 48 and the barrier metal 42a laminated on the interlayer insulating film 39a are etched by, for example, the CMP method, and only the platinum film 48a and the barrier metal 42b embedded in the contact hole 40a remain ( FIG. 13 (c)).

Next, the platinum film 48a is etched using aqua regia as an etching condition so as to be at a desired position, for example, 2000 angstroms lower than the upper surface of the interlayer insulating film 39a. At this time, since the etching rate of the barrier metal 42b is slightly higher than the etching rate of the platinum film 48a, the barrier metal 42c is etched more than 2000 angstroms (FIG. 14A).

Next, the interlayer insulating film 39a is subjected to isotropic etching, for example, wet etching using dilute hydrofluoric acid (2 to 3%) to enlarge the size of the upper part of the contact hole 40, and An unevenness is formed on the surface. At this time, the size of the recess is about 2,000 angstroms in the depth direction,
It has a size of about 2,000 angstroms on each side in the width direction. This size can be controlled by how much the platinum film 48b is formed lower than the upper surface of the interlayer insulating film 39a in the above process (FIG. 14B).

Next, the interlayer insulating film 39c having an uneven top surface is etched under anisotropic etching conditions, for example, using an etching gas: a mixed gas of carbon tetrafluoride and oxygen, for example, 3000 angstroms. The thickness is etched back, and the upper portions of the platinum film 48b and the barrier metal 42c are projected, for example, 5000 angstroms from the upper surface of the interlayer insulating film 39 (FIG. 14C).

Next, the barrier metal 42c formed on the side wall of the platinum film 48b projecting above the interlayer insulating film 39 is removed.
As etching conditions, for example, etching gas: chlorine is flowed at 40 sccm, pressure is 10 mTorr, and output is:
Under the condition of 500 W, the barrier metal 42 is removed, and the barrier metal 42 is left only at a portion between the conductor plug 41 and the platinum film 48b (FIG. 15A).

Next, the platinum film 48a is heated at, for example, 800 ° C. for 5 minutes. At this time, the deformation of the platinum film 48a stays at the concave portion on the upper surface of the interlayer insulating film 39,
Connection to another adjacent platinum film is reliably prevented. As in the case of the third embodiment, the platinum film 48a is deformed at the concave portion of the interlayer insulating film 39, and the lower electrode 43 having a dome-shaped upper surface is formed by surface tension.

Since the lower electrode 43 formed in this manner is formed by deforming the platinum film 48b and by the surface tension, the lower electrode 43 is formed by the interlayer insulating film 39 of the platinum film 48b.
Is formed in a shape that forms a hemispherical deposit. That is, the size of the lower electrode 43 can be controlled by controlling the height of the protruding portion of the platinum film 48a.

In this example, since the protruding portion of the platinum film 48a is formed of a column having a height of 5000 angstroms and a diameter of 0.2 μm, although the lower electrode 43 is slightly different from the recess of the interlayer insulating film 39, For example, it is formed as a hemisphere having a diameter of 0.4 μm. Next, the lower electrode 4
By laminating the dielectric film 44 and the upper electrode 45 on 3, a capacitor is formed (FIG. 11).

In the semiconductor device of the fourth embodiment configured as described above, the platinum film 48a protrudes from the upper surface at the concave portion of the interlayer insulating film 39, and this is deformed by heating, and the dome-shaped lower portion is formed by surface tension. The electrode 33 can be reliably formed at the concave portion of the interlayer insulating film 39. Therefore,
The lower electrode 43 can be formed without using a photoengraving technique, and it is possible to cope with miniaturization without having to consider a margin for superposition.

Further, as the material of the lower electrode 43, other materials can be used as in the case of the third embodiment. Further, similar to the third embodiment, an example in which the barrier metal 42 is formed between the conductor plug 41 and the lower electrode 43 has been described. However, the present invention is not limited to this. If it is made of tungsten or titanium nitride, any of the above-mentioned materials can be formed as shown in the fourth embodiment without providing a barrier metal.

[0086]

As described above, according to claim 1 of the present invention, an interlayer insulating film formed on a semiconductor substrate, a contact hole formed in the interlayer insulating film up to the semiconductor substrate, and a contact hole A conductive plug having a portion embedded in and protruding from the upper surface of the interlayer insulating film; and a lower electrode covering the conductive plug and having a dome-shaped upper surface. The lower electrode and the lower electrode are formed on the lower electrode. Since a capacitor is formed with the dielectric film and the upper electrode, it is possible to provide a semiconductor device that can be miniaturized.

According to a second aspect of the present invention, an interlayer insulating film formed on a semiconductor substrate, a contact hole formed in the interlayer insulating film up to the semiconductor substrate, and a conductor embedded in the contact hole A plug, and a lower electrode that covers the conductor plug and has an upper surface formed in a dome shape by surface tension. A capacitor is formed by the lower electrode, the dielectric film formed on the lower electrode, and the upper electrode. Since it is formed, a semiconductor device which can be miniaturized can be provided.

According to a third aspect of the present invention, in the second aspect, the upper surface of the interlayer insulating film is formed in a shape having irregularities, and the lower electrode is formed in a concave portion of the interlayer insulating film. Therefore, it is possible to provide a semiconductor device that can reliably prevent the lower electrode from contacting another defective portion.

According to a fourth aspect of the present invention, in any one of the first to third aspects, a barrier metal is provided between the conductor plug and the lower electrode. It is possible to provide a semiconductor device capable of relaxing the restrictions on the materials of the above.

According to a fifth aspect of the present invention, in any one of the first to fourth aspects, the lower electrode is
Since the semiconductor device is formed using platinum, iridium, palladium, ruthenium, or an alloy film containing any of these elements, it is possible to provide a semiconductor device capable of relaxing the restriction on the material of the dielectric film.

According to a sixth aspect of the present invention, an interlayer insulating film is formed on a semiconductor substrate, and a contact hole is formed at a desired position of the interlayer insulating film up to the semiconductor substrate. When the first conductive film is stacked so as to be buried, the first conductive film is etched back, and the first conductive film is left only in the portion buried in the contact hole, and the interlayer insulating film is etched back. An upper portion of the conductive film is projected from an upper surface of the interlayer insulating film, a first conductive film is used as a conductive plug, a second conductive film is stacked so as to cover the conductive plug, and the second conductive film is anisotropically. Since the etch back is performed to expose a part of the interlayer insulating film and the second conductive film is used as a lower electrode, a method for manufacturing a semiconductor device which can be miniaturized can be provided.

According to a seventh aspect of the present invention, in the sixth aspect, a barrier metal is laminated between the conductor plug and the second conductive film, and an anisotropic etch-back of the second conductive film is performed. In this case, since the barrier metal is removed so that a part of the interlayer insulating film is exposed, it is possible to provide a method of manufacturing a semiconductor device capable of relaxing the restrictions on the material of the conductor plug and the lower electrode. Becomes

According to the eighth aspect of the present invention, an interlayer insulating film is formed on a semiconductor substrate, and a contact hole is formed at a desired position of the interlayer insulating film up to the semiconductor substrate. A first conductive film is stacked so as to be embedded, and the first conductive film is etched back so that the upper surface of the first conductive film is lower than the upper surface of the interlayer insulating film by a desired position. A second conductive film is stacked so as to fill the contact hole, the second conductive film is etched back so that the upper surface of the interlayer insulating film is exposed, and the interlayer insulating film is etched back. The second conductive film is exposed from the upper surface of the interlayer insulating film, and the second conductive film is deformed by heating.
Since the lower electrode has a dome-shaped upper surface due to the surface tension of the conductive film, it is possible to provide a method of manufacturing a semiconductor device which can be miniaturized.

According to a ninth aspect of the present invention, an interlayer insulating film is formed on a semiconductor substrate, and a contact hole is formed at a desired position of the interlayer insulating film up to the semiconductor substrate. A first conductive film is stacked so as to be embedded, and the first conductive film is etched back so that the upper surface of the first conductive film is lower than the upper surface of the interlayer insulating film by a desired position. A second conductive film is stacked so as to fill the inside of the contact hole, and the second conductive film is etched back so as to be lower than a desired position from the upper surface of the interlayer insulating film, and the interlayer insulating film is isotropic. Etching, expanding the size of the upper part of the contact hole, forming an uneven shape on the upper surface of the interlayer insulating film, anisotropically etching the interlayer insulating film, and exposing the second conductive film from the upper surface of the interlayer insulating film. And a second conductive film Since the second conductive film covers the conductive plug at the concave portion of the interlayer insulating film and becomes a lower electrode having a dome-shaped upper surface due to the surface tension of the second conductive film, the second conductive film is miniaturized. It is possible to provide a method for manufacturing a semiconductor device that can reliably prevent the lower electrode from contacting another defective portion.

According to a tenth aspect of the present invention, in the eighth or ninth aspect, a barrier metal is laminated between the conductor plug and the second conductive film, and the second conductive film is formed between the conductive plug and the second conductive film. Since the barrier metal formed on the side wall of the second conductive film is etched after being exposed from the upper surface of the insulating film, it is possible to manufacture a semiconductor device capable of relaxing the restrictions on the material of the conductor plug and the lower electrode. It is possible to provide a method.

[Brief description of the drawings]

FIG. 1 is a sectional view illustrating a configuration of a semiconductor device according to a first embodiment of the present invention;

FIG. 2 is a cross-sectional view showing a method for manufacturing the semiconductor device shown in FIG.

FIG. 3 is a sectional view illustrating the method of manufacturing the semiconductor device illustrated in FIG. 1;

FIG. 4 is a sectional view illustrating the method of manufacturing the semiconductor device illustrated in FIG. 1;

FIG. 5 is a sectional view showing a configuration of a semiconductor device according to a second embodiment of the present invention;

FIG. 6 is a sectional view illustrating the method of manufacturing the semiconductor device illustrated in FIG. 5;

FIG. 7 is a sectional view illustrating a configuration of a semiconductor device according to a third embodiment of the present invention;

FIG. 8 is a sectional view illustrating the method of manufacturing the semiconductor device illustrated in FIG. 7;

FIG. 9 is a sectional view illustrating the method of manufacturing the semiconductor device illustrated in FIG. 7;

FIG. 10 is a sectional view illustrating the method of manufacturing the semiconductor device illustrated in FIG. 7;

FIG. 11 is a sectional view showing a configuration of a semiconductor device according to a fourth embodiment of the present invention.

12 is a sectional view illustrating the method of manufacturing the semiconductor device illustrated in FIG. 11;

FIG. 13 is a sectional view illustrating the method of manufacturing the semiconductor device illustrated in FIG. 11;

FIG. 14 is a sectional view illustrating the method of manufacturing the semiconductor device illustrated in FIG. 11;

FIG. 15 is a sectional view illustrating the method of manufacturing the semiconductor device illustrated in FIG. 11;

FIG. 16 is a cross-sectional view illustrating a method for manufacturing a conventional semiconductor device.

FIG. 17 is a sectional view illustrating the method of manufacturing the semiconductor device illustrated in FIG. 16;

[Explanation of symbols]

15, 15a, 29, 29a, 39, 39a Interlayer insulating film, 16, 16a, 30, 30a, 40, 40a Contact hole, 17, 31, 41 Conductor plug, 1
8, 25, 33, 43 lower electrode, 19, 26, 34,
44 dielectric film, 20, 27, 35, 45 upper electrode,
21,36 resist, 22,22a, 23,37,4
7. Polysilicon film, 24, 24a, 32, 32a, 3
2b, 42, 42a, 42b, 42c barrier metal,
28 aluminum film, 38, 38a, 48, 48a,
48b Platinum film.

Claims (10)

[Claims] 1. An interlayer insulating film formed on a semiconductor substrate, a contact hole formed in the interlayer insulating film up to the semiconductor substrate, and embedded in the contact hole and protruding from an upper surface of the interlayer insulating film. And a lower electrode covering the conductor plug and having a dome-shaped upper surface. The lower electrode, a dielectric film and an upper electrode formed on the lower electrode A semiconductor device characterized by forming a capacitor. 2. An interlayer insulating film formed on a semiconductor substrate, a contact hole formed in the interlayer insulating film up to the semiconductor substrate, a conductor plug embedded in the contact hole, and the conductor plug And a lower electrode having an upper surface formed in a dome shape by surface tension. The lower electrode, a dielectric film formed on the lower electrode, and an upper electrode form a capacitor. Semiconductor device. 3. The semiconductor device according to claim 2, wherein an upper surface of the interlayer insulating film is formed in a shape having irregularities, and a lower electrode is formed in a concave portion of the interlayer insulating film. 4. The semiconductor device according to claim 1, further comprising a barrier metal between the conductor plug and the lower electrode. 5. The semiconductor device according to claim 1, wherein the lower electrode is formed of platinum, iridium, palladium, ruthenium, or an alloy film containing these elements. 6. A step of forming an interlayer insulating film on a semiconductor substrate, a step of forming a contact hole at a desired position of the interlayer insulating film up to the semiconductor substrate, and filling the contact hole. Laminating a first conductive film, etching back the first conductive film and leaving the first conductive film only in a portion embedded in the contact hole, and etching back the interlayer insulating film. A step of projecting an upper portion of the first conductive film from an upper surface of the interlayer insulating film to make the first conductive film a conductor plug; and forming a second conductive film so as to cover the conductor plug. Stacking, and anisotropically etching back the second conductive film, exposing a part of the interlayer insulating film, and using the second conductive film as a lower electrode. Semiconductor device manufacturing Law. 7. A barrier metal is laminated between a conductor plug and a second conductive film, and a part of the interlayer insulating film is exposed when anisotropically etching back the second conductive film. 7. The method according to claim 6, further comprising the step of removing the barrier metal. 8. A step of forming an interlayer insulating film on a semiconductor substrate, a step of forming a contact hole at a desired position of the interlayer insulating film up to the semiconductor substrate, and filling the contact hole. Stacking a first conductive film and etching back the first conductive film so that the upper surface of the first conductive film is lower than the upper surface of the interlayer insulating film by a desired position; Forming a film as a conductor plug, laminating a second conductive film so as to fill the contact hole, and etching back the second conductive film so that the upper surface of the interlayer insulating film is exposed. And etching back the interlayer insulating film to form the second insulating film.
Exposing the conductive film from the upper surface of the interlayer insulating film; and heating and deforming the second conductive film, covering the conductive plug with the second conductive film and forming the second conductive film on the second conductive film. Forming a lower electrode having a dome-shaped upper surface by surface tension. 9. A step of forming an interlayer insulating film on a semiconductor substrate, a step of forming a contact hole at a desired position of the interlayer insulating film up to the semiconductor substrate, and filling the contact hole. Stacking a first conductive film and etching back the first conductive film so that the upper surface of the first conductive film is lower than the upper surface of the interlayer insulating film by a desired position; A step of using the film as a conductor plug, a step of laminating a second conductive film so as to fill the inside of the contact hole, and A step of etching back, a step of isotropically etching the interlayer insulating film, expanding a size of an upper portion of the contact hole, and forming an uneven shape on an upper surface of the interlayer insulating film; sex Etching to expose the second conductive film from the upper surface of the interlayer insulating film;
The conductive film is heated and deformed, and the second conductive film covers the conductor plug at the concave portion of the interlayer insulating film, and has a dome-shaped upper surface due to the surface tension of the second conductive film. A method of manufacturing a semiconductor device. 10. A barrier metal is laminated between a conductor plug and a second conductive film, and after exposing the second conductive film from the upper surface of the interlayer insulating film, forming a barrier metal on the second conductive film. 10. The method according to claim 8, further comprising the step of etching the barrier metal formed on the side wall.