JPH1117071A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH1117071A
JPH1117071A JP16561597A JP16561597A JPH1117071A JP H1117071 A JPH1117071 A JP H1117071A JP 16561597 A JP16561597 A JP 16561597A JP 16561597 A JP16561597 A JP 16561597A JP H1117071 A JPH1117071 A JP H1117071A
Authority
JP
Japan
Prior art keywords
linear expansion
semiconductor device
metal substrate
expansion coefficient
resin
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16561597A
Other languages
Japanese (ja)
Inventor
Toshio Ogawa
敏夫 小川
Masaaki Takahashi
正昭 高橋
Masahiro Aida
正広 合田
Noritaka Kamimura
典孝 神村
Kazuhiro Suzuki
和弘 鈴木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP16561597A priority Critical patent/JPH1117071A/en
Publication of JPH1117071A publication Critical patent/JPH1117071A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124Aluminium (Al) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1305Bipolar Junction Transistor [BJT]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1305Bipolar Junction Transistor [BJT]
    • H01L2924/13055Insulated gate bipolar transistor [IGBT]

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

PROBLEM TO BE SOLVED: To suppress the warp of a molded product and minimize the internal stress due to mounting on a heat sink to realize a high reliability and ensure a low thermal resistance, by specifying the linear expansion coefficient ratio of a metal board to a resin mold. SOLUTION: A device has a power semiconductor element 11 fixed to a lead frame 13 through a solder layer. The lead frame 13 is adhered to a metal board 19 through an insulation layer 18, the element 11 is electrically bonded by an Al wire bonding part 16 and molded with an armor resin mold 17 to form an integrated structure, and the linear thermal expansion coefficient of the resin mold 17 is adjusted relative to that of the board 11 in a ratio of 0.3:1-0.6:1 in the actual temp. range. Thus, the warp of the molded product is suppressed, and hence the internal stress due to mounting on a heat sink, etc., is minimized.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、半導体素子を含む
チップ部品が絶縁層を介して、金属基板上に搭載され、
全体が外装モールドによって保護された構造を有する樹
脂封止型半導体装置に関し、特に金属基板及びモールド
樹脂などの、該半導体装置を構成する主要構造材料間の
線膨張率差に起因する、反りを防止する手段を取ること
により、高い信頼性を実現するパワー半導体装置に関す
る。従って、本発明による半導体装置は汎用及び産業用
機器等の出力制御用インバータなどとして有効利用でき
る。
The present invention relates to a chip component including a semiconductor element mounted on a metal substrate via an insulating layer,
The present invention relates to a resin-encapsulated semiconductor device having a structure entirely protected by an exterior mold, and in particular, to prevent warpage caused by a difference in linear expansion coefficient between main structural materials constituting the semiconductor device, such as a metal substrate and a mold resin. The present invention relates to a power semiconductor device that achieves high reliability by taking measures for performing such operations. Therefore, the semiconductor device according to the present invention can be effectively used as an output control inverter for general-purpose and industrial equipment.

【0002】[0002]

【従来の技術】従来のこの種パワー半導体装置として、
公告特許公報平7−249714 号に開示される構成がある。
これは、Al基板上に導体回路を形成し、その上にパワ
ー半導体素子を搭載し、外装を、Al基板より小さい線
膨張率を有する樹脂を用いてモールド成形したものであ
る。この構造を有する半導体装置では、複数のパワー半
導体素子及びその他の部品もあわせ実装される場合が多
く、基板寸法が大きくなる。基板寸法が大きいと、わず
かな反りがあっても、それが強調されるため、該半導体
装置の成形後の充分な平坦性を実現するのは難しく、信
頼性の確保にも難があるという欠点がある。
2. Description of the Related Art As a conventional power semiconductor device of this type,
There is a configuration disclosed in Japanese Patent Publication No. 7-249714.
This is one in which a conductive circuit is formed on an Al substrate, a power semiconductor element is mounted thereon, and the exterior is molded using a resin having a linear expansion coefficient smaller than that of the Al substrate. In a semiconductor device having this structure, a plurality of power semiconductor elements and other components are often mounted together, resulting in an increase in substrate size. When the substrate size is large, even if there is a slight warpage, it is emphasized, so that it is difficult to realize sufficient flatness after molding of the semiconductor device, and it is also difficult to secure reliability. There is.

【0003】[0003]

【発明が解決しようとする課題】本発明は上記従来法の
問題点を解決し、平坦性が良好で、高信頼性のパワー半
導体装置を実現するものである。すなわち、該半導体装
置の反りはこれを構成する金属基板と、モールド樹脂と
の線膨張率のバランスによって主に決定される。ところ
が、両者の線膨張率の温度依存性には大きな差が有る。
この温度依存性を考慮して、両者の組合せを最適化する
ことによって、基板寸法の大きい半導体装置であって
も、その反り量を最小限に抑制でき、結果的に高信頼性
のパワー半導体装置を提供する。
SUMMARY OF THE INVENTION The present invention solves the above-mentioned problems of the conventional method and realizes a highly reliable power semiconductor device having good flatness. That is, the warpage of the semiconductor device is mainly determined by the balance between the coefficient of linear expansion of the metal substrate constituting the semiconductor device and the mold resin. However, there is a large difference in the temperature dependence of the coefficient of linear expansion between the two.
By optimizing the combination of the two in consideration of the temperature dependence, even if the semiconductor device has a large substrate size, the amount of warpage can be minimized, and as a result, a highly reliable power semiconductor device can be obtained. I will provide a.

【0004】[0004]

【課題を解決するための手段】上記目的を達成するため
に、本発明では次の手段をとる。
In order to achieve the above object, the present invention takes the following measures.

【0005】1.金属基板の片面に、絶縁層を介して導
体回路が形成され、該導体回路上に複数の発熱性半導体
素子が固着され、該金属基板の他の面の少なくとも一部
が実質的に外部に露出した状態で、一体の電気絶縁性外
装樹脂モールドによって保護された、複合構造を有する
半導体装置において、実用温度範囲における線膨張率の
比が、該金属基板1.0に対して該樹脂モールドが0.3
から0.6 の範囲に調節して構成された半導体装置とす
る。
[0005] 1. A conductor circuit is formed on one surface of a metal substrate via an insulating layer, a plurality of heat-generating semiconductor elements are fixed on the conductor circuit, and at least a part of another surface of the metal substrate is substantially exposed to the outside. In the semiconductor device having a composite structure protected by the integral electric insulating exterior resin mold in this state, the ratio of the coefficient of linear expansion in the practical temperature range is such that the ratio of the resin mold to the metal substrate 1.0 is zero. .3
To 0.6.

【0006】2.上記1において、前記金属基板がAl
もしくはAl合金からなり、実用温度範囲における線膨
張率が21ppm/℃から25ppm/℃の範囲にあり、かつ
前記樹脂モールドの線膨張率が8ppm/℃から14ppm/
℃の範囲に調節して構成された半導体装置とする。
[0006] 2. In the above item 1, the metal substrate may be made of Al
Alternatively, it is made of an Al alloy, has a linear expansion coefficient in a practical temperature range of 21 ppm / ° C. to 25 ppm / ° C., and has a linear expansion coefficient of 8 ppm / ° C. to 14 ppm /
The semiconductor device is configured so as to be adjusted to the range of ° C.

【0007】3.上記1において、前記金属基板がCu
もしくはCu合金からなり、実用温度範囲における線膨
張率が17ppm/℃から21ppm/℃の範囲にあり、かつ
前記樹脂モールドの線膨張率が6ppm/℃から12ppm/
℃の範囲に調節して構成された半導体装置とする。
[0007] 3. In the above item 1, the metal substrate may be made of Cu
Alternatively, the resin mold has a linear expansion coefficient of 17 ppm / ° C. to 21 ppm / ° C. in a practical temperature range, and a linear expansion coefficient of 6 ppm / ° C. to 12 ppm /
The semiconductor device is configured so as to be adjusted to the range of ° C.

【0008】図1に断面構造を示すように、この種の樹
脂封止型半導体装置の反りは、最も体積占有率の高い金
属基板と樹脂との線膨張率のバランスにより決定され
る。ところが、両者の線膨張の温度依存性には大きな差
が有り、平坦性を確保するためには製造工程における特
別な配慮が要求される。図2にAl基板の線膨張と温度
との関係を示す。ここで線膨張率αは線膨張と温度変化
との比、すなわち図2に示す直線の勾配で表される。図
3には典型的なトランスファモールド用のエポキシ系樹
脂材料のモールド成形時における収縮量と温度との関係
を示す。図中のx印が固化開始点であり、温度によっ
て、3つの領域に大別でき、それぞれ次のように定義す
る。A:化学的収縮域−液状樹脂が架橋を開始して固化
する領域。B:前期熱収縮域−ガラス転移温度(Tg)
までの熱収縮領域であり、この領域の収縮率をα2とす
る。C:後期熱収縮域−Tgより低い温度における熱収
縮領域であり、その間の収縮率をα1とする。通常α1
とα2との比は1/3とα1が小さい。これらを総合し
て、樹脂成形時の見かけの収縮率が求まる。見かけの収
縮率Aは、図3中の破線Aの勾配として得られ、液体状
態からの全収縮量が含まれる。見かけの収縮率Bは、破
線Bの勾配であり、固化終了から室温までの平均収縮量
を表す。
As shown in the sectional structure of FIG. 1, the warpage of this type of resin-encapsulated semiconductor device is determined by the balance between the linear expansion coefficients of the metal substrate having the highest volume occupancy and the resin. However, there is a great difference in the temperature dependence of the linear expansion between the two, and special consideration in the manufacturing process is required to ensure flatness. FIG. 2 shows the relationship between the linear expansion of the Al substrate and the temperature. Here, the linear expansion coefficient α is represented by the ratio between the linear expansion and the temperature change, that is, the gradient of the straight line shown in FIG. FIG. 3 shows the relationship between the amount of shrinkage and the temperature during molding of a typical epoxy resin material for transfer molding. The mark x in the figure is the solidification starting point, which can be roughly classified into three regions according to the temperature, and is defined as follows. A: Chemical shrinkage area-an area where the liquid resin starts to crosslink and solidifies. B: pre-heat shrinkage area-glass transition temperature (Tg)
The contraction rate of this region is α2. C: Late heat shrinkage region—a heat shrinkage region at a temperature lower than Tg, and the shrinkage ratio during that period is α1. Normal α1
The ratio between α1 and α2 is 1/3 and α1 is small. The apparent shrinkage at the time of resin molding is obtained by summing up these. The apparent contraction rate A is obtained as the gradient of the broken line A in FIG. 3, and includes the total contraction amount from the liquid state. The apparent shrinkage ratio B is a gradient of a broken line B and represents an average shrinkage amount from the end of solidification to room temperature.

【0009】成形後、さらに樹脂を硬化するためのポス
トキュアを施すことにより、収縮率はさらに小さくなる
傾向が有る。通常この状態における収縮率α1を単にそ
の樹脂の線膨張率もしくは収縮率と称し、ここでは前述
の収縮率と区別するために、定常収縮率と呼ぶ。
[0009] After the molding, post-curing for further curing the resin tends to further reduce the shrinkage. Usually, the shrinkage rate α1 in this state is simply referred to as the linear expansion rate or shrinkage rate of the resin, and is herein referred to as the steady shrinkage rate to distinguish it from the above-described shrinkage rate.

【0010】仮に、金属基板と、その基板の線膨張率に
等しい定常収縮率を有する樹脂とを組合せて図1に示す
形状に成形すると、金属基板面側に凸の反りが発生し、
充分な平坦性は得られない。これは、金属基板に比較し
て、樹脂の見かけの収縮率が極端に大きくなってしまう
結果と考えられる。本発明者らは、繰り返し実験の結
果、平坦性を確保するために必要な次の条件を見出し
た。それは、適用する金属基板の線膨張率αが、高くて
も樹脂の見かけの収縮率A,低くとも見かけの収縮率B
の範囲に設定することである。これを実験則に基づい
て、定常収縮率で表現すると次のようになる。すなわ
ち、金属基板の線膨張率1.0 に対して、樹脂の定常収
縮率を0.3から0.5の範囲に設定することで、上記見
かけの収縮率の条件を概ね満足できる。その条件に適合
する材料の組合せにより、成形後の充分な平坦性を有す
る成形体が得られる。
If a metal substrate and a resin having a constant contraction rate equal to the coefficient of linear expansion of the substrate are combined and formed into a shape shown in FIG. 1, a convex warpage occurs on the metal substrate surface side.
Sufficient flatness cannot be obtained. This is considered to be the result of the apparent shrinkage of the resin being extremely large compared to the metal substrate. The present inventors have found the following conditions necessary for ensuring flatness as a result of repeated experiments. That is, even if the linear expansion coefficient α of the applied metal substrate is high, the apparent contraction rate A of the resin is high, and the apparent contraction rate B is low if the linear expansion coefficient α is low.
Is set in the range. This is expressed as a steady-state contraction rate based on an experimental rule as follows. That is, by setting the steady shrinkage of the resin in the range of 0.3 to 0.5 with respect to the linear expansion coefficient of the metal substrate of 1.0, the condition of the apparent shrinkage can be almost satisfied. By a combination of materials meeting the conditions, a molded article having sufficient flatness after molding can be obtained.

【0011】一般に、単に収縮率といわれる樹脂の定常
収縮率と、見かけの収縮率には強い相関関係がある。理
由は次のようである。この種樹脂材料は、エポキシ系な
ど線膨張率の極めて高い樹脂に、熱膨張率の低いアルミ
ナ、シリカなどのフィラーを加えて材料の特性を調節し
ている。従って、両者の配合割合によって線膨張率は大
きく変動し、このように、フィラーの比率が高いほど線
膨張率は低減する。フィラーの比率で線膨張率が決定さ
れる状況は、図3中の各領域A,B及びCに共通の現象
であり、定常収縮率と見かけの収縮率はほぼ正比例する
傾向がある。
Generally, there is a strong correlation between the steady shrinkage of the resin, which is simply referred to as the shrinkage, and the apparent shrinkage. The reason is as follows. This kind of resin material adjusts the characteristics of the material by adding a filler such as alumina or silica having a low coefficient of thermal expansion to a resin having a very high coefficient of linear expansion such as an epoxy resin. Accordingly, the coefficient of linear expansion greatly varies depending on the blending ratio of the two, and as described above, the coefficient of linear expansion decreases as the ratio of the filler increases. The situation where the coefficient of linear expansion is determined by the ratio of the filler is a phenomenon common to each of the regions A, B and C in FIG. 3, and the steady-state shrinkage and the apparent shrinkage tend to be almost directly proportional.

【0012】[0012]

【発明の実施の形態】以下、本発明を実施例によってさ
らに詳細に説明するが、本発明はこれらに限定されな
い。
DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in more detail with reference to Examples, but the present invention is not limited thereto.

【0013】実施例1 図1に本発明の一実施例による半導体装置の断面構成図
を示す。例えばIGBT(Insulated Gate Bipolar Transis
tor )などのパワー半導体素子11が半田層12を介し
てリードフレーム13上に固着される。該リードフレー
ム13は絶縁層18を介して金属基板19に接着され、
素子11はアルミニウムのワイヤボンデング部16によ
り電気的に接合され、系全体が外装樹脂モールド17に
より一体成型された構造である。金属基板19は純度9
9.9%、寸法70mm×40mm×2mmのAl板を用い
た。この基板の線膨張率は23.5ppm/℃である。樹脂
材料は、エポキシ系樹脂にシリカ粉末を適当量添加して
線膨張率を調節した。表1にこれら樹脂材料の収縮率測
定結果を示す。測定は型中にセットした円柱状のサンプ
ル長さの温度変化を、変位検出用ロッドを介して直接測
定した。
Embodiment 1 FIG. 1 is a sectional view of a semiconductor device according to an embodiment of the present invention. For example, IGBT (Insulated Gate Bipolar Transis
A power semiconductor element 11 such as tor) is fixed on the lead frame 13 via the solder layer 12. The lead frame 13 is bonded to a metal substrate 19 via an insulating layer 18,
The element 11 has a structure in which it is electrically connected by an aluminum wire bonding portion 16 and the whole system is integrally molded by an exterior resin mold 17. Metal substrate 19 has a purity of 9
An 9.9% Al plate having dimensions of 70 mm × 40 mm × 2 mm was used. The coefficient of linear expansion of this substrate is 23.5 ppm / ° C. As the resin material, a linear expansion coefficient was adjusted by adding an appropriate amount of silica powder to an epoxy resin. Table 1 shows the measurement results of the shrinkage rates of these resin materials. In the measurement, the temperature change of the length of the cylindrical sample set in the mold was directly measured via a displacement detection rod.

【0014】素子11及びリードフレーム13などを装
着した金属基板19を金型内にセットし、トランスファ
モールド法により180℃で成形した。成形寸法は、図
1中のa寸法を1mm、t寸法を6mmとした。成形後、さ
らに180℃5時間のポストキュアを施して金属基板1
9の露出面の反り量を評価した。評価にあたっては、対
角線上に連続的に表面の変位を測定し、最も大きい値を
反り量とした。金属基板側に凸の変位を正、反対に樹脂
側に凸を負の反りと表現した。
The metal substrate 19 on which the element 11 and the lead frame 13 were mounted was set in a mold, and was molded at 180 ° C. by a transfer molding method. The molding dimension in FIG. 1 was 1 mm and the dimension t was 6 mm. After molding, post-curing is further performed for 5 hours at 180 ° C.
9 was evaluated for the amount of warpage of the exposed surface. In the evaluation, the displacement of the surface was measured continuously on a diagonal line, and the largest value was defined as the amount of warpage. Displacement convex on the metal substrate side is expressed as positive, and conversely, convex on the resin side is expressed as negative warpage.

【0015】負の反りは、該半導体装置と放熱部材との
間に空隙を生じ、熱抵抗が上昇してしまうので好ましく
ない。一方、正の反りが大きいと、放熱部材に取り付け
る際に内部応力が上昇し、充分な信頼性が得られない。
反りの範囲は、実用的に−20μmから+80μmの範囲
が好ましい。表1の結果より、本実施例での好ましい定
常収縮率は8.4ppm/℃−11.5ppm/℃の範囲にある
ことがわかる。
[0015] Negative warpage is not preferable because a gap is formed between the semiconductor device and the heat radiating member, and the thermal resistance increases. On the other hand, if the positive warpage is large, the internal stress increases when attaching to the heat dissipation member, and sufficient reliability cannot be obtained.
The range of warpage is practically preferably in the range of −20 μm to +80 μm. From the results shown in Table 1, it can be seen that the preferable steady-state shrinkage rate in this example is in the range of 8.4 ppm / ° C to 11.5 ppm / ° C.

【0016】[0016]

【表1】 [Table 1]

【0017】実施例2 金属基板19として、純度99.5% のCu板を用い、
その他については基板寸法も含め、実施例1と同様の方
法によってサンプルを作製し、同様に、基板面の反りを
測定した。金属基板19の線膨張率は17.7ppm/℃
である。
Example 2 As a metal substrate 19, a Cu plate having a purity of 99.5% was used.
Otherwise, including the dimensions of the substrate, a sample was prepared in the same manner as in Example 1, and the warpage of the substrate surface was measured in the same manner. The coefficient of linear expansion of the metal substrate 19 is 17.7 ppm / ° C.
It is.

【0018】測定結果を表2に示す。これより、Cu系
基板を適用する場合には、モールド樹脂17の好ましい
範囲は6.8ppm/℃から8.4ppm/℃であることがわか
る。 実施例3 実施例1と同様の方法によってサンプルを作製し、同様
に、基板面の反りを測定した。ここでは金属基板19の
寸法に着目し、反りとの関係を評価した。測定結果を図
4に示す。反り量は基板寸法の増加につれて上昇する。
このため、反りの好ましい範囲は−20μmから+80
μmであり、基板寸法が大きいほど樹脂17の線膨張率
はより狭い範囲に設定する必要があり、逆に小さい基板
では適用可能な樹脂の線膨張率適用範囲は広くなること
が示される。
Table 2 shows the measurement results. From this, it can be seen that when a Cu-based substrate is applied, the preferable range of the mold resin 17 is 6.8 ppm / ° C. to 8.4 ppm / ° C. Example 3 A sample was prepared in the same manner as in Example 1, and the warpage of the substrate surface was measured in the same manner. Here, attention was paid to the dimensions of the metal substrate 19, and the relationship with the warpage was evaluated. FIG. 4 shows the measurement results. The amount of warpage increases as the substrate size increases.
For this reason, the preferable range of the warpage is from −20 μm to +80.
It is shown that the linear expansion coefficient of the resin 17 needs to be set in a narrower range as the size of the substrate is larger, and conversely, the applicable range of the linear expansion coefficient of the applicable resin is wider with a smaller substrate.

【0019】実施例4 実施例1と同様の方法によってサンプルを作製し、同様
に、基板面の反りを測定した。ここでは成形体厚さ、t
寸法に着目し、反りとの関係を評価した。測定結果を図
5に示す。反り量はt寸法の増加につれて若干上昇する
傾向がある。
Example 4 A sample was prepared in the same manner as in Example 1, and the warpage of the substrate surface was measured in the same manner. Here, the thickness of the molded body, t
Focusing on dimensions, the relationship with warpage was evaluated. FIG. 5 shows the measurement results. The amount of warpage tends to increase slightly as the t dimension increases.

【0020】実施例5 実施例1と同様の手順によって、図6に示す回路パター
ンを有するコンバータ及びインバータ複合パワー半導体
装置を作製した。この装置を三相インダクションモータ
に直接取り付けて両者を一体化した。電気回路のブロッ
ク図を図7に示す。本発明による半導体装置は基板の反
りが小さいので、熱抵抗が低く、かつ信頼性が高いの
で、厳しい環境で使用されるモータ、例えば電気自動
車、各種ポンプ及び搬送用などのモータとの一体化が可
能となる。このようにインバータとモータとを一体化す
ることにより、それぞれの装置全体としての小型化、高
信頼性化を実現出来る。
Example 5 By the same procedure as in Example 1, a converter and inverter composite power semiconductor device having the circuit pattern shown in FIG. 6 was manufactured. This device was directly attached to a three-phase induction motor to integrate them. FIG. 7 shows a block diagram of the electric circuit. Since the semiconductor device according to the present invention has a small warpage of the substrate, low thermal resistance and high reliability, it can be integrated with a motor used in a severe environment, for example, an electric vehicle, various pumps, and a motor for transportation. It becomes possible. By integrating the inverter and the motor in this way, it is possible to realize the miniaturization and high reliability of each device as a whole.

【0021】[0021]

【発明の効果】以上説明したように、本発明によれば、
金属基板19と樹脂モールド17との線膨張率比を特定
することによって、成形後の成形体の反りを制御できる
ので、放熱部材への取付けによる内部応力を最小限に抑
制して、高信頼性を実現すると共に、低熱抵抗を確保す
る効果がある。
As described above, according to the present invention,
By specifying the linear expansion coefficient ratio between the metal substrate 19 and the resin mold 17, the warpage of the molded body after molding can be controlled, so that the internal stress due to attachment to the heat radiating member is minimized, and high reliability is achieved. And the effect of ensuring low thermal resistance.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の一実施例によるパワー半導体装置の断
面構成図。
FIG. 1 is a sectional configuration diagram of a power semiconductor device according to an embodiment of the present invention.

【図2】金属基板の線膨張温度依存性。FIG. 2 shows the linear expansion temperature dependence of a metal substrate.

【図3】モールド樹脂の線膨張温度依存性。FIG. 3 shows the linear expansion temperature dependency of a mold resin.

【図4】成形体の反り量と基板寸法との関係。FIG. 4 shows the relationship between the amount of warpage of a molded article and the dimensions of a substrate.

【図5】成形体の反り量と成形体厚さ寸法との関係。FIG. 5 shows the relationship between the amount of warpage of a molded article and the thickness of the molded article.

【図6】本発明の一実施例によるインバータモジュール
の回路パターン図。
FIG. 6 is a circuit pattern diagram of an inverter module according to an embodiment of the present invention.

【図7】本発明の一実施例によるインバータ装置の回路
ブロック図。
FIG. 7 is a circuit block diagram of an inverter device according to one embodiment of the present invention.

【符号の説明】[Explanation of symbols]

11…半導体素子、11a…整流ダイオード、11b…
IGBT、11c…フリーホイールダイオード、12…
半田、13…リードフレーム、13a…主回路系端子、
13b…制御系端子、16…ワイヤボンデング部、17
…外装樹脂モールド、19…金属基板、25…サーミス
タ、26…シャント抵抗、31…コンバータ部、32…
インバータ部、33…放熱部。
11 semiconductor element, 11a rectifier diode, 11b
IGBT, 11c ... freewheel diode, 12 ...
Solder, 13: Lead frame, 13a: Main circuit terminal,
13b: Control system terminal, 16: Wire bonding part, 17
... exterior resin mold, 19 ... metal substrate, 25 ... thermistor, 26 ... shunt resistor, 31 ... converter part, 32 ...
Inverter part, 33 ... heat radiation part.

───────────────────────────────────────────────────── フロントページの続き (72)発明者 神村 典孝 茨城県日立市大みか町七丁目1番1号 株 式会社日立製作所日立研究所内 (72)発明者 鈴木 和弘 茨城県日立市大みか町七丁目1番1号 株 式会社日立製作所日立研究所内 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Noritaka Kamimura 7-1-1, Omika-cho, Hitachi City, Ibaraki Prefecture Inside Hitachi Research Laboratory, Hitachi, Ltd. (72) Kazuhiro Suzuki 7-1-1, Omika-cho, Hitachi City, Ibaraki Prefecture No. 1 Inside the Hitachi Research Laboratory, Hitachi, Ltd.

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】金属基板の片面に、絶縁層を介して導体回
路が形成され、該導体回路上に複数の発熱性半導体素子
が固着され、該金属基板の他の面の少なくとも一部が実
質的に外部に露出した状態で、一体の電気絶縁性外装樹
脂モールドによって保護された、複合構造を有する半導
体装置において、実用温度範囲における線膨張率の比
が、該金属基板1.0に対して該樹脂モールドが0.3か
ら0.6 の範囲に調節して構成されたことを特徴とする
半導体装置。
1. A conductive circuit is formed on one surface of a metal substrate via an insulating layer, a plurality of heat-generating semiconductor elements are fixed on the conductive circuit, and at least a part of another surface of the metal substrate is substantially formed. In a semiconductor device having a composite structure, which is protected by an integral electrically insulating exterior resin mold while being exposed to the outside, the ratio of the coefficient of linear expansion in a practical temperature range is higher than that of the metal substrate 1.0. A semiconductor device, wherein the resin mold is configured to be adjusted in a range of 0.3 to 0.6.
【請求項2】請求項1において、前記金属基板がAlも
しくはAl合金からなり、実用温度範囲における線膨張
率が21ppm/℃から25ppm/℃の範囲にあり、かつ前
記樹脂モールドの線膨張率が8ppm/℃から14ppm/℃
の範囲に調節して構成されたことを特徴とする半導体装
置。
2. The resin substrate according to claim 1, wherein said metal substrate is made of Al or an Al alloy, has a linear expansion coefficient in a practical temperature range of 21 ppm / ° C. to 25 ppm / ° C., and has a linear expansion coefficient of said resin mold. 8ppm / ℃ to 14ppm / ℃
A semiconductor device characterized in that the semiconductor device is configured to be adjusted in the range of:
【請求項3】請求項1において、前記金属基板がCuも
しくはCu合金からなり、実用温度範囲における線膨張
率が17ppm/℃から21ppm/℃の範囲にあり、かつ前
記樹脂モールドの線膨張率が6ppm/℃から12ppm/℃
の範囲に調節して構成されたことを特徴とする半導体装
置。
3. The method according to claim 1, wherein the metal substrate is made of Cu or a Cu alloy, has a linear expansion coefficient in a practical temperature range of 17 ppm / ° C. to 21 ppm / ° C., and has a linear expansion coefficient of the resin mold. 6ppm / ℃ to 12ppm / ℃
A semiconductor device characterized in that the semiconductor device is configured to be adjusted in the range of:
JP16561597A 1997-06-23 1997-06-23 Semiconductor device Pending JPH1117071A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16561597A JPH1117071A (en) 1997-06-23 1997-06-23 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16561597A JPH1117071A (en) 1997-06-23 1997-06-23 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH1117071A true JPH1117071A (en) 1999-01-22

Family

ID=15815738

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16561597A Pending JPH1117071A (en) 1997-06-23 1997-06-23 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH1117071A (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6903457B2 (en) * 2002-11-13 2005-06-07 Mitsubishi Denki Kabushiki Kaisha Power semiconductor device
US6979909B2 (en) 2001-02-09 2005-12-27 Mitsubishi Denki Kabushiki Kaisha Semiconductor device and method of manufacturing same
JP2006100752A (en) * 2004-09-30 2006-04-13 Sanyo Electric Co Ltd Circuit arrangement and its manufacturing method
US7207187B2 (en) 2002-04-26 2007-04-24 Denso Corporation Inverter-integrated motor for an automotive vehicle
US20120161309A1 (en) * 2010-12-28 2012-06-28 Mitsubishi Electric Corporation Semiconductor package
JP2014049516A (en) * 2012-08-30 2014-03-17 Mitsubishi Electric Corp Cooling structure of shunt resistor and inverter device using the same
US11322430B2 (en) 2017-07-28 2022-05-03 Mitsubishi Electric Corporation Semiconductor device and semiconductor module with a highest portion of a terminal lower than a highest portion of the mold sealing resin

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6979909B2 (en) 2001-02-09 2005-12-27 Mitsubishi Denki Kabushiki Kaisha Semiconductor device and method of manufacturing same
US7045907B2 (en) 2001-02-09 2006-05-16 Mitsubishi Denki Kabushiki Kaisha Semiconductor device and method of manufacturing same
US7207187B2 (en) 2002-04-26 2007-04-24 Denso Corporation Inverter-integrated motor for an automotive vehicle
US6903457B2 (en) * 2002-11-13 2005-06-07 Mitsubishi Denki Kabushiki Kaisha Power semiconductor device
JP2006100752A (en) * 2004-09-30 2006-04-13 Sanyo Electric Co Ltd Circuit arrangement and its manufacturing method
US20120161309A1 (en) * 2010-12-28 2012-06-28 Mitsubishi Electric Corporation Semiconductor package
JP2014049516A (en) * 2012-08-30 2014-03-17 Mitsubishi Electric Corp Cooling structure of shunt resistor and inverter device using the same
US11322430B2 (en) 2017-07-28 2022-05-03 Mitsubishi Electric Corporation Semiconductor device and semiconductor module with a highest portion of a terminal lower than a highest portion of the mold sealing resin

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