JPH11168325A - Signal generation circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To effectively suppress distortion of an obtained signal waveform at the time of successively reading data stored in a memory means from there with a prescribed time interval, executing D/A conversion to the read data and obtaining the signal waveform. SOLUTION: This circuit is provided with a memory part 11 storing signal data, a latch part 14 for holding time interval data for indicating a data read time interval, a read timing signal generation part 15 for generating read timing signals corresponding to the time interval data from the latch part 14, performing accumulation for the difference from the data read time interval of the cycle of the read timing signals and prolonging the cycle of the read timing signals for one cycle of clock pulse signals when the result of the accumulation exceeds one cycle of the clock pulse signals, a read address signal formation part 16 for reading the signal data from the memory part 11 corresponding to the read timing signals and a D/A conversion part 18 for executing the D/A conversion to the signal data read from the memory part 11 and obtaining signals to be formed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] The invention described in the claims of the present application reads out data at a predetermined timing from a memory means storing data relating to a predetermined signal, and performs a predetermined reading based on the read data. The present invention relates to a signal generating circuit for obtaining a signal having a waveform corresponding to the waveform of the above signal.

[0002]

2. Description of the Related Art An image display monitor for displaying an image represented by a video signal is widely used for various purposes such as information transmission and monitoring. In such an image display monitor device, the displayed image is liable to be distorted, and when the displayed image is distorted, an image distortion correction signal is supplied separately from the video signal representing the image. Thus, the distortion of the displayed image is corrected.

In the field of a correction signal forming device for forming such an image distortion correction signal, a signal to be formed,
For example, signal data relating to the waveform of the image distortion correction signal is stored in the memory means, and the signal data is sequentially read out from the memory means at a time interval set according to the number of data per cycle of the signal to be formed. Digital / analog conversion (D / A conversion) on output signal data
It has been proposed to use a signal generation circuit that generates a signal to be formed by applying the following. Such a signal generating circuit includes a digital circuit constituting a part for forming a timing signal for reading signal data from the memory means, a read address signal, and the like. The digital circuit operates according to a clock pulse signal having a predetermined frequency.

The reading of signal data from the memory means in the digital circuit included in the signal generating circuit as described above is usually preferably performed at equal time intervals within each cycle of the signal to be formed. Therefore, the data read time interval at the time of reading the signal data from the memory means is determined by setting the cycle time of the signal to be formed as one of the signals to be formed stored in the memory means.
This is set as a value obtained by dividing the number of signal data per cycle by 1 minus the number.

For example, the frequency fx of the signal to be formed
Is 31 kHz and the number of signal data per cycle stored in the memory means is 33, the cycle Tx of the signal to be formed is 1 / fx = 32.258 μsec. For the time interval, the period Tx is 32
By dividing, Tx / 32 = 32.258 / 32
Set as μs.

[0006]

In the above-mentioned signal generating circuit, a digital circuit involved in reading out signal data from the memory means operates according to a unique clock pulse signal. Such a clock pulse signal is not guaranteed to be in a synchronous relationship with a signal to be formed related to signal data stored in the memory means. In many cases, the clock pulse signal is not related to signal data stored in the memory means. It has an asynchronous relationship with the signal to be performed.

A clock pulse signal in a digital circuit involved in reading signal data from the memory means is:
As described above, when there is an asynchronous relationship with a signal to be formed related to the signal data stored in the memory means,
In each cycle of a signal to be formed, a deviation occurs between a data read time interval set to read signal data from the memory means at equal time intervals and an actual data read time interval. Become.

For example, if the frequency fk of a clock pulse signal in a digital circuit involved in reading signal data from the memory means is 25 MHz, the period Tk is 1 / fk = 40 nsec. The time interval, ie, Tx / 32 = 32.258 / 32μ
The second is (32.258 ×
10 ³ ) / (32 × 40) = 25.201 cycles.

However, in a digital circuit that operates in response to a clock pulse signal having a frequency of 25 MHz, a timing corresponding to a cycle including a fraction of 25.201 cannot be taken. Therefore, the actual data read time interval is set to be 0.2 cycles of the clock pulse signal with respect to the set data read time interval.
A "shift" of 01 cycle time = 8.04 nsec has occurred.

The reading of signal data from the memory means in each cycle of a signal to be formed is performed at a data reading time interval (equal time interval) in which a "shift" has occurred with respect to the set data reading time interval. When performed, the read timing of each signal data read in each cycle of the signal to be formed gradually increases in “shift” from the timing according to the set data read time interval. Such a “shift” may be relatively large for signal data that is read last in each cycle of a signal to be formed. For example,
In the above case, the “shift” in the read timing of the signal data read last in each cycle of the signal to be formed is 0.201 cycle time of the clock pulse signal × 3
2 = 6.432 cycle time = 257.28 nsec.

The "shift" in the read timing when reading the signal data from the memory means is caused by the D / A conversion of the signal data read from the memory means and the signal to be formed. When the waveform is distorted and the "shift" of the read timing is relatively large, the signal to be formed obtained by subjecting the signal data read from the memory means to D / A conversion is obtained. Waveform distortion becomes non-negligible.

In view of the above, the invention described in any one of claims 1 to 7 in the claims of the present application provides a digital circuit by means of a memory means storing data relating to a signal to be formed. , The stored data are sequentially read out at time intervals set according to the number of data per cycle of the signal to be formed, and the read data or the data obtained accordingly is
In performing the / A conversion to obtain a signal to be formed, the digital circuit is read from the memory means even when the digital circuit operates in response to a clock pulse signal having an asynchronous relationship with the signal to be formed. Provided is a signal generation circuit that effectively suppresses a waveform distortion of a signal to be formed, which is obtained by performing D / A conversion on the data obtained or data obtained in accordance with the data.

[0013]

According to the present invention, there is provided a signal generating circuit according to the first or second aspect of the present invention, wherein a memory means stores signal data relating to a waveform of a signal to be formed. And data holding means for holding time interval data representing a data read time interval set according to the number of data per cycle of a signal to be formed, and a clock pulse signal having an asynchronous relationship with the signal to be formed , And generates a read timing signal corresponding to the time interval data obtained from the data holding means, and performs the accumulation of the difference between the cycle of the read timing signal and the data read time interval. When the period of the clock pulse signal exceeds one period, the period of the read timing signal is extended by one period of the clock pulse signal. A signal reading means for supplying a read address signal to the memory means for each read timing signal obtained from the timing signal generating means, and reading signal data from the memory means; and a signal read from the memory means by the data reading means. D / A conversion means for performing D / A conversion on data to obtain a signal to be formed.

According to a third aspect of the present invention, there is provided a signal generation circuit, comprising: a first memory unit storing signal data relating to a waveform of a signal to be formed; A second memory means for storing time interval data, which is obtained according to the number of data per cycle of a signal to be formed, and indicates a total data read time interval within the cycle of the signal to be formed;
A timing signal generating means for performing a count operation in accordance with each time interval data read from the memory means, and generating a read timing signal for each count operation; and a read address for each read timing signal obtained from the timing signal generating means. A signal is supplied to the first memory means, the signal data is read from the first memory means, and the time interval data is read from the second memory means. The data read means reads the time interval data from the first memory means. D / A conversion means for performing D / A conversion on signal data to be obtained to obtain a signal to be formed.

Further, in the signal generation circuit according to any one of claims 5 to 7 in the claims of the present application, the level increase and decrease are equal in each cycle of the signal to be formed. Memory means for storing time interval data indicating a time interval between signal timings determined by performing the time axis division, and a first timing signal and a second timing corresponding to the time interval data read from the memory means Timing signal generating means for generating a signal; data reading means for supplying a read address signal to the memory means for each first timing signal obtained from the timing signal generating means; and reading time interval data from the memory means; Signal data by adding or subtracting for each second timing signal obtained from the means. That the signal data forming means, and signal to the signal data obtained from the data forming means to obtain a signal to be formed by performing a D / A converter D / A converter.

In the signal generating circuit according to the first or second aspect of the present invention configured as described above, the timing of reading signal data from the memory means is determined. The timing signal generating means for generating the read timing signal which operates in response to the clock pulse signal having an asynchronous relationship with the signal to be formed operates according to the time interval data obtained from the data holding means. The difference between the period of the generated read timing signal and the data read time interval represented by the time interval data is accumulated, and when the accumulated result exceeds one cycle of the clock pulse signal, the cycle of the read timing signal is set to the clock pulse. It is lengthened by one cycle of the signal. This suppresses an increase in the "shift" of the read timing of the signal data from the memory means with respect to the read timing based on the data read time interval represented by the time interval data, and adds D / D to the signal data read from the memory means. Waveform distortion of a signal to be formed, which is obtained by performing the A conversion, is effectively suppressed.

In the signal generating circuit according to the third or fourth aspect of the present invention, the signal generation circuit is determined according to the number of data per cycle of a signal to be formed. A second memory means for storing time interval data indicating a total data read time interval within a cycle of a signal to be formed;
Timing signal generating means for generating a read timing signal for determining the read timing of the signal data from the memory means performs a count operation in accordance with each time interval data read from the second memory means, and performs the count operation. A read timing signal is generated every time. As a result, there is no increase in the "shift" of the read timing of the signal data from the first memory means with respect to the read timing based on the data read time interval represented by the time interval data. Waveform distortion of a signal to be formed, which is obtained by performing D / A conversion on the output signal data, is effectively suppressed.

Further, in the signal generation circuit according to any one of the fifth to seventh aspects of the present invention, the level of the signal to be formed is increased or decreased within each period. And memory means for storing time interval data indicating a time interval between signal timings determined by dividing the time axis so that the time intervals are made equal to each other. A first timing signal and a second timing signal which respectively determine a read timing and a timing at which signal data is obtained from the signal data forming means are generated as corresponding to each time interval data read from the memory means. Thereby, the timing at which the signal data is obtained from the signal data forming means is
There is no increase in the “shift” with respect to the signal timing having the time interval represented by the time interval data, and the signal data obtained from the signal data forming means is subjected to D / A conversion and should be formed. Signal waveform distortion is effectively suppressed.

[0019]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows an example of a signal generating circuit according to the invention described in claim 1 or 2 of the present application.

In the example shown in FIG. 1, the memory unit 1
1, the memory unit 11 stores signal data DS relating to the waveform of a signal to be formed. The signal to be formed has a predetermined frequency fs. The frequency fs is, for example, 31 kHz, and the period Ts is 1 / fs = 32.258 μsec. The signal data DS stored in the memory unit 11 is obtained by dividing the period Ts of a signal to be formed into a predetermined number, for example,
There are 33.

In the example shown in FIG. 1, a microcomputer 12 is provided. The microcomputer 12 converts the signal data DS stored in the memory unit 11 into a signal to be formed. A data read time interval for reading the cycle Ts as a section is calculated, and time interval data DRI representing the calculated data read time interval is generated. As shown in FIG. 2, reading of the signal data DS from the memory unit 11 based on the data reading time interval is performed within each cycle Ts of the signal SO to be formed, by a predetermined number corresponding to the cycle Ts. It is assumed that all of the signal data DS is read out and performed at equal time intervals TI.

Therefore, when the period Ts of the signal to be formed is 1 / fs = 32.258 μsec and the predetermined number of signal data DS corresponding to the period Ts is 33, the data read time The interval is Ts / 32 = 32.25
The time interval data DRI is calculated as 8/32 μsec.
Represents a data read time interval of Ts / 32 = 32.258 / 32 μsec. The time interval data DRI obtained from the microcomputer 12 is supplied to the memory control unit 13 and held by the latch unit 14 in the memory control unit 13.

The memory control section 13 is provided with a read timing signal generating section 15, and the read timing signal generating section 15 is supplied with a read trigger pulse signal PTR. Each time the read trigger pulse signal PTR is supplied, the read timing signal generating section 15 reads the signal data DS from the memory section 11 in each cycle Ts of the signal to be formed in accordance with the read trigger pulse signal PTR. Of the readout timing signal SRT is started, and 33 readout timing signals SRT are formed to read out 33 signal data DS.

The formation of the read timing signal SRT by the read timing signal generating unit 15 is performed under the condition that the time interval data DRI held by the latch unit 14 is supplied to the read timing signal generating unit 15 and the read timing is generated. The signal generator 15 converts the read timing signal SRT into the time interval data DR based on the time interval data DRI.
It is formed as having a cycle corresponding to the data read time interval represented by I.

At this time, the read timing signal generator 15
Is a digital circuit,
For example, it operates in response to a clock pulse signal CLK having a predetermined frequency of 25 MHz and being asynchronous with a signal to be formed. As described above, the data read time interval represented by the time interval data DRI is Ts /
32 = 32.258 / 32 μsec. Since the frequency of the clock pulse signal CLK is 25 MHz, the cycle thereof is 1/25 MHz = 40 nsec. Therefore, the data read time interval represented by the time interval data DRI is clock For the pulse signal CLK, (32.258 × 10
³ /32×40)=25.201 corresponding to the period.

Since the data read time interval represented by time interval data DRI corresponds to a cycle including a fraction of clock pulse signal CLK, read timing signal SRT formed in read timing signal generating section 15 The period is represented by a data read time interval Ts / 32 = 32.258 / represented by the time interval data DRI.
It cannot be the same as 32 μsec. Basically, for example, 25 cycles = 4 for the clock pulse signal CLK
0 n seconds × 25 = 1 μs. Therefore, the basic period of the read timing signal SRT is 25.201-25 = 25.201-25 for the clock pulse signal CLK with respect to the data read time interval represented by the time interval data DRI.
0.201 cycle = 8.04 nsec.

Thus, the read timing signal generating section 15 sets the read timing signal to set the basic cycle to 25 cycles of the clock pulse signal CLK = 40 ns × 25 = 1 μsec in accordance with the read trigger pulse signal PTR. S
RT formation is started and 33 read timing signals SR
T will be formed. At this time, every time the read timing signal generating section 15 forms the read timing signal SRT, the read timing signal generating section 15 "shifts" from the data read time interval represented by the time interval data DRI of the basic cycle, that is, 0. 201 cycles = 8.04
n seconds are accumulated, and the accumulated result is the clock pulse signal C
When LK exceeds one cycle, the read timing signal S
The period of RT is increased by one period for the clock pulse signal CLK. For example, the period of 25 periods for the clock pulse signal CLK = 40 ns × 25 = 1 μsec is changed to 26 for the clock pulse signal CLK.
Period = 40 nsec × 26 = 1.04 μsec.

Thus, each read timing signal SRT
Is obtained, the "deviation" from the time set by the sum of the data read time intervals represented by the time interval data DRI is suppressed within one cycle of the clock pulse signal CLK = 40 nsec.

In this way, the read timing signal SRT obtained from the read timing signal generator 15 is supplied to the read address signal generator 16. The read address signal forming section 16 forms a read address signal SAD representing an address which sequentially advances each time the read timing signal SRT is supplied from the read timing signal generating section 15. Further, the read address signal forming section 16 supplies the formed read address signal SAD to the memory section 11,
Thereby, the read address signal S in the memory unit 11 is
The signal data DS is read from the address represented by AD.

Therefore, the read address signal forming section 16
This means that data reading means for reading the signal data DS from the memory unit 11 is formed. Then, the memory unit 11
Thereafter, the signal data DS stored therein is read out every time the readout timing signal SRT is sequentially obtained from the readout timing signal generator 15.

The signal data DS read from the memory unit 11 is temporarily held by the latch unit 17 and then stored in the D / A
It is supplied to the conversion unit 18. The D / A conversion unit 18 performs D / A conversion on the signal data DS from the latch unit 17, thereby forming a signal SO to be formed. Therefore,
From the D / A converter 18, a signal SO to be formed is obtained for each cycle.

FIG. 3 shows a specific example of the structure of the read timing signal generator 15 shown in FIG. In the specific configuration example shown in FIG. 3, based on the time interval data DRI, the data read time interval represented by the time interval data DRI, that is, 25.
The integer part (25) and the decimal part (0.201) of the 201 periods are denoted by I and S, respectively, and the value 32-I =
Data p representing 32-25 = 7 and value S = 0.20
Data q representing 1 is set.

Data (p) representing the value 7-1 = 6 is directly obtained by the subtraction unit 22 for subtracting the value 1 from the data (p
-1) and supplied to the data selection unit 21. First, the data selection unit 21 is placed in a state of selecting the data p, and the data p
Supplied to

Each time the data p is supplied, the counter 23 counts the clock pulse signal CLK by 32− (the value represented by the data p) = 32−7 = 25. The signal is transmitted as a read timing signal SRT.

Further, in the specific configuration example shown in FIG. 3, data q is supplied to the data adding unit 24. Each time the data q is supplied, the data adding unit 24 outputs a value representing the data q. S = 0.201 is accumulated, and a value S = 0.20 representing the data q from the data adding unit 24
The accumulated data DSM representing the accumulated result of 1 is obtained.
The accumulated data DSM is supplied to the latch unit 25. The latch unit 25 supplies the accumulated data DSM every time the read timing signal SRT sent from the counter 23 is supplied.
The SM is held, and the held accumulated data DSM is supplied to the data adder 24.

When the cumulative result represented by the cumulative data DSM obtained in the data adder 24 exceeds the value 1, the data adder 24 changes the control data DD, which previously represents "0", to "1". The data is sent out to be represented and supplied to the data selection unit 21. If the control data DD indicates “1”, the cumulative result represented by the cumulative data DSM is reduced by one.

The data selecting section 21 is switched from a state of selecting data p to a state of selecting data (p-1) in accordance with the control data DD representing "1". As a result, the data (p−1) is supplied to the counter 23 through the data selector 21.

Counter 2 supplied with data (p-1)
3 outputs the clock pulse signal CLK to 32- (data (p
-1) is counted) = 32-6 = 26. Therefore, the count of the clock pulse signal CLK corresponding to the data (p−1) in the counter 23 is increased by 1 from the count 25 of the clock pulse signal CLK corresponding to the data p to 26. Then, when the counting of the clock pulse signal CLK is completed, the counter 23 sends out the count output signal as the read timing signal SRT. Thereby, the cycle of read timing signal SRT is lengthened by one cycle for clock pulse signal CLK.

FIG. 4 shows an example of a signal generating circuit according to the third or fourth aspect of the present invention.

In the example shown in FIG. 4, the memory unit 11, the same as that provided in the example shown in FIG.
A latch unit 17 and a D / A conversion unit 18 are provided;
Duplicate descriptions for them are omitted.

In the example shown in FIG. 4, a memory unit 31 different from the memory unit 11 is provided. In the memory unit 31, the signal data DS stored in the memory unit 11 is stored. A plurality of time interval data DRIM, each representing a total data read time interval, for reading out a period Ts of a signal to be formed as a section is stored.

The plurality of time interval data DRIM stored in the memory unit 31 are sequentially read out and read out from the memory control unit 32.
And a read timing signal SRT 'corresponding to the time interval data DRIM is formed in the memory control unit 32. The memory control unit 32 is also a digital circuit and has a frequency of, for example, 25 MHz. It operates according to the pulse signal CLK.

Therefore, the period Ts of the signal to be formed
Is 1 / fs = 32.258 μsec and the predetermined number of signal data DS corresponding to the cycle Ts is 33, and the data read time interval is 32 per cycle Ts.
And these 32 data read time intervals correspond to each cycle of the read timing signal SRT sent from the read timing signal generator 15 in the example shown in FIG. Signal CLK
Of the clock pulse signal CLK is equivalent to 25 periods = 1 μsec and 26 cycles of the clock pulse signal CLK is equivalent to 1.04 μsec.

Thus, the memory unit 31 includes one corresponding to 25 cycles of the clock pulse signal CLK = 1 μsec and one corresponding to 26 cycles = 1.04 μsec of the clock pulse signal CLK. Thirty-two time interval data DRIMs representing the thirty-two data read time intervals are stored so as to be read out in a preset order.

Under these circumstances, in the memory control section 32, when the read trigger pulse signal RTR is supplied to the address counter 33, the address counter 33 generates address data DAD representing the initial address in the memory section 31. Are supplied to the memory unit 31. Thereby, the first time interval data DRIM is read from the memory unit 31 and supplied to the counter 34 in the memory control unit 32. The counter 34 counts the clock pulse signal CLK in accordance with the data read time interval represented by the first time interval data DRIM,
When the count ends, the read timing signal SRT '
Is sent.

The read timing signal SRT 'obtained from the counter 34 is supplied to a read address signal forming section 35. The read address signal forming unit 35 forms a read address signal SAD representing an address according to the read timing signal SRT ′ from the counter 34, and supplies the formed read address signal SAD to the memory unit 11, thereby forming a memory. The signal data DS is read from the address represented by the read address signal SAD in the section 11.

At the same time, the read timing signal SRT 'obtained from the counter 34 is supplied to the address counter 33, whereby the address counter 33
Generates address data DAD indicating the next address of the initial address in the memory unit 31 and supplies it to the memory unit 31. Thus, the second time interval data DRIM is read from the memory unit 31 and supplied to the counter 34. The counter 34 counts the clock pulse signal CLK in accordance with the data read time interval represented by the second time interval data DRIM,
When the count ends, the read timing signal SRT '
Is sent.

Thereby, read timing signal SRT 'obtained from counter 34 is supplied to read address signal forming section 35, and read address signal SRT' representing an address corresponding to read timing signal SRT 'is output from read address signal forming section 35. The SAD is supplied to the memory unit 11,
The signal data DS is read from the address represented by the read address signal SAD in the memory unit 11. At the same time, the read timing signal SRT 'obtained from the counter 34 is supplied to the address counter 33, whereby the address counter 33 generates the address data DAD representing the next address in the memory section 31 and stores it in the memory section 31. To the unit 31. Thereby,
The third time interval data DRIM is read from the memory unit 31 and supplied to the counter 34. Thereafter, the same operation is performed by reading the 32nd time interval data DRIM from the memory unit 31 and executing the counter operation. It is repeated until it is supplied to.

As a result, the signal data DS stored in the memory unit 11
The two time interval data DRIM are sequentially read out at 32 data readout time intervals, which are respectively represented, and are supplied to the D / A conversion unit 18 via the latch unit 17.
As a result, the signal data D
S / D conversion is performed on S to obtain a signal SO to be formed.

Under these circumstances, the counter 34 and the address counter 33 form timing signal generating means, and the read address signal forming section 35 reads data signal DS from the memory section 11 to read data. It forms the means.

FIG. 5 shows an example of a signal generation circuit according to the invention described in any one of claims 5 to 7 of the present application.

In the example shown in FIG.
1, the memory unit 41 stores a plurality of time interval data DTI, each representing a total time interval between signal timings determined by dividing each cycle of a signal to be formed by a time axis. I have.

As shown in FIG. 6, the plurality of time intervals represented by the plurality of time interval data DTI stored in the memory unit 41 correspond to each period Ts of the signal SO to be formed.
Of the plurality of signal timings tn, which are determined by dividing the time axis so that the signal data DS sequentially increasing and decreasing with a constant level value are arranged, that is, by dividing the time axis so that the level increase and decrease become equal. Are the time intervals between adjacent ones.

In the example shown in FIG. 5, the read timing signal generator 42 and the read address signal generator 4
A memory control unit 45 including a 3 and an addition / subtraction unit 44 is provided. Then, the read timing signal generator 42
Is supplied with a read trigger pulse signal PTR, and the read timing signal generator 42 supplies a first timing signal STA every time the read trigger pulse signal PTR is supplied.
And supplies it to the read address signal forming unit 43, forms a second timing signal STB, and supplies it to the addition / subtraction unit 44.

The read address signal forming section 43 outputs the read trigger pulse signal PTR to the read timing signal generating section 42.
In response to the first first timing signal STA after being supplied to the memory section 41, a read address signal SAD representing an initial address of the memory section 41 is formed and supplied to the memory section 41. Thereby, the first time interval data DTI is read from the memory unit 41 and supplied to the read timing signal generation unit 42.

The addition / subtraction unit 44 responds to the first second timing signal STB after the read trigger pulse signal PTR is supplied to the read timing signal generation unit 42.
The signal data DS representing the initial level value is generated and supplied to the latch unit 46. In the latch section 46, the signal data DS from the addition / subtraction section 44 is temporarily held.

The read timing signal generating section 42 to which the first time interval data DTI read from the memory section 41 is supplied, generates the next timing at a timing corresponding to the time interval represented by the first time interval data DTI. The first timing signal STA is formed and supplied to the read address signal forming unit 43, and the next second timing signal STB is formed and supplied to the adding / subtracting unit 44.

The read address signal forming section 43 supplied with the next first timing signal STA from the read timing signal generating section 42 follows the initial address of the memory section 41 in accordance with the first timing signal STA. A read address signal SAD representing the next address is formed and supplied to the memory unit 41. Thereby, the memory unit 41
, The second time interval data DTI is read from
It is supplied to the read timing signal generator 42.

Further, the adder / subtractor 44 supplied with the next second timing signal STB from the read timing signal generator 42 responds to the second timing signal STB.
A signal data DS representing a level obtained by adding or subtracting a constant level value to or from the initial level value is generated and supplied to the latch unit 46. In the latch section 46, the signal data DS from the addition / subtraction section 44 is temporarily held.

The read timing signal generating section 42 to which the second time interval data DTI read from the memory section 41 is supplied, further generates a timing corresponding to the time interval represented by the second time interval data DTI. The next first timing signal STA is formed and supplied to the read address signal forming section 43, and the next second timing signal STB is further formed and supplied to the addition / subtraction section 44.

Such a read timing signal generator 42
Of the time interval data DT read from the memory unit 41
In the operation according to I, the last time interval data DTI is read from the memory unit 41 and the last time interval data DTI is read out.
The operation is repeatedly performed until the operation according to the TI ends. Accordingly, the operation of the read address signal forming unit 43 according to the first timing signal STA from the read timing signal generating unit 42 and the second operation of the adding / subtracting unit 44 from the read timing signal generating unit 42 Timing signal S
The operation according to TB is also performed repeatedly until the repetitive operation of the read timing signal generator 42 ends.

The operation of the read timing signal generator 42, the read address signal generator 43, and the adder / subtractor 44 constituting the memory control unit 45 is such that the read trigger pulse signal PTR is supplied to the read timing signal generator 42. It is repeated every time. As a result, during the period from the start to the end of the operations of the read timing signal generator 42, the read address signal generator 43, and the adder / subtractor 44 corresponding to each read trigger pulse signal PTR supplied to the read timing signal generator 42. In the addition / subtraction unit 44, signal data DS that sequentially increases and decreases with a constant level value for one cycle of the signal SO to be formed is formed, and is supplied to the latch unit 46.

The signal data DS temporarily stored in the latch section 46 is supplied to a D / A conversion section 47. As a result, the D / A converter 47 outputs the signal data DS.
Is subjected to D / A conversion to obtain a signal SO to be formed.

Under such circumstances, the read address signal forming section 43 forms data reading means for reading the time interval data DTI from the memory section 41, and the adding / subtracting section 44 performs addition or subtraction. This means that signal data forming means for obtaining the signal data DS is formed.

[0065]

As is apparent from the above description, in the signal generating circuit according to the first or second aspect of the present invention, signal data is read from the memory means. The time interval data obtained from the data holding means under the condition that the timing signal generating means for generating the read timing signal for determining the timing operates according to the clock pulse signal having an asynchronous relationship with the signal to be formed. Of the period of the read timing signal generated according to the data read time interval represented by the time interval data, and when the result of the total exceeds one cycle of the clock pulse signal, the cycle of the read timing signal is calculated. Is extended by one cycle of the clock pulse signal, so that the timing of reading signal data from the memory The increase in the "shift" with respect to the read timing based on the data read time interval represented by the interval data is suppressed, whereby the signal data read from the memory means is formed by being subjected to D / A conversion. Signal waveform distortion is effectively suppressed.

In the signal generation circuit according to the third or fourth aspect of the present invention, the signal generation circuit is determined according to the number of data per cycle of the signal to be formed. A second memory means for storing time interval data indicating a total data read time interval within a cycle of a signal to be formed;
Timing signal generating means for generating a read timing signal for determining the read timing of the signal data from the memory means performs a count operation in accordance with each time interval data read from the second memory means, and performs the count operation. Since the read timing signal is generated every time, the first
Of the signal data read timing from the first memory means does not increase with respect to the read timing based on the data read time interval represented by the time interval data. Waveform distortion of a signal to be formed, which is obtained by performing D / A conversion on signal data, is effectively suppressed.

Further, in the signal generation circuit according to any one of the fifth to seventh aspects of the present invention, the level of the signal to be formed is increased or decreased within each cycle. And memory means for storing time interval data indicating a time interval between signal timings determined by dividing the time axis so that the time intervals are made equal to each other. Since the first timing signal and the second timing signal, which determine the read timing and the timing at which the signal data is obtained from the signal data forming means, respectively, are generated in accordance with each time interval data read from the memory means. , The time interval data representing the timing at which the signal data is obtained from the signal data forming means. An increase in "shift" with respect to the signal timing having the interval does not occur. Therefore, the waveform of the signal to be formed, which is obtained by performing D / A conversion on the signal data obtained from the signal data forming means. The distortion is effectively suppressed.

[Brief description of the drawings]

FIG. 1 is a block connection diagram showing an example of a signal generation circuit according to the invention described in claim 1 or claim 2 of the present application.

FIG. 2 is a time chart for explaining time interval data in the example shown in FIG. 1;

FIG. 3 is a circuit connection diagram showing a specific configuration example of a read timing signal generator in the example shown in FIG. 1;

FIG. 4 is a block connection diagram showing an example of a signal generation circuit according to the invention described in claim 3 or claim 4 of the present application;

FIG. 5 is a block connection diagram showing an example of a signal generation circuit according to any one of claims 5 to 7 in the claims of the present application.

FIG. 6 is a time chart for explaining time interval data in the example shown in FIG. 5;

[Explanation of symbols]

11, 31, 41 Memory unit 12 Microcomputer 13, 32, 45 Memory control unit
14, 17, 25, 46 Latch section 15, 42
Read timing signal generator 16, 35, 43 Read address signal generator 18, 47 D / A converter 21 Data selector 22 Subtractor 2
3, 34 counter 24 data adder 3
3 address counter 44 addition / subtraction unit

Claims (7)

[Claims] A memory means for storing signal data relating to a waveform of a signal to be formed, and time interval data representing a data read time interval set according to the number of data per cycle of the signal to be formed. Data holding means for holding, operating in response to a clock pulse signal having an asynchronous relationship with the signal to be formed, generating a read timing signal corresponding to time interval data obtained from the data holding means, The cycle of the read timing signal is accumulated with respect to the difference between the data read time interval and the data read time interval. When the accumulated result exceeds one cycle of the clock pulse signal, the cycle of the read timing signal is set to one of the clock pulse signals. Timing signal generating means for lengthening by a period, and readout timing obtained from the timing signal generating means The read address signal is supplied to said memory means for each issue,
Data reading means for reading the signal data from the memory means; digital / analog converting means for performing digital / analog conversion on the signal data read from the memory means by the data reading means to obtain the signal to be formed; , A signal generation circuit comprising: 2. The signal generating circuit according to claim 1, wherein said timing signal generating means generates a plurality of read timing signals within a period of a signal to be formed. 3. A first memory means for storing signal data relating to a waveform of a signal to be formed, and the signal to be formed determined according to the number of data per cycle of the signal to be formed. A second memory means storing time interval data representing all data read time intervals in the period of the period, and performing a count operation in accordance with each time interval data read from the second memory means. Timing signal generating means for generating a read timing signal; supplying a read address signal to the first memory means for each read timing signal obtained from the timing signal generating means; Data reading means for reading the time interval data from the second memory means, and Therefore, a digital / analog conversion means for performing digital / analog conversion on the signal data read from the first memory means to obtain the signal to be formed. 4. The signal generating circuit according to claim 3, wherein said timing signal generating means operates in response to a clock pulse signal having a frequency that is asynchronous with the frequency of the signal to be formed. 5. A memory means for storing time interval data indicating a time interval between signal timings determined by dividing the time axis so that the level increase and decrease are equal in each cycle of a signal to be formed. Timing signal generating means for generating a first timing signal and a second timing signal according to time interval data read from the memory means; and a read address signal for each first timing signal obtained from the timing signal generating means. A data reading means for supplying the memory means and reading the time interval data from the memory means; a signal data formation for obtaining signal data by adding or subtracting for each second timing signal obtained from the timing signal generating means Means for converting digital / analog data into signal data obtained from the signal data forming means. Digital / analog conversion means for performing log conversion to obtain the signal to be formed. 6. The signal generating circuit according to claim 5, wherein said timing signal generating means operates in response to a clock pulse signal having an asynchronous relationship with a signal to be formed. 7. A signal generating circuit according to claim 5, wherein said signal data forming means obtains signal data by performing addition or subtraction by a constant value.