JP2000241459A - Waveform recording device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a waveform recording device capable of detecting a waveform abnormality simultaneously, when a noise or the like is superimposed on a continuously repeating waveform. SOLUTION: This waveform recording device for detecting a waveform abnormality of a repeating waveform is equipped with an A/D converter 1 for converting an input waveform signal into a digital signal, a reference waveform output means 50 for outputting reference waveform data set beforehand by synchronizing with the input waveform signal, a comparison circuit 11 for detecting the waveform abnormality by comparing the output of the A/D converter 1 with the reference waveform data, and a waveform recording means 51 for recording the input waveform signal containing the waveform abnormality based on the output of the comparison circuit 11.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a waveform recording apparatus, and more particularly to a waveform recording apparatus capable of detecting a waveform abnormality in real time when noise or the like is superimposed on a continuously repeated waveform.

[0002]

2. Description of the Related Art A conventional waveform recording apparatus converts an input waveform into an A / D
The data is fetched by using a converter or the like and stored in a storage circuit sequentially, and the stored waveform data is called up from the storage circuit and displayed or analyzed as needed.

FIG. 8 is a block diagram showing an example of such a conventional waveform recording apparatus. In FIG. 8, 1 is A /
D converters, 2 and 4 are storage circuits, 3 is a control circuit, 100
Is an input waveform signal.

An input waveform signal 100 is input to an A / D converter 1, and an output of the A / D converter 1 is connected to a storage circuit 2. The outputs of the storage circuits 2 and 4 are connected to the control circuit 3, respectively.

Now, the operation of the conventional example shown in FIG. 8 will be described with reference to FIG. FIG. 9 is a characteristic curve diagram showing an example of the input waveform signal 100 and the reference waveform data. The input waveform signal 100 is converted into a digital signal by the A / D converter 1 and is sequentially stored and stored in the storage circuit 2. The control circuit 3 reads out the waveform data stored in the storage circuit 2 as needed, and performs display or waveform analysis.

Further, reference waveform data for detecting a waveform abnormality is stored in the storage circuit 4 in advance, and the control circuit 3 stores the waveform data stored in the storage circuit 2 and the storage circuit 4. By comparing the reference waveform data, a waveform abnormality such as noise superimposed on the waveform is detected.

For example, the storage circuit 2 stores waveform data as shown in FIG. 9A, and the storage circuit 4 stores reference waveform data as shown by a broken line in FIG. 9B. In this case, when a waveform such as “NZ01” in FIG. 9 is superimposed on the input waveform signal 100 due to noise as shown in FIG. 9A, “TA01” in FIG. Since a trigger area shown in FIG. 9 is exceeded, a trigger such as "TG01" in FIG. 9 can be detected. That is, the control circuit 3 can detect a waveform abnormality by displaying the waveform data before and after the occurrence of the trigger on a display device (not shown).

As a result, it is possible to detect a waveform abnormality by comparing the acquired waveform data with the reference waveform data and displaying the waveform data before and after the occurrence of the trigger on a display device (not shown).

[0009]

However, in the conventional example shown in FIG. 8, the input waveform signal 100 is once taken into the storage circuit 2 based on a trigger obtained from the input waveform signal 100 by the control circuit 3, and then stored in the storage circuit 4. In order to compare with the reference waveform data, in other words, the trigger generation for capturing the waveform, the data capture and the comparison processing are performed in a batch process, the capture operation of the input waveform signal 100 is performed when the waveform abnormality is detected. There was a problem that dead time was caused because of failure. For this reason, there was a problem that it was not possible to detect a waveform abnormality that occurred during the dead time. In particular, a waveform abnormality cannot be detected for a continuously repeated waveform such as a power supply waveform. Therefore, an object of the present invention is to realize a waveform recording device capable of detecting a waveform abnormality in real time when noise or the like is superimposed on a continuously repeated waveform.

[0010]

According to a first aspect of the present invention, there is provided a waveform recording apparatus for detecting a waveform abnormality of a repetitive waveform. An A / D converter for converting the input waveform signal, reference waveform output means for outputting preset reference waveform data in synchronization with the input waveform signal, and comparing the output of the A / D converter with the reference waveform data A comparison circuit for detecting the waveform abnormality, and a waveform recording means for recording the input waveform signal including the waveform abnormality based on the output of the comparison circuit. When superimposed, it is possible to detect a waveform abnormality in real time.

According to a second aspect of the present invention, in the waveform recording apparatus according to the first aspect, the reference waveform output means generates a synchronous trigger signal from an output of the A / D converter. A first timer circuit that outputs a pulse signal having a shorter cycle than the synchronization trigger signal based on the synchronization trigger signal; and a first timer circuit that outputs a pulse signal having a longer cycle than the synchronization trigger signal based on the synchronization trigger signal. A second timer circuit, a reset generation circuit for generating a reset signal based on the synchronization trigger signal and the outputs of the first and second timer circuits, and a reference waveform previously incremented by an address signal and stored in a storage circuit. When noise and the like are superimposed on a waveform that is continuously repeated by being composed of an address counter circuit that outputs data It is possible to detect the waveform abnormality in real time.

According to a third aspect of the present invention, in the waveform recording apparatus according to the second aspect of the present invention, the reset generation circuit masks a signal that can be generated immediately after the generation of the synchronization trigger signal, thereby providing a reference waveform. It is possible to prevent data phase shift.

According to a fourth aspect of the present invention, in the waveform recording apparatus of the second aspect, the reset generation circuit ignores the synchronization trigger signal when the pulse of the first timer circuit is at a high level. By doing so, it is possible to prevent a phase shift of the reference waveform data.

According to a fifth aspect of the present invention, in the waveform recording apparatus according to the second aspect of the present invention, the reset generation circuit forcibly generates the reset signal a predetermined period after the generation of the synchronization trigger signal. Even when the input waveform signal is stopped at the "0" level, the waveform can be recorded.

According to a sixth aspect of the present invention, in the waveform recording apparatus according to the second aspect, the reset generation circuit outputs the reset signal when the pulse of the second timer circuit goes low. By generating the signal, the waveform can be recorded even when the input waveform signal stops at the “0” level.

According to a seventh aspect of the present invention, in the waveform recording apparatus according to the first aspect, the waveform recording means comprises:
A storage circuit, and the input waveform signal including the waveform abnormality temporarily storing the output for a predetermined time width of the A / D converter in the storage circuit temporarily based on the output from the comparison circuit; And a memory controller that records the waveform error, it becomes possible to detect a waveform abnormality in real time when noise or the like is superimposed on a continuously repeated waveform.

According to an eighth aspect of the present invention, in the waveform recording apparatus according to the first aspect, the waveform recording means comprises:
The circuit of the waveform recording means includes a ring memory circuit that constantly overwrites and records an input waveform signal for a fixed time width, and a memory controller that records the contents of the ring memory circuit based on the output from the comparison circuit. The configuration is simplified.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below in detail with reference to the drawings. FIG. 1 is a block diagram showing the configuration of an embodiment of the waveform recording apparatus according to the present invention. 1 and 10 in FIG.
0 is assigned the same reference numeral as in FIG. 8, 5 is a synchronous trigger detection circuit, 6 and 7 are timer circuits, 8 is a reset generation circuit,
9 is an address counter circuit, 10 is a storage circuit in which reference waveform data is stored in advance, 11 is a comparison circuit, 12 is a storage circuit in which an input waveform signal is stored, 13 is a memory controller, 101 is a synchronization trigger signal, 102 and 103 is an output signal of the timer circuits 6 and 7, 104 is a reset signal, 105 is an address signal, 106 is reference waveform data,
107 is a sampling timing signal.

Reference numerals 5 to 10 denote reference waveform output means 50.
And 12 and 13 constitute the waveform recording means 51, respectively.

The input waveform signal 100 is inputted to the input terminal of the A / D converter 1, and the output of the A / D converter 1 is supplied to the synchronous trigger detection circuit 5, one input terminal of the comparison circuit 11, and the input of the storage circuit 12. Connected to each terminal. The synchronization trigger signal 101, which is the output signal of the synchronization trigger detection circuit 5, is connected to the input terminals of the timer circuits 6 and 7 and the input terminal of the reset generation circuit 8, respectively.

The output signals 102 and 103 of the timer circuits 6 and 7 are connected to other input terminals of the reset generation circuit 8, and the reset signal 10 which is the output of the reset generation circuit 8 is output.
4 is connected to a reset input terminal of the address counter circuit 9.

An address signal 105 output from the address counter circuit 9 is connected to an address input terminal of the storage circuit 10, and the reference waveform data 10 output from the storage circuit 10 is output.
6 is connected to the other input terminal of the comparison circuit 11.

An output of the comparison circuit 11 is connected to a memory controller 13, and an address signal output from the memory controller 13 is connected to an address input terminal of the storage circuit 12. Further, the sampling timing signal 107 is supplied to the timer circuit 6, the timer circuit 7, the address counter circuit 9
And a clock input terminal of the memory controller 13.

The operation of the embodiment shown in FIG. 1 will now be described with reference to FIG.
This will be described with reference to FIGS. 3, 4, and 5. FIG. 2 shows (a) an input waveform signal 100, (b) a synchronization trigger signal 101,
(C) output signal 102 of timer circuit 6, (d) output signal 103 of timer circuit 7, (e) reset signal 104,
(F) Address signal 105 and (g) reference waveform data 1
FIGS. 3 and 4 are timing charts showing details of the output signals 102 and 103 of the timer circuits 6 and 7, and FIG. 5 is an explanatory view explaining trigger detection due to waveform abnormality.

The synchronization trigger detection circuit 5 generates a synchronization trigger signal 101 synchronized with the input waveform signal 100 captured by the A / D converter 1 based on a preset level.
For example, (a) input waveform signal 100 shown in FIG.
In the case of a power supply waveform of "Hz", the (b) synchronization trigger signal 101 generated is output every "20 ms" as shown in FIG.

The timer circuits 6 and 7 count the sampling timing signal 107 in synchronization with the synchronization trigger signal 101, and generate a one-shot pulse signal based on a preset value. For example, as shown in FIG. 3, the timer circuit 6 sets “1” in synchronization with the synchronization trigger signal 101 (a).
An 8 ms "pulse signal is generated.

For example, the timer circuit 7 generates a pulse signal of "22 ms" in synchronization with the synchronization trigger signal 101. However, in this case, since the period of the synchronization trigger signal 101 is "20 ms", the timer circuit 7 is reset before the falling of the pulse signal by the synchronization trigger signal 101 as shown in FIG. It is kept as it is.

On the other hand, for some reason, the synchronization trigger signal 10
When 1 is no longer generated, as shown in FIG.
The output signal 103 is the last applied synchronization trigger signal 10.
After one, it falls at "22 ms".

The reset generation circuit 8 outputs the synchronization trigger signal 10
The reset signal 104 is output by a combination of the output signal 102 and the output signals 102 and 103 of the timer circuits 6 and 7. That is, (1) when the first synchronization trigger signal 101 is generated immediately after the start (2) when the output signal 102 is at a low level and the output signal
(3) When the output signal 103 changes to a low level When each of the above conditions (1) to (3) is satisfied, a reset signal 104 is output. .

For example, (e) reset signal 1 shown in FIG.
Reference numeral 04 denotes the timing indicated by "RT01" in FIG. 2, in other words, "RT02" and "RT02" in FIG. 2 under the condition (1).
RT03 "and the like occur under the above condition (2).

The address counter circuit 9 sequentially counts up and outputs the address signal 105 according to the sampling timing signal 107. The reset signal 104 generated as described above is input to the reset input terminal of the address counter circuit 9 to The address signal 105 is reset.

For example, (f) address signal 1 shown in FIG.
05 is “000” in synchronization with (a) the input waveform signal 100.
.., "0001", "0002",... Are sequentially incremented.

For this reason, as shown in FIG.
(G) The reference waveform data 106 stored in advance is sequentially output to the comparison circuit 11 in synchronization with the input waveform signal 100.

In the comparison circuit 11, the reference waveform data 10
6 and the input waveform signal 100 are compared. For example, in FIG.
When the level of the input waveform signal 100 exceeds the trigger area formed by the reference waveform data 106 indicated by "TA02" in FIG. 5 as shown by TG02 ", an output signal is supplied from the comparison circuit 11 to the memory controller 13. You.

The memory controller 13 sends the output signal supplied from the comparison circuit 11 to the storage circuit 12 in FIG.
As shown in CD01 ", input waveform data including waveform data before and after" TG02 "in FIG. 5 is recorded.

More specifically, the input waveform signal 100 fetched by the A / D converter 1 is temporarily fetched by the memory controller 13 into the storage circuit 12 temporarily in a predetermined time width, and the comparison circuit The input waveform data from the time when the output from 11 is supplied to the time when a certain period elapses is recorded.

As a result, the reference waveform output means 50 outputs the reference waveform data in synchronization with the input waveform signal 100, and compares the reference waveform data with the input waveform data to detect a waveform abnormality. When noise or the like is superimposed on a periodically repeated waveform, a waveform abnormality can be detected in real time.

The reason why the reset generation circuit 8 does not accept the synchronization trigger signal 101 for a certain period as shown in the above condition (2) is to prevent a phase shift of the reference waveform data 106.

That is, FIG. 6 is an explanatory diagram for explaining the occurrence of a phase shift. Assuming a trigger level indicated by "TL01" in FIG. 6, if noise is not superimposed on the input waveform signal 100, FIG. Synchronization trigger signals are generated at "TG03", "TG04" and "TG05".

However, when fine noise is actually superimposed on the input waveform signal 100 as shown by "A001" in FIG. 6, the synchronization trigger signal 101 is generated at the rising edge of the noise shown by "EG01" in FIG. May occur, and then the synchronization trigger signal 101 may be generated again at the falling edge of the noise indicated by “EG02” in FIG.

In this case, there occurs a problem that the reference waveform data 106 is output in synchronization with the timing indicated by “EG02” in FIG. 6 instead of the original synchronization timing “EG01” in FIG. Therefore, the above-described phase shift can be prevented by ignoring the synchronization trigger signal that may occur in “EG02” in FIG. 6 using the output signal 102 that goes high immediately after the synchronization trigger signal 101. become.

As a result, it is possible to prevent a phase shift of the reference waveform data by masking a signal which can be generated immediately after the generation of the synchronization trigger signal 101 due to the superimposed noise in the reference waveform output means 50. Become.

As shown in FIG. 4, when the generation of the synchronization trigger signal 101 is stopped, the reset signal 104 is generated by the output signal 103. The above condition (3) is that the input waveform signal 100 is at the "0" level. This is for obtaining the difference from the input waveform signal 100 by forcibly reading out the reference waveform data 106 even when the processing stops at the step (1).

That is, FIG. 7 shows that the input waveform signal 100 is "
8 is an explanatory diagram illustrating an operation when the input waveform signal 100 stops at the “0” level at a timing indicated by “T001” in FIG.
Since the trigger level shown in the middle “TL02” is not reached, the synchronization trigger signal 101 is not generated.

For this reason, since the address counter circuit 9 is not reset, the output of the reference waveform data 106 is stopped or undefined during the period indicated by "DT01" in FIG. 13 is not supplied, and the recording of the input waveform signal is not performed.

However, at the time indicated by "T002" in FIG. 7, the output signal 103 of the timer circuit 7 changes to low level,
Since the reset signal 104 is generated in synchronism therewith, the reference waveform data 106 is forcibly output from that time. Therefore, a waveform abnormality is detected at the time indicated by “T003” in FIG. Since the output signal is applied, the input waveform signal 100 can be recorded.

As a result, the reference waveform output means 50 forcibly generates the reference waveform data 106 after a certain period after the generation of the synchronization trigger signal 101, so that the input waveform signal 100 stops at the "0" level. It is also possible to record waveforms.

Further, in the embodiment shown in FIG.
Buffered the waveform data in the storage circuit 12
As a ring memory circuit, the input waveform signal may be always overwritten and recorded, and the contents of the ring memory circuit may be transferred to another recording circuit and recorded based on the output signal from the comparison circuit 11.

In this case, the memory controller 13 only needs to transfer the contents of the ring memory circuit to another storage circuit after the output signal of the comparison circuit 11 is applied. 5
1 is simplified. Further, if only one waveform abnormality is to be recorded, it is only necessary to stop the operation of the ring memory circuit, so that the circuit configuration of the waveform recording means 51 is further simplified.

[0050]

As is apparent from the above description,
According to the present invention, the following effects can be obtained. According to the first, second and seventh aspects of the present invention, the reference waveform output means outputs the reference waveform data in synchronization with the input waveform signal, and compares the reference waveform data with the input waveform data to obtain a waveform abnormality. , It becomes possible to detect a waveform abnormality in real time when noise or the like is superimposed on a continuously repeated waveform.

According to the third and fourth aspects of the present invention, the signal which can be generated immediately after the generation of the synchronization trigger signal due to the superimposed noise in the reference waveform output means is masked, thereby providing the reference waveform data. Can be prevented.

According to the fifth and sixth aspects of the present invention, the reference waveform output means forcibly generates the reference waveform data after a predetermined period after the generation of the synchronization trigger signal, so that the input waveform signal becomes "0". Waveforms can be recorded even when stopped at the level.

Further, according to the invention of claim 8, the input waveform signal is always overwritten and recorded in the ring memory circuit, and the contents of the ring memory circuit are recorded based on the output signal from the comparison circuit. The circuit configuration is simplified.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of a waveform recording apparatus according to the present invention.

FIG. 2 is a timing chart illustrating an operation.

FIG. 3 is a timing chart showing details of an output signal.

FIG. 4 is a timing chart showing details of an output signal.

FIG. 5 is an explanatory diagram illustrating trigger detection due to a waveform abnormality.

FIG. 6 is an explanatory diagram illustrating occurrence of a phase shift.

FIG. 7 is an explanatory diagram illustrating an operation when an input waveform signal stops at a “0” level.

FIG. 8 is a configuration block diagram illustrating an example of a conventional waveform recording device.

FIG. 9 is a characteristic curve diagram showing an example of an input waveform signal and reference waveform data.

[Explanation of symbols]

 Reference Signs List 1 A / D converter 2, 4, 10, 12 Storage circuit 3 Control circuit 5 Synchronous trigger detection circuit 6, 7 Timer circuit 8 Reset generation circuit 9 Address counter circuit 11 Comparison circuit 13 Memory controller 50 Reference waveform output means 51 Waveform recording Means 100 Input waveform signal 101 Synchronous trigger signal 102, 103 Output signal 104 Reset signal 105 Address signal 106 Reference waveform data 107 Sampling timing signal

Claims (8)

[Claims] 1. A waveform recording apparatus for detecting a waveform abnormality of a repetitive waveform, comprising: an A / D converter for converting an input waveform signal into a digital signal; and a reference waveform data set in advance in synchronization with the input waveform signal. Reference waveform output means for outputting; a comparison circuit for comparing the output of the A / D converter with the reference waveform data to detect the waveform abnormality; and the input including the waveform abnormality based on the output of the comparison circuit. A waveform recording device comprising: a waveform recording unit that records a waveform signal. 2. A synchronization trigger detection circuit for generating a synchronization trigger signal from an output of the A / D converter, wherein the reference waveform output means includes: a pulse signal having a shorter period than the synchronization trigger signal based on the synchronization trigger signal; A first timer circuit that outputs a pulse signal having a period longer than the synchronization trigger signal based on the synchronization trigger signal; a synchronization timer signal and the first and second timers A reset generation circuit for generating a reset signal based on an output of the circuit, and an address counter circuit for incrementing an address signal and outputting reference waveform data stored in a storage circuit in advance. 2. The waveform recording device according to 1. 3. The waveform recording apparatus according to claim 2, wherein the reset generation circuit masks a signal that can be generated immediately after the generation of the synchronization trigger signal. 4. The apparatus according to claim 2, wherein said reset generation circuit ignores said synchronization trigger signal when a pulse of said first timer circuit is at a high level.
The waveform recording device according to the above. 5. The waveform recording apparatus according to claim 2, wherein said reset generation circuit forcibly generates said reset signal after a predetermined period after generation of said synchronization trigger signal. 6. The waveform recording apparatus according to claim 2, wherein said reset generation circuit generates said reset signal when said pulse of said second timer circuit becomes low level. 7. The waveform recording means, wherein a storage circuit and an output for a fixed time width of the A / D converter are temporarily sequentially taken into the storage circuit, and temporarily stored based on an output from the comparison circuit. 2. The waveform recording apparatus according to claim 1, further comprising: a memory controller that records the input waveform signal including the stored waveform abnormality. 8. A ring memory circuit which constantly overwrites an input waveform signal for a predetermined time width, and a memory controller which records the contents of the ring memory circuit based on an output from the comparison circuit. The waveform recording device according to claim 1, wherein the waveform recording device is configured.