JPH11163034A - Semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a semiconductor integrated circuit in which peeling in an insulating film at the time of bonding can be prevented, and a high frequency loss generated when an electric signal is transmitted can be reduced. SOLUTION: An insulating film 200 is formed on a semiconductor substrate 100, and a laminated structure including SOG layers 209 and 206 is obtained. A pad 300 for bonding is provided with a third aluminum layer 303 exposed from the insulating film 200, a first aluminum layer 301 faced to the semiconductor substrate 100, and a second aluminum layer 302 interposed between the first aluminum 301 and the third aluminum layer 303. The first aluminum layer 301 is shaped so that the inside part can be notched. The second aluminum 302 is brought into contact with an SOG layer 206 and P-TEOS layers 205 and 207 interposing this SOG layer 206.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit, and more particularly to a bonding pad capable of reducing a high-frequency loss generated when an electric signal is transmitted while preventing peeling in an insulating film during bonding. Regarding the structure.

[0002]

2. Description of the Related Art In recent years, demand for semiconductor integrated circuits has been rapidly expanding due to the remarkable spread of mobile phones. Functionally, a device that can operate even at a high frequency is required. In response to these, technological development for reducing high-frequency loss has been promoted.

FIGS. 21 and 22 show a conventional semiconductor integrated circuit, in particular, bonding pads in an input / output section. FIG.
1 is a top view, and FIG. 22 is a sectional view taken along a broken line 22 shown in FIG. Each code in FIG. 21 corresponds to each code in FIG.

In both figures, 100 is a semiconductor (Si) substrate, 201 is a thermal oxide layer, 202 is LP-TEOS (Low
Presure-Tetra Etyle Ortho Silicate) layer, 203 is BPSG (Boro-Phospho Silicate Glass) layer, 20
4 is an LP-TEOS layer, 205 is a P-TEOS (Plasma
-Tetra Etyle Ortho Silicate) layer, 206 is SOG
(Spin On Glass) formed layer (hereinafter simply referred to as “SOG layer”), 207 is a P-TEOS layer, 20
8 is a P-TEOS layer, 209 is a SOG layer, 210 is a P-TEOS layer.
A TEOS layer, 391 is a first aluminum layer, 392 is a second aluminum layer, 393 is a third aluminum layer, and 400 is a plasma nitride film for surface protection.

[0005] The first aluminum layer 391, the second aluminum layer 39
The second and third aluminum layers 393 constitute bonding pads 390 in a conventional semiconductor integrated circuit.

This semiconductor integrated circuit has a CMO (not shown).
An element such as an S transistor is formed.
01 acts as element isolation. A multilayer wiring structure (not shown) is formed on this element, and the LP-TE
Each layer from the OS layer 202 to the P-TEOS layer 210 is:
This is an interlayer insulating film in the multilayer wiring structure.

[0007] The multi-layer wiring structure (not shown) has an LP-T
It is completed through formation of each layer from the EOS layer 202 to the P-TEOS layer 210, formation of aluminum wiring, and the like. First aluminum layer 391 forming bonding pad 390, second aluminum layer 391
The aluminum layer 392 and the third aluminum layer 393 are formed as each of the multilayer wirings is formed. Also, the first aluminum layer 39
The first, second aluminum layer 392, and third aluminum layer 393 are different in size but all have similar square shapes.

In the lower layer of the insulating film 200, BPS
G layer 203 is used, while SOG layer 2
06, 209 are used. SOG and BPSG are used to flatten the surface. SOG can be flattened by heat treatment at about 400 ° C., while BPSG is 850 mm.
A heat treatment of about ° C. is required, and it cannot be used after the first aluminum layer 391 is formed.

[0009]

The bonding pad 390 in the conventional semiconductor integrated circuit shown in FIG. 22 has a parasitic capacitance between the bonding pad 390 and the semiconductor substrate. High frequency signals are lost due to parasitic capacitance.

FIG. 23 shows a conventional bonding pad of a semiconductor integrated circuit for reducing such high-frequency loss. The bonding pad 390 shown in FIG. 23 is formed on the surface of the LP-TEOS layer 207. Therefore, since the distance between the bonding pad 390 and the semiconductor substrate 100 becomes long, the parasitic capacitance is reduced, and the high-frequency loss can be reduced. However, SOG has a property that it is easily peeled off.
0, the P-TEOS layer 205 and the SOG layer 2
Separation occurs at the interface between the semiconductor substrate 100 and the interface between the semiconductor substrate 100 and the interface between the SOG layer 206 and the P-TEOS layer 207. As described above, the conventional bonding pad 390 shown in FIG. 23 can reduce high-frequency loss, but has a problem that the bonding pad 390 is separated from the semiconductor substrate 100.

SUMMARY OF THE INVENTION The present invention has been made to solve this problem, and it is possible to prevent a bonding pad from being separated from a semiconductor substrate at the time of bonding and to reduce a high-frequency loss generated when an electric signal is transmitted. It is an object to obtain a semiconductor integrated circuit that can be reduced.

[0012]

According to a first aspect of the present invention, there is provided a semiconductor device comprising: (a) a semiconductor substrate; and (b) a semiconductor substrate formed on the semiconductor substrate, and (b-1) SOG (Spin On Glas).
s), and (b-2) a second insulating layer made of a silicon oxide film different from the SOG and stacked adjacent to the lower surface of the first insulating layer. A film, (c) (c-1) a first conductive layer including an upper end, and a lower end closer to the semiconductor substrate than the upper end, and (c-2) the upper end and the first and second insulating layers. Contact with the second
The first conductive layer has a shape in which the inside of the first conductive layer is cut away from the shape of the second conductive layer when viewed from the upper end toward the lower end.

In the means for solving problems according to claim 2 of the present invention, the second conductive layer includes (c-2-1) an upper layer including the upper end, and (c-2-2) including the lower end. A lower layer laminated and electrically connected to the upper layer, wherein the insulating film is made of (b-3) the SOG and is in contact with the second insulating layer from a side opposite to the first insulating layer. And (b-4) a silicon oxide film different from the SOG and in contact with and laminated to the third insulating layer from the side opposite to the second insulating layer. A fourth insulating layer, wherein the upper layer is in contact with the third and fourth insulating layers, and the lower layer is in contact with the fourth insulating layer.

According to a third aspect of the present invention, the shape with the inside cutout is a frame shape along the edge of the second conductive layer when viewed from the direction.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiment 1 1 and 2 show a semiconductor integrated circuit according to a first embodiment of the present invention, in particular, bonding pads of an input / output unit. 1 is a top view, and FIG. 2 is a cross-sectional view taken along a broken line 2 shown in FIG. Each code in FIG. 1 corresponds to each code in FIG. The input / output unit is provided, for example, on the outer periphery of the semiconductor integrated circuit.

1 and 2, reference numeral 100 denotes a semiconductor (S
i) substrate, 201: thermal oxide layer having a thickness of about 4000 to about 5000 angstroms; 202: LP-TEOS (Tetra Etyle Ortho) having a thickness of about 2000 angstroms
Silicate) layer 203 is a BPSG (Boro-Phospho Silicate Glass) with a thickness of about 6000 Å
The layer 204 is an LP having a thickness of about 1000 angstroms.
A TEOS layer, 205 a P-TEOS layer with a thickness of about 2500 angstroms, 206 a SOG layer with a thickness of about 2500 angstroms, 207 a P-TEOS layer with a thickness of about 5000 angstroms, and 208 a film thickness of about 5000 angstroms. 2
500 Å P-TEOS layer, 209 SOG layer about 2500 Å thick, 210 P-TEOS layer about 5000 Å thick,
Reference numeral 301 denotes a first aluminum layer of AlSiCu having a thickness of about 4000 to about 5000 angstroms;
A second aluminum layer of AlSiCu of 000 to about 6500 angstroms;
0 Angstrom AlSiCu third aluminum layer, 4
Reference numeral 00 denotes a plasma nitride film having a maximum thickness of about 7,500 angstroms for surface protection.

First aluminum layer 301, second aluminum layer 30
Second and third aluminum layers 303 constitute bonding pads 300 in the semiconductor integrated circuit according to the first embodiment of the present invention.

A manufacturing process of a semiconductor integrated circuit having the bonding pads 300 will be described with reference to FIGS.

First, a thermal oxide layer 201 for element isolation is formed on a semiconductor substrate 100. Thereafter, elements such as CMOS transistors are formed on the semiconductor substrate 100 in a region (not shown). Next, an LP-TEOS layer 202 is formed, a BPSG layer 203 is formed on the LP-TEOS layer 202, and the surface is flattened in an atmosphere of 850 ° C. to 900 ° C.
Then, the LP-TEOS layer 2 is formed on the flat BPSG layer 203.
04 (FIG. 3).

Next, the first layer wiring (not shown) is LP
-Formed by sputtering and patterning (photolithography and etching) on the TEOS layer 204; At this time, the first aluminum layer 301 is also formed at the same time. Next, a resist 501 is formed on the first aluminum layer 301. Next, mask 6
The resist 501 is exposed using 01 (FIG. 4). After this exposure and predetermined development, a part of the resist 501 remains (FIG. 5).

Next, the exposed portion of the first aluminum layer 301 is removed by etching using the resist 501 as a resist pattern, so that the first aluminum layer 30 is removed.
1 is shaped into a square frame shape in which the inside of the square is cut out (FIG. 6).

Next, the first aluminum layer 301 and the LP-TE
A P-TEOS layer 205 is formed to cover the OS layer 204. Next, the SOG layer 206 is formed on the P-TEOS layer 205.
Is formed and the surface is flattened in an atmosphere of about 400 ° C.
Next, the P-TEOS layer 207 is formed on the flat SOG layer 206.
Is formed (FIG. 7).

Next, the first aluminum layer 301 is exposed by opening the P-TEOS layer 207 and a part of the surface of the SOG layer 206 and the P-TEOS layer 205 (FIG. 8).

Next, a second layer wiring (not shown) is formed by sputtering and patterning (photolithography and etching). At this time, the second aluminum layer 302 is simultaneously formed so as to cover the first aluminum layer 301, the SOG layer 206, and the P-TEOS layers 205 and 207. Next, a resist 502 is formed on the second aluminum layer 302. Next, the resist 502 is exposed using the mask 602 (FIG. 9). After this exposure and predetermined development, a part of the resist 502 remains (FIG. 10).

Next, the exposed portion of the second aluminum layer 302 is removed by etching using the resist 502 as a resist pattern, so that the second aluminum layer 30 is removed.
2 (FIG. 11).

Next, the second aluminum layer 302 and the P-TEO
A P-TEOS layer 208 is formed so as to cover the S layer 207. Next, an SOG layer 209 is formed on the P-TEOS layer 208 to flatten the surface. Next, the flat SOG layer 20
The P-TEOS layer 207 is formed on the substrate 9 (FIG. 12).

Next, as described with reference to FIGS.
-TEOS layer 210, SOG layer 209 and P-TEO
The second aluminum layer 3 is opened by opening a part of the surface of the S layer 208.
02 is exposed. Then, a third layer wiring (not shown) is sputtered and patterned (photolithography and etching).
By forming the third aluminum layer 303 and finally forming the plasma nitride film 400,
The structure shown in FIG. 2 is completed.

As described above, the laminated insulating film 200 including the SOG layers 206 and 209 is formed on the semiconductor substrate 100. The bonding pad 300 has a laminated structure including a lowermost first aluminum layer 301, a second aluminum layer 302, and an uppermost third aluminum layer 303. The first aluminum layer 301 and the second
The aluminum layer 302 is buried in the insulating film 200, but the third aluminum layer 303 is exposed from the insulating film 200 for bonding and connecting a wire such as gold or aluminum. The first aluminum layer 301 includes an LP-TEOS layer 204,
It faces the semiconductor substrate 100 via the BPSG layer 203, the LP-TEOS layer 202, and the thermal oxide layer 201. The second aluminum layer 302 and the third aluminum layer 303 are different in size but have a square shape, and the first aluminum layer 301 has a shape in which the inside is cut away from the square shape. In the first embodiment, the first
The shape of the aluminum layer 301 is a frame shape along the edge of the third aluminum layer 303.

Returning to FIG. 2, the SOG layer 206 and the P-TEO
The interface with S layer 205 is in contact with second aluminum layer 302. The interface between the SOG layer 209 and the P-TEOS layer 208 is in contact with the third aluminum layer. There is no SOG layer between the lower end of the first aluminum layer 301 and the semiconductor substrate 100.

As described above, the aluminum layer, the P-TEOS layer,
The method of finally forming the bonding pad by repeating the formation of the SOG layer and the P-TEOS has been applied to the process of a highly integrated semiconductor integrated circuit in recent years. For example, the minimum wiring width is 0.8 μm. High Frequency Bi-CM
Applied to OS processes.

FIG. 13 shows an equivalent model of the structure shown in FIG. 1 and FIG. In the figure, Csub1 is a parasitic capacitance between the bonding pad 300 and the semiconductor substrate 100,
Rsub1 is a parasitic resistance inherent in the semiconductor substrate 100;
ub2 is a parasitic capacitance inherent in the semiconductor substrate 100, and T1 is a terminal to which a high-frequency signal is applied. FIG. 14 shows the result of simulation performed on the equivalent model shown in FIG. In this simulation, 1.
A 9 GHz signal was used. As shown in FIG. 14, the loss of the high frequency signal decreases as the parasitic capacitance Csub1 decreases.

The first aluminum layer 301 according to the first embodiment has a rectangular shape with the inside cut away, unlike the conventional case. As a result, the area of the first aluminum layer 301 facing the semiconductor substrate 100 is smaller than in the related art. Therefore,
The parasitic capacitance Csub1 can be reduced as compared with the related art. Therefore, it is possible to reduce a high-frequency loss generated when an electric signal applied to the bonding pad 300 is transmitted.

The first embodiment is different from the structure shown in FIG. 23 in that the first aluminum layer is slightly left and the P-TEO
It can be said that the S layer 205 is in contact with the second aluminum layer 302. That is, the SOG layer 206 and the P-TEOS layer 205
Interface with the second aluminum layer 302 and the SOG layer 20
9 and the P-TEOS layer 208 are in contact with the third aluminum layer, so that the P-TEOS layer 205 and the SOG layer 2
06, the SOG layer 206 and the P-TEOS layer 20
7 are fixed to each other. There is no SOG layer between the lower end of the first aluminum layer 301 and the semiconductor substrate 100. Therefore, when a wire is bonded to the bonding pad 300, the bonding pad 300
From the semiconductor substrate 100 is prevented.

The first aluminum layer 301 only needs to be present as little as possible, but if it is too small, it may disappear in the process. Therefore, if the aluminum width L1 of the first aluminum layer 301 is about 10 μm, Good.

Embodiment 2 FIGS. 15 and 16 show a semiconductor integrated circuit according to the first embodiment of the present invention, in particular, bonding pads of an input / output unit of the semiconductor integrated circuit. FIG.
5 is a top view, and FIG. 16 is a sectional view taken along a break line 16 shown in FIG. Embodiment 2 is different from Embodiment 1 in the shape of second aluminum layer 302.

In the second embodiment, the second aluminum layer 302
Like the aluminum layer 301, it has a shape in which the inside is cut off from a square shape, and is, for example, a frame shape along the edge of the third aluminum layer 303. Thus, the area of second aluminum layer 302 facing semiconductor substrate 100 is smaller than in the first embodiment. Therefore, the parasitic capacitance Csub1 can be further reduced as compared with the first embodiment, and the bonding pad 3
It is possible to further reduce the high-frequency loss that occurs when the electric signal applied to 00 is transmitted.

The second aluminum layer 302 is shaped by etching, and the first aluminum layer 3
Since the first aluminum layer 301 may also be etched, the second aluminum layer 302 may be formed so as to cover the first aluminum layer 301 when viewed from above the semiconductor substrate 100.
May be about 18 μm.

Modified example. First aluminum layer 30 of the first embodiment
1 is a frame type along the edge of the third aluminum layer 303,
The shapes shown in FIGS. 17 to 20, which are top views, may be used. As described above, in the present invention, the shape in which the inside is cut off is a shape in which the entire inside is removed as shown in FIGS. 1 and 20, or a shape in which a part of the inside is removed as shown in FIGS. Means Second aluminum layer 302 of the second embodiment
The same is true for

It is most effective to make the shape of the inside cutout into a frame shape for the following reason. For example, FIG.
This will be described by taking as an example the first aluminum layer 3 shown in FIG.
Since 01 has a large area facing the semiconductor substrate 100, the parasitic capacitance is large, but the area in contact with the insulating film 200 is small, so that the reliability of preventing peeling inside is high. on the other hand,
Although the first aluminum layer 301 shown in FIG. 20 has a small area facing the semiconductor substrate 100, the parasitic capacitance is small, but the reliability of preventing separation in the insulating film 200 is low. Second aluminum layer 3
The same applies to 02. Therefore, in order to reduce the parasitic capacitance while maintaining the reliability of the prevention of peeling, the first aluminum layer 301 and the second aluminum layer 302 have a shape intermediate between FIGS. 17 and 20, that is, the first and second embodiments. The described frame shape is preferred. In particular, if a frame type is adopted, the inner and outer circumferences come into contact with the insulating film 200, so that more contact with the insulating film 200 than the structure shown in FIG. Therefore, the effect of preventing peeling is further enhanced.

Also, for example, FIG. 8 shows a case where the bottom of the opening is flat, but actually, the P-TEOS layer 205 and the SOG layer 206 are excessively etched to
The upper surface of the S layer 205 and the SOG layer 206 is the first aluminum layer 3
01 may be located below the upper surface. A step occurs on the surface of the third aluminum layer 303 according to the step between the first aluminum layer 301 and the SOG layer 206. In the case where the shape with the inside cutout is a frame type, a step corresponding to the step between the first aluminum layer 301 and the SOG layer 206 is generated outside the upper surface of the third aluminum layer 303. This step does not occur inside the upper surface and is not flat. The wire is usually
Bonding is performed with the inside of the upper surface of the third aluminum layer 303 as a target. Therefore, in the structure shown in FIG. 2, the high reliability of the connection between the wire and the bonding pad 300 can be maintained at the same level as the related art.

Also, in the structure shown in FIG. 16, a depression corresponding to the surface of the second aluminum layer 302 is formed outside the upper surface of the third aluminum layer 303, and the second surface is formed inside the upper surface of the third aluminum layer 303. Since there is no depression corresponding to the surface of the aluminum layer 302, high reliability of connection between the wire and the bonding pad 300 can be maintained at the same level as in the related art. Note that the P-TEOS layer 208 surrounded by the second aluminum layer 302 may be excessively etched so that the upper surface of the P-TEOS layer 208 is located below the upper surface of the second aluminum layer 302. However, in practice, the distance between the two second aluminum layers 302 is sufficiently long, so that the inside of the upper surface of the third aluminum layer 302 to which the wires are connected becomes flat.

The SOG layer is composed of P-TEOS and L
The present invention can also be applied to silicon oxide-based materials such as P-TEOS because these materials are likely to peel off when they are stacked adjacent to each other.

The bonding pad 3 having a three-layer structure
Although the case where 00 is applied has been described, it may be applied to a bonding pad having a structure of another number of layers. For example, when the bonding pad has a five-layer structure including the first aluminum layer (lowest layer) to the fifth aluminum layer (top layer), the following is performed. That is, several layers above the lowermost layer, such as the first and second aluminum layers and the first to third aluminum layers, may be cut off from the shape of the uppermost layer to the inside. The first to fourth aluminums are all cut out, and more preferably, the first to fourth aluminums are all frame-shaped along the edge of the uppermost layer.

[0044]

According to the first aspect of the present invention, since the parasitic capacitance formed between the first conductive layer and the semiconductor substrate is reduced, the high-frequency loss generated when an electric signal is transmitted is reduced. Can be. Moreover, since the second conductive layer is in contact with the first and second insulating layers that are easily separated from each other, the separation between the two is prevented. Further, the shape of the first conductive layer is the second conductive layer.
The inside of the second conductive layer is notched due to the shape of the conductive layer, so that a step is unlikely to occur inside the second conductive layer, and the inside of the second conductive layer can be flattened. Therefore, for example, high reliability can be maintained when performing wire bonding.

According to the second aspect of the present invention, the third and fourth insulating layers are further interposed between the second conductive layer and the semiconductor substrate, so that the parasitic capacitance can be further reduced.

According to the third aspect of the present invention, the outer periphery of the frame mold,
Since the inner periphery and the insulating film are in contact with each other, separation between the first and second insulating layers can be more effectively prevented.

[Brief description of the drawings]

FIG. 1 is a top view of a bonding pad of a semiconductor integrated circuit according to a first embodiment of the present invention.

FIG. 2 is a sectional view of a bonding pad of the semiconductor integrated circuit according to the first embodiment of the present invention.

FIG. 3 is a diagram illustrating a method of manufacturing the semiconductor integrated circuit according to the first embodiment of the present invention.

FIG. 4 is a diagram illustrating a method of manufacturing the semiconductor integrated circuit according to the first embodiment of the present invention.

FIG. 5 is a diagram illustrating a method of manufacturing the semiconductor integrated circuit according to the first embodiment of the present invention.

FIG. 6 is a diagram illustrating a method of manufacturing the semiconductor integrated circuit according to the first embodiment of the present invention.

FIG. 7 is a diagram illustrating a method of manufacturing the semiconductor integrated circuit according to the first embodiment of the present invention.

FIG. 8 is a diagram illustrating a method of manufacturing the semiconductor integrated circuit according to the first embodiment of the present invention.

FIG. 9 is a diagram illustrating a method of manufacturing the semiconductor integrated circuit according to the first embodiment of the present invention.

FIG. 10 is a diagram illustrating a method of manufacturing the semiconductor integrated circuit according to the first embodiment of the present invention.

FIG. 11 is a diagram illustrating a method of manufacturing the semiconductor integrated circuit according to the first embodiment of the present invention.

FIG. 12 is a diagram illustrating a method of manufacturing the semiconductor integrated circuit according to the first embodiment of the present invention.

FIG. 13 is a circuit diagram showing an equivalent model of a bonding pad of the semiconductor integrated circuit of the present invention.

FIG. 14 is a graph showing a simulation result for the equivalent model shown in FIG. 4;

FIG. 15 is a top view of a bonding pad of the semiconductor integrated circuit according to the second embodiment of the present invention.

FIG. 16 is a sectional view of a bonding pad of a semiconductor integrated circuit according to a second embodiment of the present invention.

FIG. 17 is a top view showing a modification of the bonding pad of the semiconductor integrated circuit of the present invention.

FIG. 18 is a top view showing a modification of the bonding pad of the semiconductor integrated circuit of the present invention.

FIG. 19 is a top view showing a modification of the bonding pad of the semiconductor integrated circuit of the present invention.

FIG. 20 is a top view showing a modification of the bonding pad of the semiconductor integrated circuit of the present invention.

FIG. 21 is a top view of a bonding pad of a conventional semiconductor integrated circuit.

FIG. 22 is a sectional view of a bonding pad of a conventional semiconductor integrated circuit.

FIG. 23 is a sectional view of a bonding pad of a conventional semiconductor integrated circuit.

[Explanation of symbols]

301 to 303 First to third aluminum layers, 400 plasma nitride film, 501, 502 resist, 601, 602
mask.

Claims (3)

[Claims] (A) a semiconductor substrate; (b) a first insulating layer formed on the semiconductor substrate and comprising (b-1) SOG (Spin On Glass); and (b-2) the SOG. An insulating film comprising a silicon oxide film different from the first insulating layer and having a second insulating layer stacked adjacent to the lower surface of the first insulating layer; (c) (c-1) an upper end; A first conductive layer including a lower end near the semiconductor substrate; and (c-2) a second conductive layer in contact with the upper end and the first and second insulating layers. When viewed from the upper end toward the lower end, the first
Is a semiconductor integrated circuit having a shape in which the inside of the second conductive layer is cut away from the shape of the second conductive layer. 2. The second conductive layer is electrically connected to (c-2-1) an upper layer including the upper end and (c-2-2) an upper layer including the lower end. A lower layer comprising: (b-3) a third layer made of the SOG, which is in contact with and laminated on the second insulating layer from the side opposite to the first insulating layer;
(B-4) a fourth insulating layer made of a silicon oxide film different from the SOG and in contact with and laminated on the third insulating layer from the side opposite to the second insulating layer; 2. The semiconductor integrated circuit according to claim 1, further comprising: the upper layer being in contact with the third and fourth insulating layers, and the lower layer being in contact with the fourth insulating layer. 3. 3. The semiconductor integrated circuit according to claim 1, wherein the shape of the inside cutout has a frame shape along an edge of the second conductive layer when viewed from the direction.