JPH11162870A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent variations of CMP(chemical mechanical polishing) conditions from being reflected on the flatness and to obtain a very flat face, even if a base material which is to be provided with CMP is not flat by forming a stopper film. SOLUTION: This method includes a process, wherein an element isolation region 102 of a specified height is formed on the surface of a semiconductor substrate 101, a process wherein conductive films 104, 105 are formed at least on the element isolation region 102, a process for depositing an insulating film 106 on the conductive films, a process for depositing an interlayer insulating film 107, after etching the conductive films and the insulating film, and a process in which the interlayer insulating film 107 is polished flat. In this case, the insulating film 106 is made of such material that it is polished more slowly than the interlayer insulating film 107 and this insulating film 106 is used as a polishing stopper, when polishing the interlayer insulating film.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of forming an interlayer insulating film on a gate electrode of a device.

[0002]

2. Description of the Related Art In a silicon LSI, a lithographic light source has a shorter wavelength and an optical lens has a higher NA as a pattern becomes finer, so that a depth of focus margin decreases. Therefore, it is important to flatten the device interlayer film.

One of the techniques for planarizing an interlayer film is CMP.
(Chemical and Mechanical
Polishing (chemical mechanical polishing). Figure 2
FIG. 7 shows a typical interlayer film flattening method using CMP, for example, an electronic material (1993.6) p48 or VM.
IC (VLSI MULTILEVER INTERC
ONCONNECTION CONFERENCE) 1990
p438 and the like.

As shown in FIG. 2, an element isolation region (field oxide film) 202 is formed on a silicon substrate 201. Next, as shown in FIG. 3, a gate oxide film 203 is formed, and a gate lower electrode 204 and a gate upper electrode 205 are deposited. Next, as shown in FIG. 4, the resist 206 is patterned by the PR technique, and then, as shown in FIG. 5, the gate electrode is processed by etching using the resist 206 as a mask. Next, as shown in FIG. 6, an interlayer insulating film 207 is deposited, and is subjected to CMP for an appropriate time to be flattened, thereby obtaining a shape as shown in FIG.

[0005] In the planarization by the CMP with a designated time, there is a problem that the flat shape changes due to a variation in the deposited film thickness of the interlayer insulating film 207 or the like. Therefore, a method of stopping the CMP, not the time designation, but the flattening of the interlayer film on the wiring is disclosed in JP-A-60-398.
Indicated at 35.

This method is shown in FIGS. 8 (a), 8 (b) and 8 (c). Reference numerals 341 and 342 denote trench isolation portions, in which a filling material 307 is buried. 303 is a nitride film. Perform CMP with this shape, and embed material 3
07 is removed to obtain the shape shown in FIG. At this time, the polishing speed of the nitride film 303 is lower than that of the oxide film 302, and the CMP is stopped when the nitride film 303 is exposed on the surface.
The filling in the trench is completed.

[0007]

When the interlayer film on the gate electrode is flattened by the method of the conventional example 1, the CMP is performed with a designated time. However, in CMP, the CMP processing time changes depending on the conditions of the base and the like, and the processing time also changes depending on the number of processed sheets. If planarization is performed in this state, the interlayer film thickness will not be stable in a plane or between wafers, and in the worst case, the gate electrode may be exposed. Therefore, CMP is performed using a film having a lower polishing speed as a stopper film than the material to be polished, so that the flatness and the film thickness of the interlayer film can be stabilized.

[0008] However, the method of the prior art 2 is used to fill a groove in a flat and flat substrate, and the stopper film is provided on a flat and flat surface. In this method, by exposing the stopper film entirely, C
Stopping MP. Therefore, when the underlying layer is not flat as in the present invention and has an element region or a gate step, a stopper film is provided on a non-flat portion, and when the technique of the second conventional example is applied, the stopper film becomes When the entire surface is exposed, there is a problem that the step of the base is not relaxed and remains as it is.

Therefore, according to the present invention, by providing the stopper film, it is possible to prevent the variation in the conditions of the CMP from being reflected on the flattened shape, and to provide a good flat surface even when the base material of the CMP is not flat. It is intended to be obtained.

[0010]

In order to solve the above-mentioned problems, according to the present invention, a step of forming an element isolation region having a predetermined height on a surface of a semiconductor substrate and a step of depositing a conductive film at least above the element isolation region are provided. Manufacturing a semiconductor device including: a step of depositing an insulating film over a conductive film; a step of depositing an interlayer insulating film after etching the conductive film and the insulating film; and a step of polishing the interlayer insulating film to a flat surface. The method
A method was employed in which the insulating film was formed of a material having a lower polishing rate than that of the interlayer insulating film, and the insulating film was used as a polishing stop boundary in the step of polishing the interlayer insulating film.
At that time, a polishing step can be performed until the surface of the insulating film is exposed. Preferably, the insulating film is a nitride film. Also, the polishing step is very preferably a chemical mechanical polishing step. In addition, the conductive film and the insulating film having a low polishing rate can be patterned in the same photolithography step. Further, in the present invention, a step of forming an element isolation region of a predetermined height on the surface of the semiconductor substrate,
Depositing a first conductive film at least above the device isolation region, depositing an insulating film over the first conductive film, depositing an interlayer insulating film after etching the conductive film and the insulating film, A method for manufacturing a semiconductor device, comprising: a step of opening a contact in a predetermined region of an insulating film; a step of depositing a second conductive film filling the contact; and a step of polishing an interlayer insulating film to a flat surface. It is also possible to adopt a method in which the film is formed of a material having a lower polishing rate than the interlayer insulating film and the second conductive film, and the insulating film is used as a polishing stop boundary in the step of polishing the interlayer insulating film. . At that time, a polishing step can be performed until the surface of the insulating film is exposed. Further, the insulating film may be a nitride film. Also, the polishing step is very preferably a chemical mechanical polishing step. In addition, the conductive film and the insulating film having a low polishing rate can be patterned in the same photolithography step.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a sectional view of a semi-plant device manufactured by applying the present invention. An element isolation oxide film (element isolation region) 102 is formed on a P-type silicon substrate (semiconductor substrate) 101, and a gate lower electrode (conductive film) 104 and a gate upper electrode (conductive film) are formed on a gate insulating film 103.
An insulating film (stopper nitride film) 106 for a polishing stopper is formed thereon. An interlayer insulating film 107 is deposited thereon and planarized by CMP (chemical mechanical polishing).

FIGS. 9 to 13 show a manufacturing method according to the first embodiment of the present invention in order of steps. FIG. 9 shows an element isolation oxide film 1 on a semiconductor substrate 101.
02 is formed. As shown in FIG. 10, a gate oxide film 103 is formed thereon, and polysilicon is deposited as a gate lower electrode 104 at 1000 DEG and WSi as a gate upper electrode 105 is deposited at 1000 DEG over the entire surface. A film 106 is deposited at 1000 °.

Next, a resist 110 is applied thereon, exposed, and patterned. FIG. 11 shows the state at this time.

Next, the stopper nitride film 106, the gate upper electrode 105 and the gate lower electrode 104 are etched using the resist 110 as a mask. FIG. 12 shows the state at this time.

Since the nitride film 106 serving as a stopper is patterned at the same time as the gate electrode, no special PR and etching steps are required, and the number of steps required for device formation does not increase at all.

Next, as shown in FIG.
07 is deposited.

Next, the interlayer insulating film 107 is polished by CMP. At this time, when the nitride film 106 on the gate upper electrode 105 formed on the element isolation oxide film 102 is exposed, the CMP is stopped, and an interlayer insulating film is formed on the nitride film 106 on the gate electrode directly above the substrate 101. 107 remains to enable flattening. The state at this time corresponds to FIG.

Next, a second embodiment of the present invention will be described.
Since the steps up to the formation of the gate electrode and the formation of the interlayer film are the same as those in the first embodiment, the subsequent steps will be described. FIG.
Reference numeral 4 denotes a portion where the interlayer insulating film 107 is formed.

Next, as shown in FIG.
An opening is formed in the contact 151 of the wiring to be formed on the layer 07.

Next, as shown in FIG.
A material for embedding 1, here, polysilicon 152 is deposited.

Next, CMP is performed to perform flattening. FIG. 17 shows the shape at this time. Also in this case, the first embodiment
Similarly, the interlayer insulating film 107 stops at the nitride film 106 deposited on the gate electrode and can be planarized.

The buried polysilicon 152 is
Anything outside the contact 151 is polished and removed,
Plug-shaped polysilicon 15 remaining only in the contact
3 is obtained.

In the present embodiment, the silicon nitride film 106 is used as a CMP stopper film.
07 is different from the polishing speed, and other insulating films can be used as long as the stopper film has a low polishing speed.

With this process, the nitride film is simultaneously PR-etched when the gate electrode is formed, so that the gate electrode and the stopper nitride film can be formed online. Also, since the stopper nitride film is not specially formed, P
The R number does not increase, but only the formation of the stopper film increases in the process.

[0025]

As described above, according to the present invention, the CM
In the step of flattening the interlayer film using P, flattening can be stably performed using a nitride stopper film, and the stopper film is formed on the gate electrode at the same time as the gate electrode. The process does not increase.

Also, the embedding of the contact plug can be performed simultaneously with the step of flattening, and can be formed stably. Further, even if the underlayer of the material for performing the CMP is not flat, the CMP is stopped when the stopper film is first exposed during the CMP, so that a flat interlayer film shape can be obtained without depending on the underlayer shape.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of a semiconductor memory device manufactured by applying the manufacturing method of the present invention.

FIG. 2 is a cross-sectional view for explaining a first example of a conventional method for manufacturing a semiconductor memory device in the order of steps.

FIG. 3 is a cross-sectional view illustrating a first example of a conventional method of manufacturing a semiconductor memory device in the order of steps.

FIG. 4 is a sectional view for explaining a first example of a conventional method for manufacturing a semiconductor memory device in the order of steps;

FIG. 5 is a cross-sectional view illustrating a first example of a conventional method of manufacturing a semiconductor memory device in the order of steps.

FIG. 6 is a cross-sectional view for explaining a first example of a conventional method for manufacturing a semiconductor memory device in the order of steps.

FIG. 7 is a sectional view for explaining a first example of a conventional method for manufacturing a semiconductor memory device in the order of steps.

FIG. 8 is a cross-sectional view illustrating a second example of a conventional method for manufacturing a semiconductor memory device in the order of steps.

FIG. 9 is a sectional view illustrating a first embodiment of a method of manufacturing a semiconductor memory device according to the present invention in the order of steps.

FIG. 10 is a sectional view illustrating a first embodiment of a method of manufacturing a semiconductor memory device according to the present invention in the order of steps.

FIG. 11 is a sectional view illustrating a first embodiment of a method of manufacturing a semiconductor memory device according to the present invention in the order of steps.

FIG. 12 is a cross-sectional view for explaining the first embodiment of the method for manufacturing the semiconductor memory device of the present invention in the order of steps.

FIG. 13 is a sectional view illustrating a first embodiment of a method of manufacturing a semiconductor memory device according to the present invention in the order of steps.

FIG. 14 is a sectional view illustrating a second embodiment of the method of manufacturing the semiconductor memory device of the present invention in the order of steps.

FIG. 15 is a cross-sectional view for explaining a second embodiment of the method of manufacturing the semiconductor memory device according to the present invention in the order of steps.

FIG. 16 is a sectional view illustrating a second embodiment of the method of manufacturing the semiconductor memory device of the present invention in the order of steps.

FIG. 17 is a sectional view illustrating a second embodiment of the method of manufacturing the semiconductor memory device of the present invention in the order of steps.

[Explanation of symbols]

 101, 201, 301 Silicon substrate 102, 202 Field oxide film (element isolation region) 103, 203 Gate oxide film 104, 204 Gate lower electrode (conductive film) 105, 205 Gate upper electrode (conductive film) 106, 303 Stopper nitride film (Insulating film) 107, 207 Interlayer insulating film 110, 206 Resist 151 Bit contact 152 Polysilicon 153 Polycon plug 302 Silicon oxide film 305 Channel stopper region 306 Insulating film 307 Filling material 308 Depression 341, 342 Groove

Claims (10)

[Claims] A step of forming an element isolation region having a predetermined height on a surface of a semiconductor substrate; a step of depositing a conductive film at least above the element isolation region; and a step of depositing an insulating film over the conductive film. A method of manufacturing a semiconductor device, comprising: a step of depositing an interlayer insulating film after etching the conductive film and the insulating film; and a step of polishing the interlayer insulating film to a flat surface. A method for manufacturing a semiconductor device, comprising: forming an insulating film from a material having a low polishing rate; and using the insulating film as a polishing stop boundary in a step of polishing an interlayer insulating film. 2. The method according to claim 1, wherein a polishing process is performed until a surface of the insulating film is exposed. 3. The method according to claim 1, wherein said insulating film is a nitride film. 4. The method according to claim 1, wherein said polishing step is a chemical mechanical polishing step. 5. The method of manufacturing a semiconductor device according to claim 1, wherein said conductive film and said insulating film having a low polishing rate are patterned in the same photolithography step. . 6. A step of forming an element isolation region having a predetermined height on a surface of a semiconductor substrate, a step of depositing a first conductive film at least above the element isolation region, and depositing an insulating film over the first conductive film. Forming a conductive film, depositing an interlayer insulating film after etching the conductive film and the insulating film, opening a contact in a predetermined region of the interlayer insulating film, and depositing a second conductive film filling the contact. And a step of polishing the interlayer insulating film to a flat surface, the method comprising the steps of:
A method for manufacturing a semiconductor device, comprising: forming a material with a lower polishing rate than a conductive film; and using the insulating film as a polishing stop boundary in a step of polishing an interlayer insulating film. 7. The method of manufacturing a semiconductor device according to claim 6, wherein a polishing step is performed until a surface of said insulating film is exposed. 8. The method for manufacturing a semiconductor device according to claim 1, wherein said insulating film is a nitride film. 9. The method according to claim 6, wherein the polishing step is a chemical mechanical polishing step. 10. The method of manufacturing a semiconductor device according to claim 6, wherein said conductive film and said insulating film having a low polishing rate are patterned in the same photolithography step. .