JPH11162165A - Semiconductor memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor memory device which realizes a low power consumption and stabilization of operation and can switch one of high- speed operation and low power consumption operation to the other according to the purpose of use. SOLUTION: In a semiconductor memory device in which a memory cell is selected in accordance with an address signal out of a plurality of memory cells and writing and reading are performed in and from the selected memory cell, there are provided an input circuit containing a latch circuit LATCH for fetching and holding a plurality of input signals input according to a clock signal CLK supplied from an external terminal; and a logic stage for decoding the input signal fetched into the latch circuit, and operation control signals required for selection, write or read of the memory cell are generated.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, such as a synchronous dynamic RAM (random access memory) that decodes a command input in synchronization with a clock to form an operation control signal. The present invention relates to a technology effective for use in a semiconductor memory device.

[0002]

2. Description of the Related Art A synchronous DRAM is known in which a control signal is input and data is input / output in response to a clock signal supplied from an external terminal. In a conventional synchronous DRAM, a control signal or an address signal as a command is input before a rising edge of a clock signal has a setup time. The control signal thus input is immediately supplied by the command decoder, and the mode is set here.

[0003]

SUMMARY OF THE INVENTION In the present inventors, since the synchronous DRAM as described above always takes in a command inputted and decodes it, a system equipped with it is used. At
It has been noticed that current consumption increases because the input circuit and the decoder continue to operate meaninglessly in response to a change in an external signal other than the decoding of the original command for the synchronous DRAM. In addition, since the input circuit and the decoder circuit inevitably generate noise on the power supply line and the ground line when the input circuit and the decoder circuit operate, the small read signal is amplified at the timing of amplifying the signal with a highly sensitive sense amplifier. We have also noticed that the noise generation due to the meaningless operation of the input circuit and the decoder circuit deteriorates the operation margin.

An object of the present invention is to provide a semiconductor memory device which realizes low power consumption and stable operation. Another object of the present invention is to provide a semiconductor memory device capable of switching between high-speed operation and low power consumption according to the purpose of use. Another object of the present invention is to provide a liquid crystal drive circuit in which the occurrence of shadow wing is reduced by using the above constant current. The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0005]

The following is a brief description of an outline of a typical invention among the inventions disclosed in the present application. That is, in a semiconductor memory device that selects a memory cell from among a plurality of memory cells in accordance with an address signal and writes or reads data to or from the selected memory cell, a plurality of memory cells input in response to a clock signal supplied from an external terminal. An input circuit including a latch circuit that captures and holds the input signal of the above, and a logic stage that decodes the input signal captured by the latch circuit is provided, and an operation control signal required for selecting, writing, or reading the memory cell, etc. To form

[0006]

FIG. 1 shows a synchronous DRAM (hereinafter simply referred to as an SDRAM) to which the present invention is applied.
1 is an overall block diagram of one embodiment. Although not particularly limited, the SDRAM shown in FIG. 1 is formed on one semiconductor substrate such as single crystal silicon by a known semiconductor integrated circuit manufacturing technique.

The SDRAM of this embodiment has a memory array 200A forming memory bank 0 and a memory bank 1
Is provided. Each of the memory arrays 200A and 200B includes dynamic memory cells arranged in a matrix. According to the figure, the selection terminals of the memory cells arranged in the same column are coupled to a word line (not shown) for each column. The data input / output terminals of the memory cells arranged in the same row are connected to complementary data lines (not shown) for each row.

One word line (not shown) of the memory array 200A is driven to a selected level in accordance with the result of decoding a row address signal by a row (row) decoder 201A. A complementary data line (not shown) of the memory array 200A is an I / O line 2 including a sense amplifier and a column selection circuit.
02A. The sense amplifier in the I / O line 202A including the sense amplifier and the column selection circuit is an amplification circuit that detects and amplifies a minute potential difference appearing on each complementary data line by reading data from a memory cell. The column switch circuit in this case is a switch circuit for selecting complementary data lines individually and conducting to the complementary I / O lines. The column switch circuit is selectively operated according to the result of decoding the column address signal by the column decoder 203A.

Similarly, a row decoder 201B, an I / O line 202B including a sense amplifier and a column selection circuit, and a column decoder 203B are provided on the memory array 200B side. The complementary I / O lines are write buffers 214A and 214B.
And the input terminals of the main amplifiers 212A and 212B. The main amplifier (or sense circuit) 21
Although the output signals of 2A and 2B are not particularly limited,
The output signal of the latch / register 213 is transmitted to the input terminal of the register 213 and output from an external terminal via the output buffer 211. The write signal input from the external terminal is transmitted to the input terminals of the write buffers 214A and 214B via the input buffer 210.
The external terminal is a data input / output terminal for outputting data D0 to D15 of 16 bits, although not particularly limited.

Address signals A0 to A9 supplied from the address input terminals are taken into a column address buffer 205 and a row address buffer 206 in an address multiplex format. The supplied address signal is held in each buffer. The row address buffer 206 takes in the refresh address signal output from the refresh counter 208 as a row address signal in the refresh operation mode. The output of the column address buffer 205 is supplied as preset data of a column address counter 207, and the column (column) address counter 207 outputs a column address signal as the preset data or a column address signal according to an operation mode specified by a command described later. A value obtained by sequentially incrementing the column address signal is output to the column decoders 203A and 203B.

A controller 2 shown by a dotted line in FIG.
09 is, although not particularly limited, a clock signal CLK, a clock enable signal CKE, and a chip select signal / C.
S, a column address strobe signal / CAS (symbol / means that a signal added thereto is a row enable signal), a row address strobe signal / RAS,
An external control signal such as a write enable signal / WE and control data from address input terminals A0 to A9 are supplied, and the operation mode of the SDRAM and the circuit block The mode register 10 and the command decoder 2 form an internal timing signal for controlling the operation.
0, a timing generation circuit 30, a clock buffer 40, and, although not particularly limited, a synchronous clock generation circuit 50.

The clock signal CLK is input to the synchronous clock generation circuit via the clock buffer 40 as described above, and is synchronized with the internal clock formed here. Although the internal clock is not particularly limited, a timing signal int.CLK for activating the output buffer 211 is used.
The signal passed through the clock buffer is directly transmitted to other circuits. Other external input signals are made significant in synchronization with the rising edge of the internal clock signal.

The chip select signal / CS instructs the start of a command input cycle by its low level. When the chip select signal / CS is at a high level (chip is not selected) and other inputs have no meaning. However, internal operations such as a memory bank selection state and a burst operation, which will be described later, are not affected by the change to the chip non-selection state. / RAS, / CAS and / WE signals are normal DR
The function is different from that of the corresponding signal in AM, and is a significant signal when defining a command cycle described later.

The clock enable signal CKE is a signal for indicating the validity of the next clock signal.
If E is at the high level, the next rising edge of the clock signal CLK is valid, and if it is at the low level, it is invalid. Although not shown, in the read mode,
When an external control signal / OE for controlling output enable for the output buffer 211 is provided, the signal / OE is also supplied to the controller 209. When the signal is at a high level, for example, the output buffer 211 is in a high output impedance state. To be.

The row address signal is a clock signal C
It is defined by the levels of A0 to A8 in a later-described row address strobe / bank active command cycle synchronized with the rising edge of LK (internal clock signal).

The address signal A9 is regarded as a bank selection signal in the row address strobe / bank active command cycle. That is, when the input of A9 is at low level, memory bank 0 is selected, and when it is at high level, memory bank 1 is selected. The selection control of the memory bank is not particularly limited, but only the row decoder of the selected memory bank is activated, all the column switch circuits of the unselected memory bank are not selected, the input buffer 210 and the output buffer of the selected memory bank only. It can be performed by processing such as connection to 211.

An address signal A8 in a precharge command cycle described later indicates a mode of a precharge operation for a complementary data line or the like, and its high level indicates that both memory banks are to be precharged. The low level indicates that one of the memory banks indicated by the address signal A9 is to be precharged.

The column address signal is defined by the levels of A0 to A7 in a read or write command (column address / read command, column address / write command described later) cycle synchronized with the rising edge of the clock signal CLK (internal clock). Is done.
The column address defined in this way is used as a start address for burst access.

Next, the SDR specified by the command
The main operation mode of the AM will be described. (1) Mode register set command (Mo) This command is for setting the mode register 30. The command is specified by / CS, / RAS, / CAS, / WE = low level, and the data to be set (register set data ) Are given via A0-A9. Although the register set data is not particularly limited,
Burst length, CAS latency, write mode, and the like are set. Although not particularly limited, the settable burst length is 1, 2, 4, 8, and full page, the settable CAS latency is 1, 2, 3, and the settable write modes are burst write and Single light.

In the read operation specified by a column address read command, which will be described later, the CAS latency is determined by the fall of / CAS and the output buffer 21.
This indicates how many cycles of the internal clock signal are to be consumed before the output operation of 1. Until the read data is determined, an internal operation time for data read is required, and this is set in accordance with the operating frequency of the internal clock signal. In other words, when using a high-frequency internal clock signal, set the CAS latency to a relatively large value, and when using a low-frequency internal clock signal, set the CAS latency to a relatively small value. I do.

(2) Row address strobe / bank active command (Ac) This is a command for validating a row address strobe and selecting a memory bank by A9.
S, / RAS = low level, / CAS, / WE = high level. At this time, the address supplied to A0 to A8 is taken as a row address signal, and the signal supplied to A9 is taken as a memory bank selection signal. .
The fetch operation is performed in synchronization with the rising edge of the internal clock signal as described above. For example, when the command is specified, a word line in the memory bank specified by the command is selected, and the memory cells connected to the word line are electrically connected to the corresponding complementary data lines. Here, it should be understood that synchronization does not mean a strict sense of phase matching, but includes a slight phase shift.

(3) Column Address Read Command (Re) This command is a command necessary for starting a burst read operation and a command for giving an instruction of a column address strobe. / CS, / CAS =
Instructed by low level, / RAS, / WE = high level. At this time, column addresses supplied to A0 to A7 are taken in as column address signals. The fetched column address signal is supplied to the column address counter 207 as a burst start address.

In the burst read operation instructed thereby, a memory bank and a word line in the memory bank are selected in a row address strobe / bank active command cycle, and the memory cell of the selected word line is The data is sequentially selected according to the address signal output from the column address counter 207 in synchronization with the internal clock signal, and is continuously read. The number of data to be continuously read is the number specified by the burst length. The start of reading data from the output buffer 211 is performed after waiting for the number of cycles of the internal clock signal defined by the CAS latency.

(4) Column Address Write Command (Wr) When a burst write is set in the mode register 10 as a mode of the write operation, it is a command necessary to start the burst write operation, and the write operation of the write operation is performed. As a mode, when the single write is set in the mode register 10, the command is a command necessary to start the single write operation. Further, the command gives an instruction of a column address strobe in single write and burst write.

The command is: / CS, / CAS, / W
Instructed by E = low level and / RAS = high level. At this time, the addresses supplied to A0 to A7 are taken in as column address signals. The column address signal thus captured is supplied to the column address counter 207 as a burst start address in burst write. The procedure of the burst write operation instructed in this way is performed in the same manner as the burst read operation. However, there is no CAS latency in the write operation, and the capture of write data is started from the column address / write command cycle.

(5) Precharge command (Pr) This is a command to start a precharge operation for the memory bank selected by A8 and A9, and / C
S, / RAS, / WE = low level, / CAS = high level.

(6) Auto-refresh command This command is required to start auto-refresh, and includes commands / CS, / RAS, / CA
Instructed by S = low level, / WE, CKE = high level.

(7) Burst stop in full page command This command is required to stop the burst operation for a full page for all memory banks, and is ignored in burst operations other than the full page. This command is for / CS, / WE = low level, / RAS, / CA
Indicated by S = high level.

(8) No operation command (No
p) This is a command instructing that no substantial operation is performed, / CS = low level, / RAS, / CAS, / W
It is indicated by the high level of E.

In the SDRAM, when a burst operation is being performed in one memory bank, another memory bank is designated in the middle of the burst operation and a row address strobe / bank active command is supplied. The row address operation in the other memory bank is enabled without affecting the operation in one memory bank. For example, the SDRAM has means for internally holding data, addresses, and control signals supplied from the outside, and the held contents, particularly addresses and control signals, are not particularly limited, but may be held for each memory bank. It has become. Alternatively, data for one word line in a memory block selected by a row address strobe / bank active command cycle is held in a latch / register 213 for a read operation before a column-related operation. I have.

Therefore, as long as the data D0-D15 do not collide with the data input / output terminal of, for example, 16 bits, during execution of a command whose processing has not been completed, the command being executed is different from the memory bank to be processed. The internal operation can be started in advance by issuing a precharge command and a row address strobe / bank active command to the memory bank.

Since the SDRAM can input and output data, addresses, and control signals in synchronization with a clock signal CLK (internal clock signal), it is possible to operate a large-capacity memory similar to a DRAM at a high speed comparable to an SRAM. ,
By specifying the number of data to be accessed for one selected word line by the burst length, the selection state of the column system is sequentially switched by the built-in column address counter 207, and a plurality of data are accessed. Can be read or written continuously.

FIG. 2 is a block diagram showing one embodiment of the command decoder 20 of the SDRAM according to the present invention. The command decoder 20 of this embodiment includes a latch circuit LATCH receiving an internal command signal com, and a logic stage (mo) that decodes the latch circuit LATCH and determines an operation mode or the like.
de dec). The internal command signal com is formed by an input buffer (not shown) that receives a control signal supplied from an external terminal. That is, the command decoder 20 shown in FIG.
It comprises a latch circuit LATCH and a logic stage. The latch circuit LATCH captures and latches the internal command signal com passed through the input buffer at the rising edge of the clock signal CLK.

FIG. 3 is a waveform chart for explaining the operation of the command decoder shown in FIG. Only the valid commands A, B and C input during the setup time ts and hold time th corresponding to the rising edge of the clock signal CLK are latched by the latch circuit LA.
TCH holds. And one of the commands A
Indicates an operation mode, an operation mode signal is output correspondingly. Another command B to be subsequently input
And C are, for example, the no operation command (No.
p), which indicates that no substantial operation is performed, and does not output anything as a mode decoder output.

In this embodiment, only the input signal that changes during the setup time ts and the hold time th corresponding to the rising edge of the clock signal CLK is valid, and the remaining input signal is retained. Even if the input signal changes, the static C
In a logic stage (mode dec) constituted by a MOS circuit, the input signal does not change due to the interposition of the latch circuit LATCH, so that the current consumption is theoretically zero. That is,
According to this embodiment, the input signal transitions at most once /
Since it is limited to one clock, low power consumption can be achieved.

FIG. 4 is a block diagram showing another embodiment of the command decoder 20 of the SDRAM according to the present invention. In the embodiment of FIG. 2, since the clock signal CLK is used as a command input latch to reduce power consumption, the logic circuit is required to output an output signal at the rising edge of the clock signal CLK. Is delayed by the signal propagation delay time.

Therefore, in the command decoder of this embodiment, a function is added for switching between the above-described one in which low power consumption is prioritized and the one in which high-speed operation is prioritized. For this reason, in the command decoder 20 as shown in FIG. 2, a latch circuit is also added to the output stage of the logic stage. Latch circuit L provided on the input side
A switch circuit is provided to switch and use the ATCH and the latch added to the output stage. This switch circuit switches between supplying the clock signal CLK to the preceding latch circuit LATCH or supplying the clock signal CLK to the output stage. The latch circuit LATCH and the latch circuit forming the output stage operate as a simple buffer circuit when the clock signal CLK is not supplied.

Although not particularly limited, a D-type flip-flop circuit is formed using two well-known clocked inverter circuits and two through latch circuits formed using CMOS transmission gates. This D-type flip-flop circuit is composed of a master circuit that captures data and a slave circuit that retains data. The slave circuit retains and outputs data in the previous clock cycle, and outputs the data of the master circuit. At the same time as the inlet is closed, the data inlet of the slave circuit is opened to take in the data of the master circuit and update the output data.

When the clock signal CLK is not supplied, the level of the complementary clock signal supplied to the clocked inverter circuit or the CMOS transmission gate is fixed, and for example, the clocked inverter circuit inserted in the signal transmission path is connected to the inverter. By operating the circuit as a circuit and turning on the CMOS transmission gate, an operation as a buffer circuit in which an input signal is directly transmitted from an output terminal can be performed.

FIG. 5 shows that the latch circuit LATCH provided on the input side is operated as a simple buffer circuit.
A waveform diagram for explaining an operation when the output stage is operated as a latch circuit is shown. In this embodiment, since the command is input to the logic stage (mode dec) through the input buffer and the latch circuit functioning as the buffer circuit, the command A valid at the timing when the clock signal CLK changes from high level to low level.
Can be immediately output.
Thereby, the operation can be speeded up.

However, when a meaningless change in the input command that does not correspond to the clock signal CLK occurs,
Correspondingly, the power consumption increases because the latch circuit LATCH and the logic stage respond to the operation current. Conversely, the latch circuit LATC provided on the input side
When H is operated as a latch circuit as described above and the output stage is operated as a simple buffer circuit, the transition of the input signal in the latch circuit LATCH and the logic stage is the maximum as shown in FIG. Since power consumption is limited to once per clock, power consumption is reduced.

In other words, the switching by the switch circuit can be used for two purposes: a high-speed operation priority and a low-power consumption priority purpose. Can be used selectively. Further, even in the same system, high-speed operation is prioritized in the switch circuit between memory access by a high-speed microprocessor and memory access from a relatively low-speed device such as a direct access memory control device. Or a control signal for setting whether to give priority to low power consumption may be set by software.

FIG. 6 is a block diagram showing still another embodiment of the command decoder 20 of the SDRAM according to the present invention. In this embodiment, a chip select signal / CS is used to further reduce power consumption. That is, as understood from the above commands, all commands are conditioned on / CS being at low level. Therefore, it is necessary to supply the clock signal CLK to the latch circuit LATCH through the gate circuit controlled by the chip select signal / CS, in other words, to operate the latch circuit LATCH with the logical product of / CS and CLK to capture the clock signal CLK. The latch circuit LATCH and the logic stage operate only when an original command is input.

FIG. 7 is a waveform chart for explaining the operation of the command decoder shown in FIG. In this embodiment, the clock signal CLK is supplied to the latch circuit L only when the chip select signal / CS is set to the low level.
Only valid commands A and B supplied to the ATCH and input during the setup time ts and the hold time th corresponding to the rise thereof are latched by the latch circuit LATCH.
Holds. That is, even if the clock signal CLK changes from low level to high level between the valid commands A and B, the latch circuit LATCH keeps latching the command A because / CS is at high level. ing.

Therefore, even if a signal corresponding to the no operation command (Nop) is input in response to the clock signal CLK, the latch circuit LATCH and the logic stage stop responding thereto. Thus, synchronous D
Since the latch circuit LATCH and the logic stage do not operate in response to a change in the input signal that is meaningless for the RAM, further lower power consumption can be achieved.

FIG. 8 is a block diagram showing still another embodiment of the command decoder 20 of the SDRAM according to the present invention. In this embodiment, in order to further reduce power consumption, the chip select signal / C
S is used to control an input buffer that takes in other control signals. That is, in the embodiment of FIG. 5, the operation of the latch circuit LATCH and the logic stage is limited. However, when the control signal input from the external terminal changes, the input buffer circuit performs the operation correspondingly. Therefore, useless current is consumed here.

In order to reduce the power consumption in the input buffer, the output signal of the / CS input buffer is
Control signals constituting commands other than the / CS, for example, / RAS, / CAS, / WE, etc., are prohibited. Although not particularly limited, the input buffer is constituted by a clocked inverter circuit, supplies / CS to the clock terminal of the input buffer, and includes a P-channel MOSFET and an N-channel MOSFET which receive a clock signal when the / CS is made low. N-channel type MOSF which receives an input signal supplied from an external terminal when turned on
The operation of the CMOS inverter circuit including the ET and the P-channel MOSFET may be made effective.

When the clocked inverter circuit as described above is used, when the signal / CS is at a high level, the output is in a high impedance state (floating state),
If a problem occurs in the latch circuit LATCH of the next-stage circuit, an N-channel MOSFET that is turned on by the high level of the signal / CS is provided at the output section to forcibly fix the output signal to the low level. I just need.

FIG. 9 is a waveform chart for explaining the operation of the command decoder shown in FIG. In this embodiment, when the chip select signal / CS is set to the high level, the input control signal (input buffer enable) is set.
e) becomes low level and stops the operation of the input buffer. As a result, useless current consumption in the input buffer can be suppressed.

In this case, the chip select signal / CS supplied from the external terminal changes to low level,
The setup time ts (t2) is substantially reduced by the time t1 required for the CS buffer to set the internal signal / CS to the low level in response. Therefore, in order to secure the necessary setup time ts, the above-mentioned / C
It is necessary to increase the speed of the S buffer bus.

As described above, the operation limitation of the logic stage by the clock signal CLK, the operation limitation of the latch circuit and the logic stage by the chip select signal / CS and the clock signal, and the operation limitation of the input buffer as described above. In addition to the fact that the current consumption can be reduced, the noise generated in the power supply line and the ground line due to the current flowing when each of the above circuits operates is inevitably reduced. In particular, a synchronous DRAM uses a dynamic memory cell to amplify a minute potential change of a bit line due to a minute storage charge with a high-sensitivity sense amplifier. Have. For this,
The operation margin can be expanded by the operation restriction in the logic stage, the latch circuit, and the input buffer.

The operation and effect obtained from the above embodiment are as follows. (1) A semiconductor memory device that selects a memory cell from among a plurality of memory cells according to an address signal and writes or reads data to or from the selected memory cell is input in response to a clock signal supplied from an external terminal. An input circuit including a latch circuit for receiving and holding a plurality of input signals, and a logic stage for decoding the input signal captured by the latch circuit are provided, and operation control necessary for selecting, writing, or reading the memory cell, etc. By forming a signal, useless current consumption due to a meaningless input signal that does not correspond to a clock signal can be suppressed, so that an effect that power consumption can be reduced can be obtained.

(2) An output latch circuit and a latch control circuit are further provided on the output side of the logic stage, and one of the latch circuit included in the input circuit and the output latch circuit is provided by the latch control circuit. However, when the latch operation is performed according to the clock signal, the other latch circuit controls the switching of the operation of directly transmitting the input signal to the output so that the high-speed operation and the low power consumption operation corresponding to the intended use can be performed. Can be switched.

(3) The latch circuit uses an edge trigger type in which an input signal is fetched and latched at a timing when the clock signal changes from one level to the other level, thereby affecting the original operation. The power consumption can be effectively reduced without being affected by the pulse duty of the clock pulse.

(4) By supplying a clock signal formed by ANDing a chip select signal and a clock signal supplied from an external terminal to a latch circuit included in the input circuit, it is possible to cope with an original valid command. Only after that, the latch circuit and the logic stage can be operated, so that an effect of further reducing power consumption can be obtained.

(5) In the input circuit, an input buffer receiving an input signal other than the chip select signal supplied from an external terminal is provided with an input buffer input from the external terminal when the chip select signal is made valid. 5. The semiconductor memory device according to claim 4, wherein an internal signal corresponding to the signal is formed and transmitted to said latch circuit.

(6) As described above, an effect is obtained that a synchronous DRAM with low power consumption, stable operation, and improved usability can be obtained.

Although the invention made by the inventor has been specifically described based on the embodiments, the invention of the present application is not limited to the above embodiments, and various modifications can be made without departing from the gist of the invention. Needless to say. For example, a synchronous DRAM may have four memory banks in addition to one having two memory banks. The control signal specifying the command may be a signal for adding a control signal as needed. The present invention can be widely used not only for synchronous DRAMs but also for semiconductor memory devices of a system in which a control signal is input corresponding to a clock signal and the mode is set by decoding the control signal.

[0059]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows. That is, in a semiconductor memory device that selects a memory cell from among a plurality of memory cells in accordance with an address signal and writes or reads data to or from the selected memory cell, a plurality of memory cells input in response to a clock signal supplied from an external terminal. An input circuit including a latch circuit that captures and holds the input signal of the above, and a logic stage that decodes the input signal captured by the latch circuit is provided, and an operation control signal required for selecting, writing, or reading the memory cell, etc. , Power consumption can be reduced because useless current consumption due to a meaningless input signal that does not correspond to the clock signal can be suppressed.

[Brief description of the drawings]

FIG. 1 is an overall block diagram showing an embodiment of a synchronous DRAM to which the present invention is applied.

FIG. 2 is a block diagram showing one embodiment of a command decoder 20 of the SDRAM according to the present invention.

FIG. 3 is a waveform chart for explaining an operation of the command decoder shown in FIG. 2;

FIG. 4 is a block diagram showing another embodiment of the command decoder 20 of the SDRAM according to the present invention.

5 is a latch circuit LATC provided on the input side in FIG.
FIG. 9 is a waveform diagram for explaining an operation when H operates as a simple buffer circuit and an output stage operates as a latch circuit.

FIG. 6 is a block diagram showing still another embodiment of the command decoder 20 of the SDRAM according to the present invention.

FIG. 7 is a waveform chart for explaining an operation of the command decoder shown in FIG. 6;

FIG. 8 is a block diagram showing still another embodiment of the command decoder 20 of the SDRAM according to the present invention.

FIG. 9 is a waveform chart for explaining the operation of the command decoder shown in FIG. 8;

[Explanation of symbols]

10: mode register, 20: command decoder, 30
... timing generation circuit, 30 ... clock buffer, 50
... Synchronous clock generation circuit, 200A, 200B ... Memory array, 201A, 201B ... Row decoder, 202
A, 202B: sense amplifier and column selection circuit, 20
3A, 203B: column decoder, 205: column address buffer, 206: row address buffer, 207
... column address counter, 208 ... refresh counter, 209 ... controller, 210 ... input buffer,
211: output buffer, 212A, B: main amplifier,
213: latch / register, 214A, B: write buffer, LATCH: latch circuit, mode dec: logic stage (mode decoder),

Continued on the front page (72) Inventor Masayuki Nakamura 2326 Imai, Ome-shi, Tokyo Inside the Device Development Center, Hitachi, Ltd. (72) Inventor Shoji Wada 3-1-1 Higashi-Koikekubo, Kokubunji-shi, Tokyo Hitachi ULSI・ Inside Engineering Co., Ltd. (72) Inventor Kazuhiko Kajiya 2326 Imai, Ome-shi, Tokyo Inside Device Development Center, Hitachi, Ltd.

Claims (6)

[Claims] A plurality of memory cells; an address selection circuit that selects a memory cell according to an address signal among the plurality of memory cells; a circuit that writes or reads data to or from the selected memory cell; An input circuit including a latch circuit that captures and holds a plurality of input signals that are input corresponding to the clock signal to be input; and selects the memory cell by decoding the input signal captured by the latch circuit of the input circuit. And a logic stage for forming an operation control signal necessary for writing or reading. 2. An output latch circuit and a latch control circuit are further provided on an output side of the logic stage. The latch control circuit includes a latch circuit included in an input circuit corresponding to a predetermined switching control signal and the latch circuit. When one of the output latch circuits performs a latch operation in accordance with the clock signal, the other latch circuit controls switching of an operation of transmitting an input signal to an output as it is. Item 1. The semiconductor memory device according to Item 1. 3. The semiconductor memory according to claim 1, wherein said latch circuit fetches and latches an input signal at a timing when a clock signal changes from one level to another level. apparatus. 4. A clock signal supplied to a latch circuit included in the input circuit is formed by a logical product of a chip select signal supplied from an external terminal and a clock signal. Item 1. The semiconductor memory device according to Item 1. 5. An input buffer for receiving an input signal other than the chip select signal supplied from an external terminal of the input circuit, wherein the input signal input from the external terminal when the chip select signal is made valid. 5. The semiconductor memory device according to claim 4, wherein an internal signal corresponding to the above is formed and transmitted to said latch circuit. 6. The memory cell according to claim 1, wherein said memory cell is a dynamic memory cell, and said logic stage constitutes a command decoder in a synchronous DRAM. The semiconductor memory device according to claim 4 or claim 5.