JPH11160368A - Current detection circuit - Google Patents
Current detection circuitInfo
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- JPH11160368A JPH11160368A JP34854597A JP34854597A JPH11160368A JP H11160368 A JPH11160368 A JP H11160368A JP 34854597 A JP34854597 A JP 34854597A JP 34854597 A JP34854597 A JP 34854597A JP H11160368 A JPH11160368 A JP H11160368A
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- current
- detection
- transistor
- resistor
- circuit
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- Control Of Voltage And Current In General (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、検出抵抗を電流検
出線路に直列に挿入して電流検出を行う電流検出回路に
係り、とくにＤＣ−ＤＣコンバータの過電流保護回路等
に用いることのできる電流検出回路に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a current detection circuit for detecting a current by inserting a detection resistor in series with a current detection line, and more particularly to a current detection circuit which can be used for an overcurrent protection circuit of a DC-DC converter. It relates to a detection circuit.
【０００２】[0002]
【従来の技術】従来、レギュレータの保護回路として、
カレントミラー回路を応用した電流検出回路が特開昭６
４−６７６１３号で提案されている。図９はそこで開示
されている電流検出回路であり、トランジスタＱ1，Ｑ2
のベースを共通に接続したカレントミラー回路のＱ1，
Ｑ2のエミッタを検出抵抗Ｒ1の両端にそれぞれ接続しか
つＱ2のコレクタを定電流源１に接続して、前記検出抵
抗Ｒ1を電流検出線路に直列に挿入している。2. Description of the Related Art Conventionally, as a protection circuit for a regulator,
A current detection circuit using a current mirror circuit is disclosed in
No. 4-67613. FIG. 9 shows a current detection circuit disclosed therein, which includes transistors Q1 and Q2.
Q1 of the current mirror circuit with the bases connected in common
The emitter of Q2 is connected to both ends of the detection resistor R1 and the collector of Q2 is connected to the constant current source 1, and the detection resistor R1 is inserted in series with the current detection line.
【０００３】図９において、電流検出線路に流れる被検
出電流をＩin、定電流源１の電流をＩ1、トランジスタ
Ｑ1のコレクタより流出する検出信号電流（出力電流）
をＩoutとしたとき、ＩinとＩoutとの関係は以下の各式
により導出される。In FIG. 9, the detected current flowing through the current detection line is Iin, the current of the constant current source 1 is I 1 , and a detection signal current (output current) flowing out of the collector of the transistor Q1.
Is Iout, the relationship between Iin and Iout is derived by the following equations.
【０００４】Ｉout≒ＩE(Q1) （但し、ＩE(Q1)：Ｑ1の
エミッタ電流） とすると、 Ｉout＝ＩS1ｅｘｐ｛（ｑＶBE(Q1)／ｋＴ）−１｝ …(1) （但し、ＩS1：Ｑ1の飽和電流、ＶBE(Q1)：Ｑ1のベー
ス、エミッタ間電圧、ｑ：電子の電荷量、ｋ：ボルツマ
ン定数、Ｔ：絶対温度） Ｉ1≒ＩE(Q2) （但し、ＩE(Q2)：Ｑ2のエミッタ電流）
とすると、 Ｉ1＝ＩS2ｅｘｐ｛（ｑＶBE(Q2)／ｋＴ）−１｝ …(2) （但し、ＩS2：Ｑ2の飽和電流、ＶBE(Q2)：Ｑ2のベー
ス、エミッタ間電圧） ＶBE(Q2)＝（ｋＴ／ｑ）｛ｌｎ（Ｉ1／ＩS2）＋１｝ …(3) また、ＶBE(Q1)は次式でも表せる。 ＶBE(Q1)＝ＶBE(Q2)＋ＩinＲ1 …(4) (4)式に(3)式を代入すると、 ＶBE(Q1)＝（ｋＴ／ｑ）｛ｌｎ（Ｉ1／ＩS2）＋１｝＋ＩinＲ1 …(5) モノリシックの対のトランジスタをＱ1，Ｑ2に使用する
と、 ＩS1≒ＩS2 …(6) といえる。(5)式及び(6)式を(1)式に代入すると、 Ｉout＝ＩS1ｅｘｐ｛ｌｎ（Ｉ1／ＩS2）＋１＋（ｑ／ｋＴ）ＩinＲ1−１｝ ＝（ＩS1／ＩS2）Ｉ1ｅｘｐ｛（ｑ／ｋＴ）ＩinＲ1｝ ＝Ｉ1ｅｘｐ｛（ｑ／ｋＴ）Ｒ1Ｉin｝ …(7) (7)式より検出信号電流Ｉoutは被検出電流Ｉinに対して
指数関数的に変化することになる。[0004] Iout ≒ I E (Q1) (where, I E (Q1): Q1 emitter current) of the to, Iout = I S1 exp {( qV BE (Q1) / kT) -1} ... (1) ( Where I S1 : saturation current of Q1, V BE (Q1) : base-emitter voltage of Q1, q: charge of electrons, k: Boltzmann constant, T: absolute temperature. I 1 IE (Q2) ( However, IE (Q2) : emitter current of Q2)
Then, I 1 = I S2 exp {(qV BE (Q2) / kT) −1} (2) (where, I S2 : saturation current of Q2, V BE (Q2) : base-emitter voltage of Q2 V BE (Q2) = (kT / q) {ln (I 1 / I S2 ) +1} (3) V BE (Q1) can also be expressed by the following equation. V BE (Q1) = V BE (Q2) + IinR1 (4) By substituting equation (3) into equation (4), V BE (Q1) = (kT / q) ｛ln (I 1 / I S2 ) +1 } + IinR1 ... (5) with the transistor Q1, Q2 of the pair of monolithic, I S1 ≒ I S2 ... can be said that (6). (5) and are substituted into the expression (6) (1), Iout = I S1 exp {ln (I 1 / I S2) +1+ (q / kT) IinR1-1} = (I S1 / I S2) I 1 exp {(q / kT ) IinR1} = I 1 exp {(q / kT) R1Iin} ... (7) (7) detection signal current Iout from the equation changes exponentially with respect to the detected current Iin Will be.
【０００５】図１０は図９の如き従来回路における被検
出電流Ｉinと検出信号電流（出力電流）Ｉoutとの関係
を表したグラフであり、検出抵抗Ｒ1一定の条件下で両
者は指数関数的な関係となっている。ここでは、検出抵
抗Ｒ1が標準値Ｒ1（typ）から最大値Ｒ1（max）〜最小
値Ｒ1（min）の範囲でばらつくものとして、標準値Ｒ1
（typ）、最大値Ｒ1（max）、最小値Ｒ1（min）のそれ
ぞれの場合について被検出電流Ｉinと検出信号電流Ｉou
tとの関係を示す曲線を描いている。FIG. 10 is a graph showing the relationship between the detected current Iin and the detection signal current (output current) Iout in the conventional circuit as shown in FIG. Relationship. Here, assuming that the detection resistor R1 varies from the standard value R1 (typ) to the maximum value R1 (max) to the minimum value R1 (min), the standard value R1
(Typ), the maximum value R1 (max), and the minimum value R1 (min) in each case, the detected current Iin and the detection signal current Iou
The curve showing the relationship with t is drawn.
【０００６】[0006]
【発明が解決しようとする課題】ところで、図１０から
わかるように、図９の従来回路では、ある被検出電流Ｉ
inに対して検出抵抗Ｒ1が僅かにばらついても検出信号
電流Ｉoutは大きく変化することになり、それを校正す
ることが困難であり（とくにＲ1の抵抗値に変更を加え
ることなく校正するのが難しい）、電流検出精度を向上
させることが難しい問題があった。By the way, as can be seen from FIG. 10, in the conventional circuit of FIG.
Even if the detection resistor R1 varies slightly with respect to in, the detection signal current Iout greatly changes, and it is difficult to calibrate it (especially, it is necessary to calibrate without changing the resistance value of R1). It is difficult to improve the current detection accuracy.
【０００７】本発明は、上記の点に鑑み、検出抵抗を流
れる被検出電流と検出信号電流との関係をリニアにし
て、検出抵抗のばらつきに起因する検出信号電流のばら
つきを校正可能とし、あわせて電流検出精度の向上を図
った電流検出回路を提供することを目的とする。In view of the above, the present invention makes the relationship between the current to be detected flowing through the detection resistor and the detection signal current linear, and makes it possible to calibrate the variation in the detection signal current caused by the variation in the detection resistor. It is an object of the present invention to provide a current detection circuit that improves the current detection accuracy.
【０００８】本発明のその他の目的や新規な特徴は後述
の実施の形態において明らかにする。[0008] Other objects and novel features of the present invention will be clarified in embodiments described later.
【０００９】[0009]
【課題を解決するための手段】上記目的を達成するため
に、本発明の電流検出回路は、第１及び第２のトランジ
スタのベースを共通に接続したカレントミラー回路の前
記第２のトランジスタのエミッタを検出抵抗の一端に接
続しかつコレクタを定電流源に接続し、前記第１のトラ
ンジスタのエミッタは直列抵抗を介して前記検出抵抗の
他端に接続し、前記検出抵抗を電流検出線路に直列に挿
入するとともに、前記検出抵抗に流れる被検出電流を前
記第１のトランジスタのコレクタ側にて検出する構成と
している。In order to achieve the above object, a current detecting circuit according to the present invention comprises an emitter of the second transistor in a current mirror circuit in which the bases of the first and second transistors are connected in common. Is connected to one end of a detection resistor, the collector is connected to a constant current source, the emitter of the first transistor is connected to the other end of the detection resistor via a series resistor, and the detection resistor is connected in series to a current detection line. And the detected current flowing through the detection resistor is detected on the collector side of the first transistor.
【００１０】前記電流検出回路において、前記第１のト
ランジスタのコレクタ側に前記第１のトランジスタと同
極性の第３のトランジスタを直列に挿入し、該第３のト
ランジスタのベースを前記第２のトランジスタのコレク
タに接続した構成としてもよい。In the current detection circuit, a third transistor having the same polarity as the first transistor is inserted in series on the collector side of the first transistor, and the base of the third transistor is connected to the second transistor. May be connected to the collector.
【００１１】[0011]
【発明の実施の形態】以下、本発明に係る電流検出回路
の実施の形態を図面に従って説明する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The embodiments of the current detection circuit according to the present invention will be described below with reference to the drawings.
【００１２】図１は本発明に係る電流検出回路の第１の
実施の形態であって、基本的な回路構成を示す。この電
流検出回路は、第１及び第２のＰＮＰトランジスタＱ
1，Ｑ2のベースを共通に接続したカレントミラー回路の
前記第２のトランジスタＱ2のエミッタを検出抵抗Ｒ1の
一端（電流流出端）に接続しかつコレクタを定電流源１
（電流Ｉ1）に接続し、前記第１のトランジスタＱ1のエ
ミッタは直列抵抗Ｒ2を介して検出抵抗Ｒ1の他端（電流
流入端）に接続し、検出抵抗Ｒ1を電流検出線路に直列
に挿入している。そして、前記検出抵抗Ｒ1に流れる被
検出電流Ｉinを、第１のトランジスタＱ1のコレクタ側
の検出信号電流Ｉoutから検出する構成となっている。FIG. 1 shows a first embodiment of a current detection circuit according to the present invention, and shows a basic circuit configuration. This current detection circuit includes first and second PNP transistors Q
1, the emitter of the second transistor Q2 of the current mirror circuit in which the bases of Q2 are commonly connected is connected to one end (current outflow end) of the detection resistor R1, and the collector is a constant current source 1
(Current I 1 ), the emitter of the first transistor Q1 is connected to the other end (current inflow end) of the detection resistor R1 via the series resistor R2, and the detection resistor R1 is inserted in series with the current detection line. doing. The detected current Iin flowing through the detection resistor R1 is detected from the detection signal current Iout on the collector side of the first transistor Q1.
【００１３】なお、モノリシックの対のトランジスタを
Ｑ1，Ｑ2に使用することが望ましい。また、電流検出線
路の端子Ｐは、グランド線路のグランド端子Ｇに対して
高い電位となっていることが前提であり、Ｑ1コレクタ
に接続した出力端子２とグランド端子Ｇ間の抵抗Ｒ3
は、検出信号電流Ｉoutに比例した検出信号電圧を取り
出したい場合に接続する。It is desirable to use a monolithic pair of transistors for Q1 and Q2. It is assumed that the terminal P of the current detection line has a higher potential than the ground terminal G of the ground line, and the resistance R3 between the output terminal 2 connected to the Q1 collector and the ground terminal G is assumed.
Is connected when it is desired to extract a detection signal voltage proportional to the detection signal current Iout.
【００１４】前記第１のトランジスタＱ1のエミッタを
直列抵抗Ｒ2を介して検出抵抗Ｒ1に接続した図１の回路
の場合に、検出信号電流Ｉoutが被検出電流Ｉinに対し
リニアに変化する理由を以下の各式により示す。In the case of the circuit shown in FIG. 1 in which the emitter of the first transistor Q1 is connected to the detection resistor R1 via the series resistor R2, the reason why the detection signal current Iout changes linearly with respect to the detected current Iin is as follows. Are shown by the following equations.
【００１５】前記(4)式が直列抵抗Ｒ2を挿入したことに
より次式となる。 ＶBE(Q1)＋ＩoutＲ2＝ＶBE(Q2)＋ＩinＲ1 …(8) また(1)式よりＶBE(Q1)は、 ＶBE(Q1)＝（ｋＴ／ｑ）｛ｌｎ（Ｉout／ＩS1）＋１｝ …(9) (3)式及び(9)式を(8)式に代入すると、 Ｉin＝（ｋＴ／ｑＲ1）ｌｎ（Ｉout／Ｉ1）＋（Ｒ2／Ｒ1）Ｉout …(10) (10)式を検出信号電流Ｉoutで微分すると、 （ｄＩin／ｄＩout）＝（Ｒ2／Ｒ1）＋（ｋＴ／ｑＲ1・logｅ・Ｉout） …(11) (11)式でＲ2>>（ｋＴ／ｑ・logｅ・Ｉout）≒1.987×10-4
（Ｔ／Ｉout）ならば、検出信号電流Ｉoutは被検出電流
Ｉinに対してリニアに変化することがわかり、このよう
なＲ2の値に設定することは十分可能である。The equation (4) becomes the following equation by inserting the series resistor R2. V BE (Q1) + I out R 2 = V BE (Q 2) + I in R 1 (8) From the equation (1), V BE (Q 1) is V BE (Q 1) = (kT / q) ｛ln (Iout / I S1 ) +1 } ... (9) (3) and (9) substituting expression (8) below, Iin = (kT / qR1) ln (Iout / I 1) + (R2 / R1) Iout ... (10) (10 ) Is differentiated by the detection signal current Iout. (DIin / dIout) = (R2 / R1) + (kT / qR1 · log · Iout) (11) In the equation (11), R2 >> (kT / q · log)・ Iout) ≒ 1.987 × 10 -4
If (T / Iout), it is understood that the detection signal current Iout changes linearly with respect to the detected current Iin, and it is sufficiently possible to set such a value of R2.
【００１６】この第１の実施の形態によれば、次の通り
の効果を得ることができる。According to the first embodiment, the following effects can be obtained.
【００１７】(1) 検出信号電流Ｉoutは被検出電流Ｉin
に対してリニアに変化する（実質的に比例関係とな
る）。このため、検出抵抗Ｒ1にばらつきがある場合で
も、直列抵抗Ｒ2又は抵抗Ｒ3の抵抗値を調整することで
校正可能である。(1) The detection signal current Iout is the detected current Iin
Changes linearly (substantially proportionally). Therefore, even when the detection resistance R1 varies, calibration can be performed by adjusting the resistance value of the series resistance R2 or the resistance R3.
【００１８】(2) 検出抵抗Ｒ1のばらつきに起因する検
出信号電流Ｉoutの変動は図９の従来回路に比べて少な
くでき、電流検出精度の向上を図ることができる。(2) The fluctuation of the detection signal current Iout due to the fluctuation of the detection resistor R1 can be reduced as compared with the conventional circuit of FIG. 9, and the current detection accuracy can be improved.
【００１９】図２は本発明の第２の実施の形態を示す。
この場合、第２のトランジスタＱ2のコレクタ側の定電
流源を抵抗Ｒ4，Ｒ5及び定電圧ダイオードＺＤで実現し
ている。また、第１のトランジスタＱ1のコレクタとグ
ランド端子Ｇ間に検出信号電流Ｉoutを流す抵抗Ｒ31，
Ｒ32の直列回路が接続され、抵抗Ｒ31，Ｒ32の接続点が
出力端子３となっている。その他の構成は前述した第１
の実施の形態と同様である。FIG. 2 shows a second embodiment of the present invention.
In this case, a constant current source on the collector side of the second transistor Q2 is realized by resistors R4 and R5 and a constant voltage diode ZD. Also, a resistor R31, which allows a detection signal current Iout to flow between the collector of the first transistor Q1 and the ground terminal G,
A series circuit of R32 is connected, and a connection point of the resistors R31 and R32 is an output terminal 3. Other configurations are the same as those of the first
This is the same as the embodiment.
【００２０】図２において、電流検出線路の端子Ｐとグ
ランド線路のグランド端子Ｇ間に入力電圧Ｖinを供給
し、検出抵抗Ｒ1を通して被検出電流Ｉinが流れるよう
に負荷Ｌｄを接続して、被検出電流Ｉinと出力端子３の
検出信号電圧Ｖsenseとの関係を求めたところ、図３の
グラフのようになった。但し、図３中、線（イ）は入力
電圧Ｖin＝２０Ｖ、線（ロ）は入力電圧Ｖin＝３０Ｖ、
線（ハ）は入力電圧Ｖin＝４０Ｖの場合であり、回路定
数は、Ｒ1：０．３９Ω、Ｒ2：３９Ω、Ｒ31：１ｋΩ、
Ｒ32：４７０Ω、Ｒ4：４．７ｋΩ、，Ｒ5：１０ｋΩ、
ＺＤのツェナー電圧：５Ｖである。これらより、入力電
圧Ｖinが一定の条件下で、被検出電流Ｉinと検出信号電
圧Ｖsenseとの関係がリニアであることが明らかとなっ
た。In FIG. 2, an input voltage Vin is supplied between a terminal P of a current detection line and a ground terminal G of a ground line, and a load Ld is connected so that a current Iin to be detected flows through a detection resistor R1. When the relationship between the current Iin and the detection signal voltage Vsense at the output terminal 3 was obtained, the graph shown in FIG. 3 was obtained. However, in FIG. 3, the line (a) is the input voltage Vin = 20 V, the line (b) is the input voltage Vin = 30 V,
The line (c) shows the case where the input voltage Vin = 40 V, and the circuit constants are R1: 0.39Ω, R2: 39Ω, R31: 1 kΩ,
R32: 470Ω, R4: 4.7kΩ, R5: 10kΩ,
Zener voltage of ZD: 5V. From these, it became clear that the relationship between the detected current Iin and the detection signal voltage Vsense is linear under the condition that the input voltage Vin is constant.
【００２１】なお、入力電圧Ｖinが変化するのに伴って
検出信号電圧Ｖsenseが変動するのは、トランジスタＱ1
のＶCEが変化することに起因するアーリー効果と呼ばれ
る現象であり、入力電圧Ｖinが変化する条件下で使用す
る場合には注意を要する。The reason why the detection signal voltage Vsense fluctuates as the input voltage Vin fluctuates is that the transistor Q1
Is a phenomenon called the Early effect caused by a change in V CE of the device, and care must be taken when the device is used under conditions where the input voltage Vin changes.
【００２２】図４は本発明の第３の実施の形態であっ
て、上記のアーリー効果を解消するためにウィルソンの
カレントミラー回路（ウィルソンミラー回路）を応用し
た回路構成を示す。この図において、第１のトランジス
タＱ1のコレクタ側に第１のトランジスタＱ1と同極性の
第３のトランジスタＱ3を直列に挿入し、トランジスタ
Ｑ1，Ｑ2のベースを第３のトランジスタＱ3のエミッタ
に接続し、第３のトランジスタＱ3のベースを第２のト
ランジスタＱ2のコレクタに接続し、Ｑ3のコレクタを出
力端子２に接続している。なお、その他の構成は前述し
た第１の実施の形態と同様である。FIG. 4 shows a third embodiment of the present invention, and shows a circuit configuration in which a Wilson current mirror circuit (Wilson mirror circuit) is applied to eliminate the Early effect. In this figure, a third transistor Q3 having the same polarity as the first transistor Q1 is inserted in series on the collector side of the first transistor Q1, and the bases of the transistors Q1 and Q2 are connected to the emitter of the third transistor Q3. , The base of the third transistor Q3 is connected to the collector of the second transistor Q2, and the collector of Q3 is connected to the output terminal 2. The other configuration is the same as that of the first embodiment.
【００２３】この第３の実施の形態によれば、アーリー
効果を解消して、入力電圧の変化伴う検出信号電流Ｉou
tの変動を除去でき、電流検出精度のいっそうの改善を
図ることができる。According to the third embodiment, the Early effect is eliminated and the detection signal current Iou accompanying the change in the input voltage is reduced.
The fluctuation of t can be removed, and the current detection accuracy can be further improved.
【００２４】図５は本発明の第４の実施の形態であっ
て、上記のアーリー効果を解消するためにウィルソンの
カレントミラー回路（ウィルソンミラー回路）を応用し
た場合の具体的な回路構成を示す。この場合、第２のト
ランジスタＱ2のコレクタ側の定電流源を抵抗Ｒ4，Ｒ5
及び定電圧ダイオードＺＤで実現している。また、第３
のトランジスタＱ3のコレクタとグランド端子Ｇ間に検
出信号電流Ｉoutを流す抵抗Ｒ31，Ｒ32の直列回路が接
続され、抵抗Ｒ31，Ｒ32の接続点が出力端子３となって
いる。その他の構成は前述した第３の実施の形態と同様
である。FIG. 5 shows a fourth embodiment of the present invention, and shows a specific circuit configuration in the case where a Wilson current mirror circuit (Wilson Miller circuit) is applied to eliminate the Early effect. . In this case, the constant current source on the collector side of the second transistor Q2 is connected to the resistors R4 and R5.
And a constant voltage diode ZD. Also, the third
A series circuit of resistors R31 and R32 for flowing the detection signal current Iout is connected between the collector of the transistor Q3 and the ground terminal G, and the connection point of the resistors R31 and R32 is the output terminal 3. Other configurations are the same as those of the third embodiment.
【００２５】図５において、電流検出線路の端子Ｐとグ
ランド線路のグランド端子Ｇ間に入力電圧Ｖinを供給
し、検出抵抗Ｒ1を通して被検出電流Ｉinが流れるよう
に負荷Ｌｄを接続して、被検出電流Ｉinと出力端子３の
検出信号電圧Ｖsenseとの関係を求めたところ、図６の
グラフのようになった。但し、図６中、線（ニ）は入力
電圧Ｖin＝２０Ｖ、線（ホ）は入力電圧Ｖin＝３０Ｖ，
４０Ｖの場合であり、線（ニ）と線（ホ）とは大部分が
重なっていて入力電圧Ｖinが変化しても検出信号電圧Ｖ
senseは変動していないことがわかる。なお、回路定数
は、Ｒ1：０．３９Ω、Ｒ2：３９Ω、Ｒ31：１ｋΩ、Ｒ
32：４７０Ω、Ｒ4：４．７ｋΩ、，Ｒ5：１０ｋΩ、Ｚ
Ｄのツェナー電圧：５Ｖとした（図２と同じ）。これら
より、入力電圧にかかわりなく、被検出電流Ｉinと検出
信号電圧Ｖsenseとの関係がリニアであることが明らか
となった。In FIG. 5, an input voltage Vin is supplied between a terminal P of a current detection line and a ground terminal G of a ground line, and a load Ld is connected so that a current Iin to be detected flows through a detection resistor R1. When the relationship between the current Iin and the detection signal voltage Vsense at the output terminal 3 was obtained, the graph shown in FIG. 6 was obtained. However, in FIG. 6, line (d) is input voltage Vin = 20V, line (e) is input voltage Vin = 30V,
In the case of 40 V, the line (d) and the line (e) are mostly overlapped, and even if the input voltage Vin changes, the detection signal voltage V
It can be seen that sense does not change. The circuit constants are: R1: 0.39Ω, R2: 39Ω, R31: 1 kΩ, R
32: 470Ω, R4: 4.7kΩ, R5: 10kΩ, Z
The Zener voltage of D was 5 V (same as FIG. 2). From these, it has become clear that the relationship between the detected current Iin and the detection signal voltage Vsense is linear regardless of the input voltage.
【００２６】図７は本発明の第５の実施の形態であっ
て、検出信号電流Ｉoutの流れる可変抵抗ＶＲ1の両端に
生じる検出信号電圧と、基準電圧Ｖrefとを比較する比
較器４を設けている。その他の構成は前述した第１の実
施の形態と同様である。FIG. 7 shows a fifth embodiment of the present invention, in which a comparator 4 for comparing a detection signal voltage generated at both ends of a variable resistor VR1 through which a detection signal current Iout flows with a reference voltage Vref is provided. I have. Other configurations are the same as those of the first embodiment.
【００２７】この第５の実施の形態では、検出抵抗Ｒ1
を流れる被検出電流Ｉinが所定値を越えたとき、比較器
４の出力端子５にハイレベル出力が得られるので、過電
流検出等に応用できる。In the fifth embodiment, the detection resistor R1
When the detected current Iin flowing through the comparator exceeds a predetermined value, a high-level output is obtained at the output terminal 5 of the comparator 4, so that it can be applied to overcurrent detection and the like.
【００２８】図８は本発明の第６の実施の形態であっ
て、第１及び第２のトランジスタＱ1，Ｑ2としてＮＰＮ
トランジスタを用いている。従って、第１〜第５の実施
の形態とは電圧の正負が逆となり、グランド端子Ｇに接
続されたグランド線路を電流検出線路として、ここに検
出抵抗Ｒ1を挿入することができる。そして、検出抵抗
Ｒ1に流れる被検出電流Ｉinを、第１のトランジスタＱ1
のコレクタ側の検出信号電流Ｉoutから検出する。つま
り、正側の端子Ｐと第１のトランジスタＱ1のコレクタ
間に接続された可変抵抗ＶＲ2の両端の電圧から検出信
号電圧を取り出す構成となっている。なお、その他の構
成は前述した第１の実施の形態と同様である。FIG. 8 shows a sixth embodiment of the present invention, in which NPN is used as the first and second transistors Q1, Q2.
A transistor is used. Therefore, the polarity of the voltage is opposite to that of the first to fifth embodiments, and the ground line connected to the ground terminal G can be used as the current detection line, and the detection resistor R1 can be inserted here. The detected current Iin flowing through the detection resistor R1 is supplied to the first transistor Q1.
From the detection signal current Iout on the collector side. That is, the detection signal voltage is extracted from the voltage across the variable resistor VR2 connected between the positive terminal P and the collector of the first transistor Q1. The other configuration is the same as that of the first embodiment.
【００２９】この第６の実施の形態では、電流検出をグ
ランド側にて行うことが可能な利点がある。The sixth embodiment has an advantage that the current can be detected on the ground side.
【００３０】なお、図７及び図８の第５及び第６の実施
の形態に対しても、アーリー効果を解消するためにウィ
ルソンのカレントミラー回路（ウィルソンミラー回路）
を応用した回路構成に変更することが可能である。The fifth and sixth embodiments shown in FIGS. 7 and 8 also have a Wilson current mirror circuit (Wilson mirror circuit) in order to eliminate the Early effect.
It is possible to change to a circuit configuration that applies.
【００３１】また、入力変動が少ない条件下では、各実
施の形態における定電流源の代わりに電流安定化用抵抗
を用いることができ、図２や図５の定電圧ダイオードＺ
Ｄを省略した回路構成とすることも可能である。Further, under the condition that the input fluctuation is small, a current stabilizing resistor can be used instead of the constant current source in each embodiment, and the constant voltage diode Z shown in FIGS. 2 and 5 can be used.
It is also possible to adopt a circuit configuration in which D is omitted.
【００３２】以上本発明の実施の形態について説明して
きたが、本発明はこれに限定されることなく請求項の記
載の範囲内において各種の変形、変更が可能なことは当
業者には自明であろう。Although the embodiments of the present invention have been described above, it is obvious to those skilled in the art that the present invention is not limited to the embodiments and various modifications and changes can be made within the scope of the claims. There will be.
【００３３】[0033]
【発明の効果】以上説明したように、本発明に係る電流
検出回路によれば、第１及び第２のトランジスタのベー
スを共通に接続したカレントミラー回路の前記第２のト
ランジスタのエミッタを検出抵抗の一端に接続し、前記
第１のトランジスタのエミッタは直列抵抗を介して前記
検出抵抗の他端に接続し、前記検出抵抗を電流検出線路
に直列に挿入した構成であるから、前記検出抵抗に流れ
る被検出電流に略比例した検出信号（電圧又は電流）を
前記第１のトランジスタのコレクタ側より取り出すこと
が可能である。従って、前記検出抵抗のばらつきに起因
する前記検出信号のずれを容易に校正可能である。ま
た、前記検出抵抗のばらつきに起因する検出信号の変動
は従来回路に比べて少なく、電流検出精度の向上を図る
ことができる。As described above, according to the current detection circuit of the present invention, the emitter of the second transistor of the current mirror circuit in which the bases of the first and second transistors are connected in common is connected to the detection resistor. , The emitter of the first transistor is connected to the other end of the detection resistor via a series resistor, and the detection resistor is inserted in series with the current detection line. It is possible to take out a detection signal (voltage or current) substantially proportional to the flowing current to be detected from the collector side of the first transistor. Therefore, it is possible to easily calibrate the deviation of the detection signal due to the variation of the detection resistance. Further, the variation of the detection signal due to the variation of the detection resistor is smaller than that of the conventional circuit, and the current detection accuracy can be improved.
【図１】本発明に係る電流検出回路の第１の実施の形態
を示す回路図である。FIG. 1 is a circuit diagram showing a first embodiment of a current detection circuit according to the present invention.
【図２】本発明の第２の実施の形態を示す回路図であ
る。FIG. 2 is a circuit diagram showing a second embodiment of the present invention.
【図３】第２の実施の形態における被検出電流Ｉinと検
出信号電圧Ｖsenseとの関係を示すグラフである。FIG. 3 is a graph showing a relationship between a detected current Iin and a detection signal voltage Vsense in the second embodiment.
【図４】本発明の第３の実施の形態を示す回路図であ
る。FIG. 4 is a circuit diagram showing a third embodiment of the present invention.
【図５】本発明の第４の実施の形態を示す回路図であ
る。FIG. 5 is a circuit diagram showing a fourth embodiment of the present invention.
【図６】第４の実施の形態における被検出電流Ｉinと検
出信号電圧Ｖsenseとの関係を示すグラフである。FIG. 6 is a graph showing a relationship between a detected current Iin and a detection signal voltage Vsense in the fourth embodiment.
【図７】本発明の第５の実施の形態を示す回路図であ
る。FIG. 7 is a circuit diagram showing a fifth embodiment of the present invention.
【図８】本発明の第６の実施の形態を示す回路図であ
る。FIG. 8 is a circuit diagram showing a sixth embodiment of the present invention.
【図９】電流検出回路の従来回路を示す回路図である。FIG. 9 is a circuit diagram showing a conventional circuit of a current detection circuit.
【図１０】従来回路における被検出電流Ｉinと検出信号
電流Ｉoutとの関係を示すグラフである。FIG. 10 is a graph showing a relationship between a detected current Iin and a detection signal current Iout in a conventional circuit.
１ 定電流源 ２，３，５ 出力端子 ４ 比較器 Ｑ1，Ｑ2，Ｑ3 トランジスタ Ｒ1，Ｒ2，Ｒ3，Ｒ4，Ｒ5，Ｒ31，Ｒ32 抵抗 ＺＤ 定電圧ダイオード DESCRIPTION OF SYMBOLS 1 Constant current source 2, 3, 5 Output terminal 4 Comparator Q1, Q2, Q3 Transistor R1, R2, R3, R4, R5, R31, R32 Resistance ZD Constant voltage diode
Claims (2)
共通に接続したカレントミラー回路の前記第２のトラン
ジスタのエミッタを検出抵抗の一端に接続しかつコレク
タを定電流源又は抵抗に接続し、前記第１のトランジス
タのエミッタは直列抵抗を介して前記検出抵抗の他端に
接続し、前記検出抵抗を電流検出線路に直列に挿入する
とともに、前記検出抵抗に流れる被検出電流を前記第１
のトランジスタのコレクタ側にて検出することを特徴と
する電流検出回路。1. A current mirror circuit in which the bases of a first transistor and a second transistor are commonly connected, an emitter of the second transistor is connected to one end of a detection resistor, and a collector is connected to a constant current source or a resistor. An emitter of the first transistor is connected to the other end of the detection resistor via a series resistor, the detection resistor is inserted in series into a current detection line, and a current to be detected flowing through the detection resistor is connected to the first transistor.
A current detection circuit characterized in that the current is detected on the collector side of the transistor.
前記第１のトランジスタと同極性の第３のトランジスタ
を直列に挿入し、該第３のトランジスタのベースを前記
第２のトランジスタのコレクタに接続してなる請求項１
記載の電流検出回路。2. A third transistor having the same polarity as the first transistor is inserted in series on the collector side of the first transistor, and a base of the third transistor is connected to a collector of the second transistor. Claim 1
The current detection circuit as described.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP34854597A JPH11160368A (en) | 1997-12-02 | 1997-12-02 | Current detection circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP34854597A JPH11160368A (en) | 1997-12-02 | 1997-12-02 | Current detection circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH11160368A true JPH11160368A (en) | 1999-06-18 |
Family
ID=18397740
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP34854597A Pending JPH11160368A (en) | 1997-12-02 | 1997-12-02 | Current detection circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH11160368A (en) |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1096262A2 (en) * | 1999-10-27 | 2001-05-02 | Harness System Technologies Research, Ltd. | Current detector |
| WO2002041491A1 (en) * | 2000-11-16 | 2002-05-23 | Robert Bosch Gmbh | A current-sensing switching circuit |
| JP2007114966A (en) * | 2005-10-19 | 2007-05-10 | Toshiba Microelectronics Corp | Current limiting circuit |
| JP2008129977A (en) * | 2006-11-24 | 2008-06-05 | Yokogawa Electric Corp | Voltage shift circuit |
| WO2008084593A1 (en) * | 2007-01-11 | 2008-07-17 | Panasonic Corporation | Voltage detector for storage element |
| EP2157437A1 (en) | 2008-08-19 | 2010-02-24 | SMA Solar Technology AG | Method for measuring a current, particularly through an earthing device |
| EP2239591A1 (en) * | 2009-04-08 | 2010-10-13 | Alcatel Lucent | Current monitor for sensing the current in a current path and corresponding control device |
| US8717047B2 (en) | 2008-08-19 | 2014-05-06 | Sma Solar Technology Ag | Method for measuring a current, in particular by means of a grounding apparatus |
-
1997
- 1997-12-02 JP JP34854597A patent/JPH11160368A/en active Pending
Cited By (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1096262A2 (en) * | 1999-10-27 | 2001-05-02 | Harness System Technologies Research, Ltd. | Current detector |
| EP1096262A3 (en) * | 1999-10-27 | 2004-01-02 | Autonetworks Technologies, Ltd. | Current detector |
| WO2002041491A1 (en) * | 2000-11-16 | 2002-05-23 | Robert Bosch Gmbh | A current-sensing switching circuit |
| US7362010B2 (en) | 2000-11-16 | 2008-04-22 | Robert Bosch Gmbh | Currents-sensing switching circuit |
| JP2007114966A (en) * | 2005-10-19 | 2007-05-10 | Toshiba Microelectronics Corp | Current limiting circuit |
| JP2008129977A (en) * | 2006-11-24 | 2008-06-05 | Yokogawa Electric Corp | Voltage shift circuit |
| WO2008084593A1 (en) * | 2007-01-11 | 2008-07-17 | Panasonic Corporation | Voltage detector for storage element |
| EP2157437A1 (en) | 2008-08-19 | 2010-02-24 | SMA Solar Technology AG | Method for measuring a current, particularly through an earthing device |
| KR101117611B1 (en) | 2008-08-19 | 2012-03-07 | 에스엠에이 솔라 테크놀로지 아게 | Apparatus for measuring grounding current in photovoltaic power system with photovoltaic generator |
| US8169226B2 (en) | 2008-08-19 | 2012-05-01 | Sma Solar Technology Ag | Method for measuring a current, in particular by means of a grounding apparatus |
| US8717047B2 (en) | 2008-08-19 | 2014-05-06 | Sma Solar Technology Ag | Method for measuring a current, in particular by means of a grounding apparatus |
| EP2239591A1 (en) * | 2009-04-08 | 2010-10-13 | Alcatel Lucent | Current monitor for sensing the current in a current path and corresponding control device |
| WO2010115681A1 (en) * | 2009-04-08 | 2010-10-14 | Alcatel Lucent | Current monitor for sensing the current in a current path and corresponding control device |
| US8729915B2 (en) | 2009-04-08 | 2014-05-20 | Alcatel Lucent | Current monitor for sensing the current in a current path and corresponding control device |
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