JPH11157142A - Semiconductor device, image-processing apparatus, and printer - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an image-processing apparatus which can efficiently transfer in DMA data such as compressed data or the like that cannot be judged by a CPU. SOLUTION: A memory controller 20 including a DMA control part 35 is adapted to receive information setting DMA transfer from a video interface circuit 12 which is an ASIC of a DMA transfer destination. Even when compressed image data are DMA transferred to the video interface circuit 12 from an image buffer 31, a condition setting the DMA transfer can be directly controlled in accordance with a quantity of image data decoded at the video interface circuit 12 and other conditions. A large quantity of image data can be transferred efficiently.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to an image processing apparatus suitable for handling a large amount of data for image creation, such as a printer controller.

[0002]

2. Description of the Related Art FIG. 5 shows a schematic configuration of a conventional printer 1 such as a laser type for performing page printing. The printer 1 receives input data for printing from a host such as a personal computer and converts the input data into output data (image data) printable by a printing mechanism (printer engine), and prints based on the output data. A printing mechanism 2 for printing on paper.

The image processing section 5 includes an input interface circuit section 11 for receiving input data from a host, and a ROM 15 for storing a program for storing a program for interpreting the input data and converting the data into output data for creating an image.
And a ROM 16 storing font data for converting input data into print data, and a DRAM 14 serving as a work area for conversion processing and storing output data or intermediate data for converting input data to output data. And are connected by a bus 17.

Further, these interfaces 11, R
The OMs 15 and 16, the DRAM 14, etc.
The data input from the input interface 11 is connected to the U 13 and is converted according to a program stored in the ROM 15.

In the image processing unit 5, when the input data is converted into bit image data (image data) for creating an image, it is temporarily stored in an image buffer of the DRAM 14. Then, output data is supplied to the printer engine 2 via the video interface circuit unit 12 connected to the bus 17, and printing for each page is performed. Image data is DMA-transferred from the DRAM 14 to the video interface circuit unit 12 using the DMA transfer function of the memory controller 20, temporarily stored in the FIFO memory, and then transferred to the printing mechanism 2.

[0006]

When performing DMA transfer, the type of DMA (read / write, address, number of DMAs, data length, etc.) is given from the CPU 13 to the memory controller 20, and thereafter, the memory controller 20 Controlling. This is the AS other than the memory controller
The same applies to the case where the IC performs DMA control to directly transfer data between another ASIC and the memory, and the ASIC that controls the CPU interface (hereinafter, the first ASIC)
(Semiconductor device)) controls all types of DMA.
Therefore, when the first ASIC controls all the DMA transfer and starts the other ASIC (hereinafter, the second ASIC).
(Semiconductor device)), processing proceeds only with a DMA request signal and a signal corresponding thereto. Therefore, the second AS
Even if there is information on the DMA request from the IC, the first A
It could not be reflected in SIC DMA control.

In recent years, printers also handle high-resolution images or full-color images, and the amount of image data handled in printing such images is enormous. Therefore, the storage capacity of the image buffer for storing image data becomes enormous, and the amount of data transferred from the image buffer to the video interface circuit section 12 also becomes enormous. Therefore, it has been considered that the image data is transferred in a compressed state and decompressed by the video interface circuit unit 12 so that the capacity of the image buffer can be reduced and the transfer processing time can be shortened.

However, since the amount of the transferred image data or other conditions can be determined at the stage of decompression, the second
The setting conditions of the DMA control are found on the side of the video interface circuit unit 12 corresponding to the ASIC. However, in order to set the DMA control from the second ASIC side, it is necessary to employ a complicated system such as performing the control via a CPU using software. For this reason, D
Since the conditions for MA control cannot be set, the process of compressing and transferring image data is not performed smoothly, and the performance is reduced.

Therefore, in the present invention, as described above, even in the transfer processing in which the setting conditions of the DMA control are determined on the side of the second ASIC, the DM configuration can be performed with a simple configuration.
It is an object of the present invention to provide an ASIC and an image processing apparatus having a DMA control function capable of setting A control and improving performance. Another object of the present invention is to provide a printer capable of processing a large amount of image data at high speed without significantly increasing the memory capacity.

[0010]

Therefore, according to the present invention, there is provided a semiconductor device having a DMA control function capable of controlling direct data transfer between a memory and another semiconductor device. By using a semiconductor device having a DMA control function, which is capable of receiving setting information of the DMA control function, a
Instead of a system capable of controlling the type of transfer, the type of DMA transfer can also be controlled from the destination or source second semiconductor device (ASIC).
That is, an image processing apparatus according to the present invention includes a first semiconductor device having a CPU, a memory capable of storing image data, and a DMA control function capable of controlling direct data transfer between the memory and the second semiconductor device. And the first semiconductor device is capable of receiving setting information of the DMA control function from the second semiconductor device.

The setting information receivable from the second semiconductor device includes read / write, DMA channel, necessity of address loading, transfer count or transfer data length, and these setting information is stored in the second semiconductor device. The setting of the type of the DMA transfer can be controlled by the second semiconductor device as the transfer destination or the transfer source of the DMA by giving it from the device, and the DMA control corresponding to this can be performed by the first semiconductor device. Can be done with

Therefore, in a transfer process in which the status of the actual quality or quantity of the transfer data is found in the transfer source or the transfer destination second semiconductor device, the D value corresponding to the situation is determined.
The setting of the MA control function can be directly controlled from the second semiconductor device. Therefore, there is no need to use software to set conditions via the CPU, and the system can be simplified, and at the same time, the type of DMA transfer can be controlled with good timing, so that the performance can be improved. Of course, a plurality of first and second semiconductor devices can be provided. In addition, the first semiconductor device can be controlled by a plurality of second semiconductor devices, and the first semiconductor device can be controlled by a third semiconductor device via the second semiconductor device. It is also possible to do so.

A first semiconductor device having a DMA control function is a memory controller. In a printer which DMA-transfers image data from a memory to an output interface capable of outputting image data to a printing mechanism, the compressed image data When performing the DMA transfer, the memory controller can receive the setting information of the DMA control function from the output interface unit. Therefore, the type of DMA transfer can be controlled based on the image data decompressed or decompressed by the output interface unit. Therefore, a large amount of image data can be smoothly transferred in a compressed state.
The speed at which a large amount of image data is processed by the printer can be improved, and the memory capacity for processing a large amount of image data can be reduced.

Further, by allowing setting information of the DMA control function to be provided from the second semiconductor device, optimization is not limited to DMA transfer for transferring image data to the output interface unit, but various DMA transfers are also optimized. Can be planned. For example, even when the input data input from the host is DMA-transferred from the input interface unit to the memory, the setting conditions are given from the input interface unit to control the DMA transfer based on the amount of the input data and optimize the transfer speed. Can be further improved.

[0015]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a printer 1 according to the present invention.
Is shown. The printer 1 of the present embodiment converts input data supplied from the host into output data for image creation and converts the input data supplied from the host into a printing mechanism 2 in the same manner as the printer described above.
, And a printing mechanism 2 that performs printing based on the image data supplied from the image processing unit 10. Common parts are denoted by the same reference numerals, and description thereof is omitted below. I do.

The image processing unit 10 of this embodiment includes a CPU 13
A memory controller 20 connected to the CPU 13 and the CPU bus 19;
And a program R connected via a memory bus 17
An OM 15 and a ROM 16 for fonts are provided. The memory interface 17 further includes an input interface circuit 1
A semiconductor device (ASIC) such as No. 1 is also connected.

In the image processing apparatus 10 of the present embodiment, the video interface circuit section 12 is connected to the CPU bus 19, and can directly receive data from the memory 30 connected to the CPU bus 19 via the bus driver 21. It has become. In this example, a RAM bus 22 is connected to a CPU bus 19 via a bus driver 21, and R
An SDRAM 30 as a memory is connected to the AM bus 22. The SDRAM 30 includes a memory controller 20
, Address data is supplied via an address bus 23, and a control signal is supplied via a control signal wiring 24. Also, SDR
The clock signal 25 input to the CPU 13 for the synchronous operation is input to the AM 30 at the same time.
3 operates at the same operating frequency.

The memory controller 20 of the present embodiment has a DMA
A control unit 35 is provided so that data can be directly transferred between the SDRAM 30 and the video interface circuit 12. Then, using this transfer system, the image data stored in the image buffer 31 of the SDRAM 30 is DMA-transferred to the video interface circuit 12 and can be output to the printing mechanism 2. Therefore, the control signal wiring 26 for controlling the control of the bus with the CPU 13 and the information for setting the DMA transfer, for example, the read / write, address, the number of DMAs, the data length, etc. are supplied from the CPU 13. And a signal line 27 for a system command.

A signal line 28 for a DMA request command for controlling DMA transfer and a signal line 29 for a command responding to the DMA request command are provided between the memory controller 20 and the video interface circuit 12. . Further, between the memory controller 20 and the video interface circuit 12 of the present example, in addition to the above-described control command, information for setting a DMA transfer can be transmitted from the video interface circuit 12 to the memory controller 20. A signal line 36 is provided. Therefore,
Conventionally, setting information such as the type of DMA transfer that could only be transmitted from the CPU 13 is transferred from the video interface circuit 12 that is the DMA transfer destination to the D of the memory controller 20.
It can be set directly in the MA control unit 35.

The setting command CMD receivable by the DMA controller 35 of the present embodiment from the video interface circuit 12 is:
This is 5-bit information, the contents of which are shown in FIG.
Reading or writing can be instructed by the most significant bit CMD (4), and a DMA channel can be selected by the next bit CMD (3). Further, it is possible to set whether or not to load a new address set from the CPU 13 in the next bit CMD (2). Furthermore, the number of DMA transfers such as single or burst transfer and the length of data to be transferred such as 1 byte or 8 bytes can be set by the least significant 2 bits CMD (1) and CMD (0). I have.

In the image processing section 10 of the present embodiment, information can be set in the DMA control section 35 from the video interface circuit 12, so that the DMA transfer by the DMA control section 35 of the present embodiment is as shown in FIG. Progress in a simple process.

First, when a DMA start command is issued in step 51, the CPU 13 sets an address in the DMA controller 35 of the memory controller 20 in step 52. Then, in step 53, the CPU 13 issues a DMA start command to the video interface 12. Thus, in step 54, the video interface circuit 12
The condition of the next DMA transfer is determined by judging conditions such as the data amount of the image data which has been DMA-transferred until then, and after setting each bit CMD (4) to (0) of the setting command, the DMA controller Send to 35. Thereafter, in step 55, the video interface circuit 12 outputs a DMA request signal to the DMA controller 35. In response to the DMA request signal, the DMA control unit 35 decodes the setting commands CMD (4) to (0) in step 56 to set DMA transfer conditions, and sends the image data stored in the SDRAM 30 to the video interface circuit 12. DMA transfer is performed. Thus, in step 57, the video interface circuit 12 can receive and capture the image data.

As described above, in the image processing apparatus 10 of the present embodiment, the type of DMA transfer can be controlled from the video interface circuit 12 side by using the setting command. Therefore, the video interface circuit 12
The setting of the next DMA transfer can be controlled according to the state of the image data transferred by the A transfer. For this reason, the image data is stored in a compressed state in the memory buffer 31, and the image data is decompressed or expanded by the video interface circuit 12 of the transfer destination. Image data can be transferred.

That is, in recent years, high-resolution and / or high-gradation full-color images can be processed by a personal computer or the like, and it is urgently necessary to output the image data as a high-quality print even in a printer. I have. The amount of image data for outputting a high-resolution or high-gradation full-color print is enormous, and if it is desired to store the image data in the image buffer as it is, it is necessary to greatly increase the memory capacity. Further, even if a large amount of image data can be stored by increasing the memory capacity, the processing time for transferring the image data to the printing mechanism 2 is greatly increased, and the printing speed is reduced. Therefore, by reducing the required memory capacity by reducing the image data stored in the image buffer in a compressed state, the amount of data transferred to the video interface circuit 12 is also reduced, and the processing speed is increased. Is considered.

However, it is determined that the substantial amount of the compressed image data and other conditions must be decompressed or decompressed by the video interface circuit 12 and decoded into actual image data to be passed to the printing mechanism 2. Can not. Therefore, even if the memory capacity can be reduced by compressing the data and the transfer speed with respect to the data amount can be improved, the transfer status cannot be determined by the CPU, so that the conditions for the DMA transfer cannot be set efficiently. For this reason, the total performance of the image processing may not be improved but may be reduced. Although it is possible to control the DMA by feeding back the transfer state determined by the video interface circuit 12 to the CPU 13 via software or the like, the system becomes very complicated.

On the other hand, the video interface circuit 12 and D
It is possible to manufacture the memory controller 20 having the MA transfer function as one ASIC so that the setting of the DMA transfer can be controlled within the same ASIC. Can be simply controlled. However, even if the specifications of the video interface circuit 12 are changed, it is necessary to design and remanufacture the entire ASIC including the memory controller, thereby increasing the cost. Also,
The flexibility of the system as the image processing device is reduced.

On the other hand, in the image processing apparatus 10 of the present embodiment, the external controller which is the object of the DMA transfer is transmitted to the memory controller.
Since the setting command can be received from the video interface circuit 12 of the SIC, all of the above problems can be solved. That is, since the setting of the DMA transfer can be directly controlled in accordance with the conditions found on the video interface circuit 12 side, even when the transfer data is compressed, it is possible to deal with the case where the transfer data is compressed by a system having a simple configuration, and to optimize the transfer conditions And maintain high performance.
Furthermore, even if the memory controller 20 and the video interface circuit 12 are realized as separate ASICs, since DMA transfer is set by a setting command from the video interface circuit 12, each ASIC can be independently designed and manufactured. . Therefore, it is possible to build a system that can flexibly respond to specification changes, etc.
It is also possible to suppress cost increase.

As described above, by employing the ASIC having the DMA transfer function of the present invention as a memory controller, image data for high-resolution or full-color printing, which has a large amount of data, can be compressed to improve processing efficiency. The processing speed can be improved. Further, the image processing apparatus 1 has a high degree of freedom with respect to system changes at low cost.
0 and the printer 1 can be provided. further,
The setting command that can be received by the memory controller 20 of this example has versatility. For this reason, the same function as described above can be used not only for the DMA transfer with the video interface circuit 12 but also for the DMA transfer from the input interface circuit 11 to the reception buffer, for example, depending on the reception state from the host. By setting appropriate conditions, the performance of DMA transfer can be improved.

As described above, in the conventional DMA transfer processing using the ASIC having the DMA control function, the setting of the DMA transfer can be controlled only from the CPU, so that the amount or other conditions are directly judged from the CPU. When transferring information in a form that cannot be performed, for example, compressed information, efficient DMA transfer processing has been difficult. On the other hand, the memory controller 20 according to the present embodiment uses an ASIC that is a data transfer destination or a transfer source directly with a memory.
Is implemented as an ASIC provided with an interface for receiving setting information for DMA transfer from the ASIC. Therefore, C
The ASIC of the transfer destination or transfer source cannot determine the PU.
The setting control of the DMA transfer can be performed with good timing even when performing data transfer processing that can be determined only by the above. Therefore, an ASIC having a DMA control function according to the present invention
By adopting, the DMA transfer of various data can be performed efficiently, so that an information processing apparatus with a higher processing speed can be realized. Further, it is possible to provide a high-speed image processing apparatus suitable for image data-related information whose data amount will further increase in the future.

The configuration of the setting command described above is merely an example, and a command system of 4 bits or less or 6 bits or more can be adopted. Further, an external ASIC (second ASIC) Of course, the information that can be set from another ASIC is not limited to the above. In addition, a plurality of first ASICs having a DMA function such as the memory controller 20 can be provided, and a plurality of external ASICs as a second ASIC can be provided. First
By providing an interface capable of connecting a plurality of second ASICs to the ASIC, it is also possible to perform DMA control based on setting commands from the plurality of second ASICs.

As shown in FIG. 4, the third ASIC
From the first A through the second ASIC
It is also possible to transmit to the SIC and control the setting conditions of the DMA transfer by the third ASIC. As the third AIC, for example, there is an ASIC 41 for compression processing including a compression circuit for compressing and storing the above-described image data, and transmits a setting command to the memory controller 20 via the video interface circuit 12. The DMA transfer can be controlled according to the compression state of the image data.

[0032]

As described above, in the present invention, unlike the conventional system in which the condition of the DMA transfer is set only from the CPU, another ASIC in which the data is directly transferred to and from the memory. That is, the ASIC having the DMA control function from the second ASIC, that is, the first ASIC
The SIC can directly receive the setting information of the DMA control function. Therefore, the substantial amount and other conditions of the data being transferred on the side of the second ASIC are known and the CP
Even in a transfer mode in which the transfer status cannot be grasped from U, it is possible to construct a system such as an image processing apparatus capable of efficiently performing a DMA transfer by coping with optimum conditions.

Further, since the first ASIC having the DMA control function according to the present invention has versatility, it is not limited to a specific ASIC such as a video interface circuit or the like, and various types of DMA transfer source or destination can be used. DMA transfer conditions can be set and controlled directly from the ASIC. Therefore, the present invention is not limited to the printer described above, and can be applied to various information processing systems, and is particularly suitable for an image processing apparatus that handles a large amount of data.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a schematic configuration of a printer according to an embodiment of the present invention.

FIG. 2 is a diagram illustrating a configuration example of a setting command that can be set from a video interface circuit of an image processing unit of the printer illustrated in FIG.

FIG. 3 is a flowchart showing an outline of a process of DMA transfer to a video interface circuit in the printer shown in FIG. 1;

FIG. 4 is a block diagram showing a different example according to the embodiment of the present invention.

FIG. 5 is a block diagram illustrating a schematic configuration of a conventional printer.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Printer 2 Printing mechanism 10 Image processing part 11 Input interface part 12 Video interface part 13 CPU 15 Program ROM 16 Font ROM 17 Memory bus 19 CPU bus 20 Memory controller 21 Bus driver 22 RAM bus 23 Address bus 30 SDRAM unit 35 DMA Control unit 36 Signal line for setting command 41 Compression processing unit

Claims (8)

[Claims] 1. A semiconductor device having a DMA control function capable of controlling direct data transfer between a memory and another semiconductor device, wherein setting information of the DMA control function can be received from the other semiconductor device. DMA characterized by the following
A semiconductor device having a control function. 2. The semiconductor device according to claim 1, wherein the setting information includes information on read / write, DMA channel, necessity of address loading, transfer count or transfer data length. 3. A semiconductor device comprising: a CPU; a memory capable of storing image data; and a first semiconductor device having a DMA control function capable of controlling direct data transfer between the memory and the second semiconductor device. An image processing apparatus, wherein the first semiconductor device is capable of receiving setting information of the DMA control function from the second semiconductor device. 4. The semiconductor device according to claim 3, wherein
An image processing device, which is an SIC. 5. The image processing apparatus according to claim 3, wherein the setting information includes information on read / write, DMA channel, necessity of address loading, transfer count or transfer data length. 6. The image processing apparatus according to claim 3, wherein the first semiconductor device is a memory controller. 7. A CPU, a memory capable of storing image data, and a memory controller having a DMA control function of DMA-transferring image data from the memory to an output interface unit capable of outputting image data to a printing mechanism. And
The printer, wherein the memory controller can receive setting information of the DMA control function from the output interface unit. 8. The printer according to claim 7, wherein the setting information includes information on read / write, DMA channel, necessity of address loading, transfer count or transfer data length.