JPH11155285A - Controller of power converter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a controller of a power converter which is capable of reducing 'chattering' and reduce switching loss, while the gain of a resonance suppression control system is not reduced. SOLUTION: When an output vector, which is outputted by a power converter immediately before, is stored in a selected vector storing means 53 and a region dividing vector diagram is generated by a region dividing vector diagram generating means 54, the area of a region including the immediately before output vector stored in a selected vector storing means 53 is enlarged than an ordinary area to generate region dividing vector diagram. An output-enable vector, corresponding to a region in which a command value vector is included, is selected as the output vector for next fine by using the region dividing vector diagram.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a control device for a power converter in which converters are multiplexed.

[0002]

2. Description of the Related Art FIG. 26 is a block diagram of a multiple current type converter. In FIG. 26, AC load 1 has capacitors 2 to
Converters 5-8 for converting DC power to AC power via 4
Are connected to the AC load 1 with the respective AC terminals common, and the parallel operation is performed. Capacitors 2 to 4 are used to absorb switching surges of converters 5 to 8, and converters 5 to 8 are self-extinguishing switching elements 9 to 3.
2 Hereinafter, a case where a gate turn-off thyristor (GTO) is used as the self-extinguishing type switching element will be described. The DC power supplies 4 are connected to the converters 5 to 8 via DC reactors 33 to 40 for smoothing the DC current.
1 to 44 are connected. Here, DC power supplies 41 to 44
Are controlled equally.

As means for controlling the firing state of the elements of this multiple current type converter according to a current command, as shown in FIG. 27, as conventionally described in Japanese Patent Application No. 7-135776. Control circuits have been proposed.

First, before explaining FIG. 27, a current vector that can be generated on the AC side by the four-multiplex converter of FIG. 26 will be described with reference to FIG. In FIG. 28, coordinate axes are U, V,
Indicated by W. For example, GTO9 and GTO9 of the converter 5
When the current is flowing through the U-phase to the X-phase from the U-phase, the output current is zero and this is defined as I0. GTO9 and GTO14
The current vector when current flows from the U-phase to the Z-phase when the current flows from the U-phase to the Z-phase is I1, and the current vector when the current flows from the V-phase to the Z-phase when the GTO10 and the GTO14 are energized is I2. The current vector when GTO12 is energized and the current flows from the V phase to the X phase is I3, and the current vector when GTO11 and GTO12 are energized and the current flows from the W phase to the X phase is I4. , GT
When O11 and GTO13 are energized and a current is flowing from the W-phase to the Y-phase, the current vector is I5, and GTO9 and GTO9 are G5.
The current vector when the current flows from the U-phase to the Y-phase when the TO13 is energized is defined as I6. As described above, one converter is composed of I0, I1, I2, I3, I4, I5, and I6.
Can generate the same current vector. FIG. 28 shows all the current vectors that can be generated by the four multiplexed current source converters shown in FIG. 26, and 61 current vectors can be generated by combining four unit converters. For example, the vector I111 indicates that the three transducers determine the current vector I1 as 1
Converters are generating the vector I0.
Vector I6611 is a state where two converters generate vector I6 and two converters generate vector I1. The same applies hereinafter.

In a conventional multiplex converter, when a command vector of the AC output current of the converter is given, the output possible current vector closest to the command value vector is selected so that the converter generates the signal. And To select the output possible vector closest to the command value vector, as shown in FIG. 28, the space vector diagram is divided into regular hexagonal areas surrounding each output possible vector, and the vector corresponding to the area where the command value vector exists is selected. It is equivalent to The control circuit shown in FIG. 27 is based on a vector selection algorithm based on this region division.

In FIG. 27, an AC current command value generator 4
5 is the output current command value vector of the converter, U, V, W
The coordinates are given as components RIU1, RIV1, and RIW1. The three-phase to two-phase converter 46 composed of an adder and a multiplier calculates the components RIU1 and RI on the U, V, and W coordinates by the following operation.
V1 and RIW1 are converted into components RIA1 and RIB1 on the A and B coordinates. However, the A axis is an axis parallel to the U axis, and the B axis is an axis advanced by 90 degrees with respect to the A axis.

[0007]

RIA1 = RIU1− (RIV1 + RIW1) / 2 RIB1 = (RIV1−RIW1) * 1.732 / 2 The output enable vector generator 47 outputs all output enable vector values that can be generated by the multiplex converter to the A axis B Axis coordinate values (InA,
InB). Region division space vector diagram generator 4
8 generates a space vector diagram divided into regions as shown in FIG. The region determination and vector selection circuit 49 determines which region of the region divided space vector diagram contains the command value vector (RIA1, RIB1), and selects an output vector In corresponding to the region. The vector-to-three-phase converter 50 generates a GTO switching pattern corresponding to the output enable vector In selected by the area determination and vector selection circuit 49. The gate signal generation circuit 51
G of the multiplex converter 52 composed of the converters 5 to 8 in FIG.
Generates a TO firing pulse.

As shown in the figure, a multiplex current type converter has a converter which uses a DC power supply and has a load on the AC side and a power supply on the AC side. There are also configurations. There are many things that have the same operation and technical issues just because they are called differently. Since the problems to be solved by the present invention are also common, they are treated as multiple current type converters without distinguishing them.

[0009]

The following is a description of FIG.
Consider FIG. 29 in which an angle 0 to 60 degrees portion of FIG.
This is intended to be "enlarged" for easy viewing, and the generality of the PWM method described below is not lost.

In FIG. 29, the command vector Ir is I11
Consider a case in which the area surrounding 1 has been moved to the area surrounding I112. As the converter output current changes from I112 to I112, the output current fluctuates through the capacitor and the motor leakage inductance. In a current source inverter, resonance suppression control is generally performed to suppress resonance caused by a capacitor and a motor leakage inductance. Since the resonance suppression control tries to suppress the fluctuation of the output current, the command vector is pulled back,
As a result, the command vector enters the area of I111. When the converter outputs the current of I111 again, the resonance suppression control works in the opposite direction, and the current command vector moves in the direction of I112.
After repeating this several times, it is stabilized at I112. This is shown in FIG.

When such "chattering" occurs, the number of times of switching of the GTO increases, and the power loss accompanying the switching also increases. One method of reducing chattering is to reduce the gain of the resonance suppression control system. However, if the gain is excessively reduced, the original resonance suppression becomes insufficient, and the transient response deteriorates.

Accordingly, an object of the present invention is to provide a control device of a power conversion device capable of reducing "chattering" and reducing switching loss without reducing the gain of the resonance suppression control system.

[0013]

According to a first aspect of the present invention, there is provided a control apparatus for a power converter, comprising a plurality of converters each having a self-extinguishing type switching element connected in a bridge. A plurality of DC reactors for smoothing the DC current of the plurality of converters, AC terminals of the plurality of converters are connected in common and connected to an AC load, and the plurality of DC reactors are respectively connected to the plurality of DC reactors. In a power converter connected in series to a positive terminal and a negative terminal of a converter, an output vector output immediately before by the power converter is stored by a selection vector storage unit, and is divided by a region division vector diagram generating unit. When generating a vector diagram,
The area of the region including the immediately preceding output vector stored in the selected vector storage unit is enlarged more than usual to create a region division vector diagram. Then, using the area division vector diagram, an output available vector corresponding to the area including the command value vector is selected as the next output vector. This increases the possibility that the vector currently output by the power conversion device will be selected again. As a result, the number of times of switching is reduced, and the switching loss is reduced.

In the control device for a power converter according to a second aspect of the present invention, a plurality of converters each having a self-extinguishing type switching element connected in a bridge, and an AC output of each converter are connected to a primary side. A power converter configured to include a plurality of transformers and controlling a power converter that is connected to an AC load by commonly connecting secondary terminals of the plurality of transformers,
The output vector output immediately before by the power conversion device is stored by the selection vector storage unit, and when the region division vector diagram generation unit generates the region division vector diagram, the output vector includes the immediately preceding output vector stored in the selection vector storage unit. A region division vector diagram is created by enlarging the area of the region more than usual. Then, using the area division vector diagram, an output available vector corresponding to the area including the command value vector is selected as the next output vector. This increases the possibility that the vector currently output by the power conversion device will be selected again. As a result, the number of times of switching is reduced, and the switching loss is reduced.

According to a third aspect of the present invention, in the power converter control device for controlling the multi-level output power converter for outputting a multi-level voltage, the output vector output by the power converter immediately before is output. Is stored by the selection vector storage means, and when the area division vector diagram is generated by the area division vector diagram generation means, the area of the area including the immediately preceding output vector stored in the selection vector storage means is enlarged more than usual. Create a region division vector diagram.
Then, using the area division vector diagram, an output available vector corresponding to the area including the command value vector is selected as the next output vector. This increases the possibility that the vector currently output by the power conversion device will be selected again. As a result, the number of times of switching is reduced, and the switching loss is reduced.

In the control device for a power conversion device according to claim 4 of the present invention, a region surrounding each output enable vector in the region division vector diagram is a regular hexagonal region. Claim 5 of the present invention
In the control device of the power converter according to the above, the area surrounding each output enable vector in the area division vector diagram is defined as a rhombic area.

[0017]

Embodiments of the present invention will be described below with reference to the drawings. The configuration of the main circuit of the multiplex current source converter according to the first embodiment of the present invention is the same as the conventional configuration shown in FIG.

It is also assumed that the DC currents flowing through converters 5 to 8 are controlled equally. FIG. 1 is a configuration diagram of a control circuit according to a first embodiment of the present invention,
It is characterized in that the region division space vector diagram is changed according to the vector output immediately before.

In FIG. 1, an AC current command generator 45
Is the AC current command (RIU1, RIV1, R
IW1), and the three-phase to two-phase converter 46 outputs the AC current commands (RIU1, RIV1, RV) generated by the current command generator 45.
IW1) is converted into a current command (RIA1, RIB1) in a rectangular coordinate system. The output possible vector generator 47 converts all the output possible vector values that can be generated by the multiplex converter into A-axis and B-axis coordinate values (InA, InB), and outputs the selected vector storage circuit 5.
3 stores the vector selected in the previous vector selection operation. This vector is a vector that is actually output by the converter until immediately before the vector selected by the current selection operation is actually output (the output of the area determination and vector selection circuit 55 described later).

An area division space vector diagram generator 54 calculates an area division space vector used for the current vector selection from the output enable vector generated by the output enable vector generator 47 and the previous selection vector obtained from the selection vector storage circuit 53. Generate figure.

The region determination and vector selection circuit 55 determines which region of the region divided space vector diagram contains the command value vector (RIA1, RIB1), and selects an output vector In corresponding to that region.

The vector-to-three-phase converter 50 generates a GTO switching pattern corresponding to the output enable vector In selected by the area determination and vector selection circuit 55, and the gate signal generation circuit 51 generates the GTO switching pattern shown in FIG. Vessels 5-8
Generates a firing pulse for the GTO of the multiplex converter 52.

Here, the operation of the region division space vector diagram generator 54 and the region judgment and vector selection circuit 55 which are the characteristic portions of the present embodiment will be described with reference to FIGS. FIG. 2 shows a part of a space vector diagram when the previous selection vector is I111. The region division space vector diagram generator 54 includes a vector I111 of an output enable vector from the output enable vector generator 47 based on the vector I111 output from the converter immediately before and stored in the selection vector storage circuit 53. A region division space vector diagram in which the region to be expanded is expanded is generated. That is, the area of the regular hexagon including the vector I111 is larger than that in the normal area division (indicated by a dotted line).

The region determination and vector selection circuit 55 determines which region of the region division space vector diagram contains the command value vector and selects an output vector corresponding to that region. Because of the spread, the vector I111 is continuously selected for a while even if the command vector Ir crosses the boundary (dotted line) of the normal area division. When the vector I112 is selected beyond the boundary of the solid line in FIG. 2, a region division space vector diagram in which the region of the vector I112 is widened as shown in FIG. For this reason, even if the resonance suppression control operates, the vector I111 is not immediately selected.

As described above, in this embodiment, the currently selected vector is easily selected next time by using the area division in which the area of the area including the currently selected vector is enlarged. Therefore, chattering is reduced, and the number of times of switching can be reduced.

Next, a flow in the case of performing the software processing of the first embodiment will be described with reference to FIG. However, here, only the portions corresponding to the region division space vector diagram generator 54 and the region determination and vector selection circuit 55 of FIG. 1 which are the characteristic portions of the present embodiment will be described.

First, in step 1, the current command value and the previous selection vector are converted into a rectangular coordinate system. In step 2, a vector corresponding to an area including the command value vector is selected as a candidate vector in the same area division as in the related art. I do.

In STEP 3, the previous selected vector is compared with the candidate vector.
If not, it jumps to STEP6. In STEP 4, the candidate vector is set to the current selection vector.

In STEP 5, the selection vectors are U, V,
Convert to a component on the W coordinate. In STEP6, it is determined whether the candidate vector is an area next to the previous selection vector. If the area is an adjacent area, the process jumps to STEP7. If not, the program jumps to STEP8.

In STEP 7, a vector corresponding to the area including the command vector is set as the current selection vector by area division in which the area of the area including the previous selection vector is increased.

In STEP 8, the candidate vector is set to the current selection vector. In other words, first, a vector that is a candidate for the current selection vector is determined in the same divided region as before, and only when the candidate vector is a vector in a region adjacent to the previous selection vector, the region including the previous selection vector is expanded. The current selection vector is determined in the divided area.

Thus, when processing is performed by software, it is not necessary to always perform a region division in which the area of the region including the previous selection vector is increased. Next, the second embodiment of the present invention
An embodiment will be described.

FIG. 5 is a configuration diagram of a control circuit according to a second embodiment of the present invention. In FIG. 5, an area division space vector diagram generator 56, an area determination and vector selection circuit 57
Except for the above, the configuration is the same as that of the first embodiment shown in FIG.

The second embodiment shown in FIG. 5 is based on the space vector diagram shown in FIG. In this case, the area surrounding each output possible vector is a rhombus. However,
30 degrees, 90 degrees, 150 degrees, 210 degrees, 270
The area surrounding the output possible vector on the straight line of 330 degrees is a figure in which half of the rhombus is pasted. In the vector selection using the space vector diagram divided as described above as it is, chattering accompanying resonance suppression control and current control may occur as in the case of hexagonal division.

Here, the operation of the region division space vector diagram generator 56 and the region judgment and vector selection circuit 57 which are the characteristic portions of the present embodiment will be described with reference to FIGS. FIG. 7 shows a part of a space vector diagram when the previous selection vector is I12. The region division space vector diagram generator 56 includes the vector I12 of the output enable vector from the output enable vector generator 47 based on the vector I12 output from the converter immediately before and stored in the selection vector storage circuit 53. A region division space vector diagram in which the region to be expanded is expanded is generated. That is, the area of the rhombus including the vector I12 is larger than that of the normal area division (indicated by a dotted line).

The region determination and vector selection circuit 57 determines which region of the region divided space vector diagram contains the command value vector and selects an output vector corresponding to that region. Because of the spread, the command vector Ir is at the boundary (dotted line) of the normal area division.
, The vector I12 is continuously selected for a while. When the vector I112 is selected beyond the boundary of the solid line in FIG. 7, from the next control operation, as shown in FIG.
A region division space vector diagram in which the region 2 is widened is adopted. Therefore, even if the resonance suppression control operates, the vector I12 is not immediately selected.

As described above, in this embodiment, the currently selected vector is easily selected next time by using the area division in which the area of the area including the currently selected vector is enlarged. Therefore, chattering is reduced, and the number of times of switching can be reduced.

Next, in the second embodiment, another example will be described as a method of expanding a region including the previously selected vector. In FIGS. 9 and 10, not only the region including the vector selected last time, but also the region in the two sides of the rhombus of the region is expanded at the same time.

In FIGS. 11 and 12, four corners of a figure obtained by expanding a region including a vector selected last time as a rhombus are cut off so as to be a convex figure as a whole. These are all intended to make the area containing the command vector or the area adjacent to that area convex. For example, the region containing the vector I1122 in FIG. 7 is no longer convex. A convex shape is a mathematical area A
For any two points P1 and P2 belonging to

[0040]

[Equation 2] αP1 + (1−α) P2, (0 ≦ α ≦ 1) also means that it belongs to the area A. Figure 13 shows examples of convex and non-convex shapes. In a non-convex figure, area A
There are points that are not included in area A even if they are points on any two straight lines belonging to.

If there is a non-convex area, switching may increase or the waveform may be distorted. Therefore, when the area including the vector selected last time is expanded, the area after the change is made convex, so that unnecessary increase in switching and distortion of the waveform can be suppressed.

In the above description, the case where the space vector diagram is divided into regular hexagons and the case where the space vector diagram is divided into rhombuses has been described. It goes without saying that the method helps to reduce unnecessary chattering and to reduce the number of switching times.

Next, the case where the present invention is applied to a multiple voltage source converter will be described. First, the basic configuration of the multiple voltage source converter will be described. FIG. 14 is a configuration diagram of a main circuit of the multiple voltage source converter. In FIG. 14, reference numeral 71 denotes an AC load, and reference numerals 72 to 75 denote voltage source converters for converting DC power into AC power. Each AC terminal is connected to a primary terminal of transformers 76 to 79. The secondary sides of transformers 76-79 are coupled in series and combine the output voltages of each converter. The combined output voltage is connected to AC load 71. The DC input of each converter is commonly connected to a DC voltage source 80.
Here, a diagram is shown in which they are connected in common, but a voltage source may be individually prepared for each converter.

GU1 to GZ4 are self-extinguishing switching elements constituting converters 72 to 75. Also, DU1
DZ4 is a freewheeling diode connected in anti-parallel with the self-extinguishing switching element. Hereinafter, a case where a gate turn-off thyristor (GTO) is used as the self-extinguishing type switching element will be described.

Referring to FIG. 15, a voltage vector that can be generated on the AC side by a single voltage source converter will be described. Here, the V1 vector is the output voltage when U, Y, and Z are fired, the V2 vector is the output voltage when U, V, and Z are fired, and the V3 vector is the output voltage when X, V, and Z are fired. , The V4 vector is the output voltage when X, V, W is fired, the V5 vector is the output voltage when X, Y, W is fired, and the V6 vector is U, Y, W The output voltage at this time, the V0 vector, corresponds to the output voltage (zero voltage) when U, V, W or X, Y, Z is fired.

FIG. 16 shows a voltage vector diagram that can be generated by the four-multiplex voltage source converter. Here, for example, V1122 is 4
Two of the unit converters are vectors realized by outputting a V1 vector and the remaining two output V2 vectors.

Also in a multiple voltage source converter, a method has been proposed in which a space vector diagram is divided into regular hexagonal regions, a region where a voltage command vector exists is determined, and an output enable vector corresponding to the region is selected. (Japanese Patent Application Hei 9-435
No. 15). FIG. 16 shows a regular hexagonal area division. The same patent also proposes vector selection in rhombic division or arbitrary area division. FIG. 17 shows an example in which the space vector diagram is divided into rhombic regions.

FIG. 18 is a block diagram of a control circuit according to the third embodiment of the present invention, which is characterized in that a region division space vector diagram is changed according to a vector output immediately before. .

Referring to FIG. 18, an AC voltage command generator 81
Is the AC voltage command (RVU1, RVV1, RV
VW1), and the three-phase to two-phase converter 82 outputs the AC voltage commands (RVU1, RVV) generated by the AC voltage command generator 81.
1, RVW1) is the current command (RVA1, RVB) in the rectangular coordinate system.
Convert to 1). The output possible vector generator 83 converts all output possible vector values that can be generated by the multiplex converter into the A-axis B
Converted to the form of the axis coordinate values (VnA, VnB), the selected vector storage circuit 84 stores the vector selected in the previous vector selection operation. This vector is a vector that is actually output by the converter until immediately before the vector selected by the current selection operation is actually output (the output of the area determination and vector selection circuit 86 described later).

The region division space vector diagram generator 85 calculates the region division space vector used for the current vector selection from the output possible vector generated by the output possible vector generator 83 and the previous selection vector obtained from the selection vector storage circuit 84. Generate figure.

The region determination and vector selection circuit 86 determines which region of the region divided space vector diagram contains the command value vector (RVA1, RVB1), and selects an output vector Vn corresponding to that region.

A vector-to-three-phase converter 87 generates a GTO switching pattern corresponding to the output enable vector Vn selected by the area determination and vector selection circuit 86, and the gate signal generation circuit 88 converts the GTO switching pattern shown in FIG. Container 72 ~
The multiplex converter 89 comprising 75 generates a GTO firing pulse.

Here, referring to FIG. 19 and FIG. 20, a region division space vector diagram generator 8 which is a feature of the present embodiment will be described.
5 and the operation of the area determination and vector selection circuit 86 will be described.

FIG. 19 shows a part of a space vector diagram when the previous selection vector is V122. The region division space vector diagram generator 85 includes a selection vector storage circuit 8.
4 is the vector V output by the converter immediately before
On the basis of the output vector 122, an area including the vector V122 of the output possible vector from the output vector generator 83 is expanded to generate an area division space vector diagram. That is, the area of the regular hexagon including the vector V122 is larger than that in the normal area division (indicated by a dotted line).

The region determination and vector selection circuit 86 determines which region of the region divided space vector diagram contains the command value vector, and selects an output vector corresponding to that region. Because of the spread, the vector V122 is continuously selected for a while even if the command vector Vr exceeds the boundary (dotted line) of the normal area division. Beyond the boundary of the solid line in FIG.
Is selected, a region division space vector diagram in which the region of the vector V222 is widened as shown in FIG. Therefore, even if the control such as the current control works, the vector V122 is not immediately selected.

As described above, in the present embodiment, the currently selected vector is easily selected next time by using the area division in which the area of the area including the currently selected vector is enlarged. Therefore, chattering is reduced, and the number of times of switching can be reduced.

Further, as shown in the current source, the same operation can be performed even in a rhombic region division. FIG. 21, FIG.
2 shows an example of area division in the case of diamond division. FIG. 21 shows a part of the space vector diagram when the previously selected vector is V12, and not only the region including the previously selected vector, but also the rhombic regions in the two sides of the region are simultaneously expanded. ing.

In FIG. 21, since the region including the vector V12 is widened, the vector V12 is continuously selected for a while even if the command vector Vr exceeds the boundary (dotted line) of the normal region division. When the vector V122 is selected beyond the boundary of the solid line in FIG. 21, a region division space vector diagram in which the region of the vector V122 is widened as shown in FIG. Therefore, even if the control such as the current control works, the vector V12 is not immediately selected.

Here, the case where the space vector diagram is divided into regular hexagons and the case where the space vector diagram is divided into rhombuses has been described. However, also in the case where the space vector diagram is divided into arbitrary figures, the area of the region including the previously selected vector is increased. Similarly, the method helps reduce unnecessary chatter and reduce the number of switching times.

Next, the case where the present invention is applied to a multilevel output converter will be described. First, the basic configuration of the multilevel output converter will be described. FIG. 23 is an example of a main circuit configuration of the multilevel output power converter, and includes + 2E, + E,
This is a five-level output power converter capable of outputting voltages of 0, -E, and -2E. In the figure, U is the U phase, V
Denotes a V-phase and W denotes a W-phase single-phase power converter.
Also, Su1 to Su8, Sv1 to Sv8, Sw1 to Sw8 are self-extinguishing elements, Du1 to Du8, Dv1 to Dv8, Dw1 to Dw8 are diodes connected in antiparallel to the self-extinguishing elements, Dcu1 to Dcu.
6, Dcv1 to Dcv6, Dcw1 to Dcw6 are clamping diodes, E1 is a divided voltage source between a first terminal and a second terminal of the DC voltage source E, and E2 is a second voltage source of the DC voltage source E. A divided voltage source between the terminal and the third terminal, E3, is a divided voltage source between the third terminal and the fourth terminal of the DC voltage source E, E3.
Reference numeral 4 denotes a divided voltage source between the fourth terminal and the fifth terminal of the DC voltage source E.

In the five-level output power converter configured as described above, for example, between the self-extinguishing elements Su4 and Su5 of the U-phase converter of U, when the self-extinguishing elements Su1 to Su4 are on, + E1 + E2. Voltage (E1 = E2 = E3 = E4 = E
+ 2E voltage level).
When Su5 is on, the voltage of + E2 (also E voltage level) is 0, when the self-extinguishing elements Su3 to Su6 are on, the voltage is 0, and when the self-extinguishing elements Su4 to Su7 are on, -E3 (-E3). When the self-extinguishing elements Su5 to Su8 are ON.
A voltage of E3 -E4 (the voltage level of -2E) is output,
It can output five-level voltages of + 2E, + E, 0, -E, and -2E.

FIG. 24 shows the relationship between the switch states of the U-phase elements Su1,... Su8 and the U-phase output Su. A voltage obtained by multiplying Su by E is output to a U-phase output terminal taken out from between the elements Su4 and Su5. Similarly, a table showing the relationship between the phase outputs Sv and Sw and each element switch state can be written for the V phase and the W phase, and the output voltage of the entire converter is (Su, Sv, S
w).

FIG. 25 shows a voltage vector diagram that can be generated by the five-level output converter. In each vector, (Su, Sv, Sw) capable of outputting the vector is written. Some vectors can be realized in more than one firing state.

In the multi-level output converter as well, the space vector diagram is divided into regions including each outputable vector,
A method has been proposed in which a region where a voltage command vector exists is determined, and an output enable vector corresponding to the region is selected.

Then, for the multilevel converter,
As in the case of the current-source converter and the voltage-source converter described above, the previously selected vector is stored, and the command vector exists based on the area division space vector diagram obtained by expanding the area including the previously selected vector. By determining the area and selecting the current vector, unnecessary chattering can be reduced and the number of switching times can be reduced.

[0066]

As described in detail above, according to the present invention,
In the multiple current source converter, the multiple voltage source converter, and the multi-level output converter, unnecessary chattering can be reduced and the number of times of switching can be reduced, so that switching loss can be reduced. Further, accordingly, components such as a heat sink can be reduced in size, and the entire device can be reduced in size.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a control circuit according to a first embodiment of the present invention.

FIG. 2 is a diagram of a regular hexagonal division space vector when a previous selection vector is I111.

FIG. 3 is a diagram of a regular hexagonal division space vector when a previous selection vector is I112.

FIG. 4 is a flowchart when software processing is performed on the first embodiment;

FIG. 5 is a configuration diagram of a control circuit according to a second embodiment of the present invention.

FIG. 6 is a space vector diagram obtained by dividing a possible output vector of a four-multiplex current source converter into a rhombic region.

FIG. 7 is a diagram of a diamond-shaped divided space vector when the previous selection vector is I12.

FIG. 8 is a diamond-shaped divided space vector diagram when the previous selection vector is I122.

FIG. 9 is a diagram showing another example of division of a diamond-shaped division space vector diagram.

FIG. 10 is a diagram showing another example of division of a diamond-shaped division space vector diagram.

FIG. 11 is a diagram showing another example of division of a diamond-shaped division space vector diagram.

FIG. 12 is a diagram showing another example of division of a diamond-shaped division space vector diagram.

FIG. 13 is a diagram showing an example of a convex figure and a non-convex figure.

FIG. 14 is a configuration diagram of a main circuit of a multiple voltage source converter to which the present invention is applied.

FIG. 15 is a diagram illustrating a voltage vector that can be generated on the AC side by a single voltage source converter included in the multiple voltage source converter.

FIG. 16 is a diagram showing voltage vectors that can be generated by a four-multiplex voltage source converter.

FIG. 17 is a space vector diagram obtained by dividing an output possible vector of the four-multiplex voltage source converter into a rhombic region.

FIG. 18 is a configuration diagram of a control circuit according to a third embodiment of the present invention.

FIG. 19 is a diagram of a regular hexagonal division space vector when the previous selection vector is V122.

FIG. 20 is a diagram of a regular hexagonal divided space vector when the previous selection vector is V222.

FIG. 21 is a diagram of a diamond-shaped divided space vector when the previous selection vector is V12.

FIG. 22 is a diagram of a diamond-shaped divided space vector when the previous selection vector is V122.

FIG. 23 is a main circuit configuration diagram of a multilevel output power converter to which the present invention is applied.

FIG. 24 is a relationship diagram between a U-phase element and a U-phase output Su.

FIG. 25 is a diagram showing voltage vectors that can be generated by the multilevel output power converter shown in FIG. 23.

FIG. 26 is a main circuit configuration diagram of a multiplex current type converter.

FIG. 27 is a configuration diagram of a conventional control circuit.

FIG. 28 is a view showing current vectors that can be generated on the AC side by the four-multiplex current source converter shown in FIG. 1;

FIG. 29 illustrates a chattering phenomenon.

FIG. 30 illustrates a chattering phenomenon.

[Explanation of symbols]

1 ... AC load 2-4 ... Capacitor 5-8 ... Converter 9-32 ... GTO 33-40 ... DC reactor 41-44 ... DC power supply 45 ... AC current command generator 46 ... 3 Phase → two-phase converter 47... Outputable vector generator 48... Area division space vector diagram generator 49... Area determination and vector selection circuit 50... Vector → three-phase converter 51... Gate signal generation circuit 52 ... Multiplex converter 53... Selected vector storage circuit 54... Region divided space vector diagram generator 55... Region decision and vector selection circuit 56... Region divided space vector diagram generator 57. 71 AC load 72-75 Voltage source converter 76-79 Transformer 80 DC voltage source GU1-GZ4 GTO DU1-DZ4 Freewheeling Diode 81 AC voltage command generator 82 Three-phase to two-phase converter 83 Outputable vector generator 84 Selected vector storage circuit 85 Region divided space vector diagram generator 86 Region determination And vector selection circuit 87... Vector to three-phase converter 88... Gate signal generation circuit 89... Multiple voltage source converters Su1 to Su8, Sv1 to SV8, Sw1 to Sw8. ... Dv8, Dw1 to Dw8... Diodes Dcu1 to Dcu6, Dcv1 to Dcv6, Dcw1 to Dcw6.
Clamping diodes E1, E2, E3, E4, E5... Divided voltage sources U, V, W... U, V, W of three-phase multilevel converter
Phase single phase power converter

Claims (5)

[Claims] 1. A converter comprising a plurality of converters in which self-extinguishing type switching elements are connected in a bridge, and a plurality of DC reactors for smoothing DC currents of the plurality of converters, and AC terminals of the plurality of converters. And a power converter connected to an AC load and controlling the power converter in which the plurality of DC reactors are connected in series to the positive and negative terminals of the plurality of converters, respectively. In the device, vector command means for giving a command value vector of an AC output current of the power conversion device; output-capable vector generation means for giving all output-capable vectors of the AC output current that can be generated by the power conversion device; A selection vector storage means for storing an output vector output immediately before the apparatus; and an output vector based on an output enable vector from the output enable vector generation means. When generating a region division vector diagram surrounding the force possible vector, a region division vector diagram generation unit for generating a region division vector diagram such that a region including the immediately preceding output vector stored in the selection vector storage unit is widened. It is determined which region of the region division vector diagram generated by the region division vector diagram generating unit the command value vector from the vector instruction unit is included in, and an output possible vector corresponding to the region where the command value vector exists Control means for controlling the power supply state of the self-extinguishing type switching element in accordance with the output vector selected by the vector selection means. apparatus. 2. The plurality of transformers comprising a plurality of converters each having a self-extinguishing type switching element connected in a bridge, and a plurality of transformers each having an AC output of each converter connected to a primary side. A control device for controlling the power converter connected to the AC load by connecting the secondary terminals of the power converter in common, a vector command means for providing a command value vector of an AC output current of the power converter. An output enable vector generating means for providing all output enable vectors of the AC output current that can be generated by the power conversion device; a selection vector storage means for storing an output vector output immediately before by the power conversion device; When generating a region division vector diagram surrounding each output available vector based on the output available vector from the generating unit, the region division vector diagram is stored in the selected vector storage unit. Region division vector diagram generating means for generating a region division vector diagram so that the region including the immediately preceding output vector becomes wide, and a region in which the command value vector from the vector commanding unit is generated by the region division vector diagram generation unit A vector selecting unit that determines which region of the divided vector diagram is included in the vector, selects and outputs an outputable vector corresponding to the region where the command value vector exists, and outputs the vector according to the output vector selected by the vector selecting unit. A control device for a power conversion device, comprising: means for controlling a conduction state of the self-extinguishing type switching element. 3. A control device for a power conversion device for controlling a multi-level output power conversion device for outputting a multi-level voltage, comprising: vector command means for giving a command value vector of an AC output current of the power conversion device; Output possible vector generation means for providing all output possible vectors of the AC output current that can be generated by the conversion device; selection vector storage means for storing the output vector output immediately before the power conversion device; and output possible vector generation means. When generating a region division vector diagram surrounding each output possible vector based on the output possible vector, a region division vector diagram is generated so that the region including the immediately preceding output vector stored in the selected vector storage unit is widened. Means for generating an area division vector diagram, and a command value vector from the vector A vector selection unit that determines which region of the region division vector diagram generated by the vector diagram generation unit is included, and selects and outputs an outputable vector corresponding to the region where the command value vector exists; A control device for a power conversion device, comprising: means for controlling an energization state of the self-extinguishing switching element according to an output vector selected by the means. 4. The control device for a power conversion device according to claim 1, wherein a region surrounding each outputable vector in the region division vector diagram is a regular hexagonal region. Control device for the power converter. 5. The control device for a power conversion device according to claim 1, wherein a region surrounding each of the output enable vectors in the region division vector diagram is a rhombic region. Control device for power converter.