JPH11154943A - Serial interface circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a circuit which can be applied to data transmission at high speed by detecting a timing of collating a synchronizing pattern by detection at the time of change from a second logical level to a first logical level. SOLUTION: When serial data is not transmitted from a data signal line, a logical level is fixed to the first logical level to fix the second logical level to the leading bit of a synchronizing pattern and to fix the first logical data to the next bit. In this circuit, a collation part 8 collates the three-bit pattern of a part suitable for detecting a synchronizing pattern among 20 bits latched by a received data shift register 5 with a synchronizing pattern 010 stored in a synchronizing pattern storing part 7 with a timing detected by a count value from a counter 9, and when they are matched with each other, a coincidence signal is given to a clock frequency dividing circuit 10.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a serial interface circuit for performing an interface process on transmitted serial data. For example, the present invention relates to a serial interface circuit between a monitoring control panel such as a digital transmission device or a digital switching device and a data input / output panel. It can be applied to serial data transmission.

[0002]

2. Description of the Related Art For example, a digital transmission apparatus, though not shown, monitors a plurality of data input / output boards for data transmission processing of a communication channel and monitors and controls the state of each data input / output board. And a monitoring control panel.

Conventionally, the monitoring control panel and each data input / output panel are connected by three signal lines for a clock signal, transmission / reception data and a scan signal, respectively, and are monitored by a so-called three-wire interface system. Although serial data transmission of control data has been performed, the number of wires has been increased when connecting to a large number of data input / output boards, and a reduction in the number of wires has been required.

A conventional serial interface circuit capable of responding to such a reduction in the number of wirings is disclosed in Japanese Patent Application No. Hei 9-1 / 1991.
No. 36531 is shown in the specification and the drawings, and the monitoring control panel and each data input / output panel are respectively connected only by data signal lines to realize transmission and reception of monitoring control data.

That is, since the data input / output panel is connected only by the data signal line, the data input / output panel receives the supervisory control data transmitted from the supervisory control panel with a clock having a frequency eight times as high as the transmission clock, and sets a predetermined synchronization pattern. The reproduction clock is generated by collating the bit number eight times as large as the number of bits, and thereafter, the monitor control data is transmitted and received based on the reproduction clock.

[0006]

However, in the conventional serial interface circuit, it is necessary to always collate eight times the number of bits with respect to a predetermined synchronization pattern. There is a problem that it cannot be applied to high-speed data transmission.

Therefore, there has been a demand for a serial interface circuit applicable to high-speed data transmission. Such demands are being made not only for digital transmission equipment but also for many equipment employing serial data transmission.

[0008]

In order to solve the above-mentioned problems, a first aspect of the present invention is connected to an opposing serial interface circuit by a data signal line, and a plurality of bits are provided at the start of one communication period. In the serial interface circuit to which serial data to which a synchronous pattern is added is given from the opposing serial interface circuit, (1) the data signal line is the first signal when serial data is not transmitted from the opposing serial interface circuit. (2) The first two bits of the synchronization pattern are respectively set to a second logic level different from the first logic level and the first logic level, and (3) A clock for allowing the opposing serial interface circuit to perform a synchronous transmission operation during data transmission. A clock oscillation unit for oscillating a high-speed clock signal having a frequency N times the frequency of the signal,
(4) shift register means for latching serial data from a data signal line based on the high-speed clock signal oscillated by the clock oscillating means; and (5) a latch data pattern latched by the shift register means, Edge detection means for detecting a transition edge from the second logic level to the first logic level; and (6) a latch timing determined based on a time detected by the edge detection means, and latched by the shift register means. (7) a clock signal after frequency division is input based on a time when the data pattern matches the synchronization pattern, and (7) a time when the matching means detects a match between the two patterns. A clock that divides the high-speed clock signal from the clock oscillating means by 1 / N so as to be substantially synchronized with the serial data. And click dividing unit, (8) based on the divided clock signal from the clock divider means, and having a data communication means for transmitting and receiving serial data through the data signal line.

According to a second aspect of the present invention, serial data is connected to an opposing serial interface circuit via a data signal line, and serial data to which a synchronization pattern of a plurality of bits is added at the start of one communication period. In a serial interface circuit provided from the serial interface circuit, (1) clock oscillation means for oscillating a high-speed clock signal having a frequency which is N times higher than a frequency of a clock signal for causing the opposing serial interface circuit to perform a synchronous transmission operation at the time of data transmission; (2) shift register means for latching serial data from a data signal line based on a high-speed clock signal oscillated by the clock oscillation means; and (3) a latch data pattern latched by the shift register means, Predetermined number of bits at the beginning of the synchronization pattern A synchronization detecting means for detecting a minute and determining a synchronization timing based on the detection; and (4) a clock signal after frequency division is added to the input serial data based on the time when the synchronization detection means determines the synchronization timing. Clock dividing means for dividing the high-speed clock signal from the clock oscillating means by 1 / N so as to be substantially synchronized; (5)
The serial data is transmitted / received via the data signal line based on the frequency-divided clock signal from the clock frequency dividing means, and an initial pattern of the transmitted / received data is not used for the detection processing of the synchronization detecting means. And a data communication unit for checking whether or not the synchronization pattern is matched.

As described above, according to the first aspect of the present invention, when serial data is not transmitted from the data signal line, the first logical level is fixed, and the first bit of the synchronization pattern is the second logical level. Since the first logic level is defined for the level and the next bit, the timing for comparing the synchronization pattern can be detected by detecting the change from the second logic level to the first logic level. It is not necessary to perform collation, and the number of latch data patterns to be collated can be at least the number of synchronization patterns.

Further, according to the second aspect of the present invention, since the synchronization pattern is provided at the head of the synchronization pattern, only the synchronization pattern is detected from the latch data pattern to determine the synchronization timing. In order to confirm in the data communication means that the data given from the data signal line is the remaining synchronization pattern based on the divided clock signal, the latched data pattern to be compared is synchronously captured. Only the portion corresponding to the application pattern.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS (A) First Embodiment A first embodiment in which a serial interface circuit of the present invention is applied to a digital transmission device will be described below with reference to the drawings.

FIG. 2 is a block diagram showing the configuration of the digital transmission apparatus according to the first embodiment. As shown in FIG. 2, the digital transmission device of the first embodiment
It has a monitoring control panel 200 and a data input / output panel 300 connected to each other by the data signal lines 100. The data signal line 100 is connected to VCC via the resistors 400 and 500 in the monitoring control panel 200 and the data input / output panel 300 and is pulled up. Here, the start of data transmission is always from the monitoring control panel 200, and the relationship between the monitoring control panel 200 and the data input / output panel 300 is a master-slave relationship.

FIG. 3 is an image diagram showing the format of monitoring control data transmitted and received between the monitoring control panel 200 and the data input / output panel 300. The upper part shows the format of the monitoring control data transmitted from the monitoring control panel, and the lower part shows the format of the monitoring control data if the transmitted monitoring control data is for reading (a request for control data from the data input / output panel 300). Data input / output panel 3 based on
This is the format of the monitoring control data transmitted from 00. The middle row shows a standby time for the direction switching control or the like between the transmitted and received monitoring control data. As shown in the upper row, the monitoring control data transmitted from the monitoring control panel has read / write data stored in the first bit, “010” which is a synchronization pattern in the next three bits, and 28 bits of control address data. And odd and even parity bits. After the 8-bit standby, the monitoring control data transmitted from the data input / output panel 300 is composed of 32-bit control data and odd and even parity bits.

As described above, the serial interface circuit of the present invention pulls up the data signal line 100,
Further, by providing the monitoring control data with the synchronization pattern “010”, the monitoring control panel 200 and the data input / output panel 3
This makes it possible to perform data transmission at a high speed with 00, and its configuration is shown in FIG.

As shown in FIG. 1, the serial interface circuit includes a data signal line 100 pulled up,
A driver 2, a receiver 3, a clock oscillation circuit 4,
It includes a reception data shift register 5, an edge detection unit 6, a synchronization pattern storage unit 7, a collation unit 8, a counter 9, a clock frequency dividing circuit 10, and a data transmission / reception unit 11.

The receiver 3 fetches incoming data from the data signal line 100 and supplies the received data to the received data shift register 5 and the data transmitting / receiving unit 11. The driver 2 receives the data output from the data transmitting / receiving unit 11. It drives the data signal line 100 during transmission. The receiver 3 and the driver 2 include a data transmitting / receiving unit 11
The receiver 3 operates alternatively in response to a transmission direction control signal from the receiver 3, and the receiver 3 can operate in a standby state in which transmission and reception are not performed.

The clock oscillation circuit 4 includes a monitoring control panel 200
Oscillates an eight-fold clock signal having a frequency eight times the frequency of the clock signal in the received data shift register 5, edge detection unit 6, matching unit 8, counter 9 And the clock frequency dividing circuit 10. The eight-fold clock signal generated by the clock oscillation circuit 4 is naturally asynchronous with the clock signal in the monitoring control panel 200.

The received data shift register 5 takes in the data supplied from the receiver 3 based on the eight-times clock signal generated by the clock oscillation circuit 4, latches the data therein, and performs a shift operation. The number of stages of the reception data shift register 5 is selected to be 20 stages.

The edge detector 6 partially refers to the first 4 bits of the 20 bits latched in the received data shift register 5 to determine a rising edge which is a rising change point of the level of data from the receiver 3. It is to detect. That is, a change point from "0" to "1" in "010" set as the synchronization pattern is detected. When detecting the rising edge, the edge detecting section 6 supplies a rising edge detection signal to the counter 9.

The synchronous pattern storage unit 7 stores a monitoring control panel 20
Synchronization pattern “0” set in monitoring control data from “0”
10 "is given to the collating unit 8 in parallel and constantly.

The counter 9 starts counting based on an eight-fold clock signal from the clock oscillation circuit 4 when a rising edge detection signal from the edge detection unit 6 is given. The count value is provided to the matching unit 8 and is used for detecting a timing suitable for matching the synchronization pattern by the matching unit 8 to determine the coincidence.

At the timing detected by the count value from the counter 9, the collating unit 8 detects a 3-bit pattern of a portion appropriate for detecting a synchronization pattern among the 20 bits latched in the received data shift register 5. Is compared with the synchronization pattern “010” stored in the synchronization pattern storage unit 7, and when they match, a match signal is given to the clock frequency dividing circuit 10. When the matching signal is given, the matching unit 8 holds the significant logic level of the matching signal until the end of the communication period is instructed by the data transmitting / receiving unit 11.

The clock frequency dividing circuit 10 uses the timing at which the coincidence signal from the collating unit 8 is supplied (the edge at which the coincidence signal changes to a significant logical level) as a phase reference, and uses the 8-times clock supplied from the clock oscillation circuit 4 as a phase reference. The signal is frequency-divided by ８, and the clock signal obtained by frequency division is supplied to the data transmitting / receiving unit 11.

The clock signal output from the clock frequency dividing circuit 10 is not synchronized with the clock signal in the monitoring and control panel 200, but has the same frequency. If a clock signal is transmitted from the monitoring control panel 200, the phase difference between the received clock signal and the clock signal output from the clock frequency dividing circuit 10 is 1 /
It is about eight clock cycles.

That is, the data transmission / reception unit 11 recognizes the start of communication based on the change of the coincidence signal to a significant logic level, and synchronizes with the clock signal output from the clock frequency dividing circuit 10 to transmit and receive the subsequent monitoring control data. Is what you do.

Next, the operation of the first embodiment will be described with reference to FIGS.

Data signal line 100 from monitoring control panel 200
Is received by the receiver 3 and the received data shift register 5 and the data transmitting / receiving unit 1
Given to one.

FIG. 4 is a timing chart showing the operation of the first embodiment. The waveform A is the monitor control data transmitted from the monitor and control device, the waveform B is the eight-fold clock signal oscillated from the clock transmission circuit 4, and the waveform C is 20.
The 20-bit (C0 to C20) value of the reception data shift register 5 selected in the stage, the waveform D indicates the count timing in the counter 9, the waveform E indicates the coincidence signal given from the matching unit 8, and the waveform F indicates the divided clock. 2 shows a clock signal provided from the generation unit 10.

First, when the monitoring control panel 200 and the data input / output panel 300 are not driven, the data signal line 100 is pulled up to VCC.
As shown in the waveform A, the received data becomes “1”.

In the reception data shift register 5, the waveform B
At the rising edge of the eight-time clock signal shown in (1), the received data at that time shown in waveform A is first captured in C0 (), and at the next rising edge, the received data captured in C0 is shifted to C1 and at the same time, It is taken into C0 (). In the next rise, C0 and C1
At the same time, the received data is shifted to C1 and C2, respectively, and at the same time, the received data at that time is taken into C0 ().
1 and C2 are received data respectively.
At the same time as shifting to 1, C2 and C3, the received data at that time is taken in C0 (), and thereafter this process is repeated.

The edge detector 6 refers to the first 4 bits (C0 to C3) of the 20 bits latched in the received data shift register 5 and detects the rising edge of the level of the data received from the receiver 3. Things. That is, at the rise of the eight-times clock signal shown in the waveform B, C3 and C2 are "0" and C1 and C0 are "1".
When, the rising edge is detected and a rising edge detection signal is supplied to the counter 9 ().

In the counter 9, when a rising edge detection signal is given from the edge detection unit 6, counting is started based on an eight-fold clock signal as shown in a waveform D.

When the count value of the counter 9 is an appropriate value for performing the matching judgment by comparing the synchronization pattern, that is, when the rising edge is detected by 2 bits,
The time when counting is performed, that is, the timing at which the received data is just synchronized with the received data, and the received data patterns of C19, C11, and C3 latched in the received data shift register 5 at that time are the 3-bit data stored in the synchronization pattern storage unit 7. It is compared with the synchronization pattern, ie, “010”, and when they match, a match signal is given to the clock frequency dividing circuit 10 ().

In the clock frequency dividing circuit 10, the time of the coincidence signal from the collating unit 8 is given,
The 8-fold clock signal shown in the waveform B is divided by 1/8 with the phase after the clock as the phase reference, and the waveform F obtained by the frequency division is obtained.
Is given to the data transmission / reception unit 11 (), and the data transmission / reception unit 11 performs subsequent data transmission / reception in synchronization with the clock signal. In addition,
In the data transmission / reception unit 11, when a series of transmission / reception of the monitoring control data ends, the collation unit 8 is instructed to end the communication period.

As described above, according to the first embodiment, by pulling up the data signal line and providing the synchronization pattern "010" in the monitoring control data, the synchronization pattern is collated by detecting the rising edge. Can be detected, eliminating the need for constant verification.
Also, the number of bit patterns to be matched can be at least the number of synchronous patterns, and therefore the matching processing time is shorter than in the prior art, and it can be applied to high-speed data transmission.

(B) Second Embodiment Hereinafter, a second embodiment in which the serial interface circuit of the present invention is applied to a digital transmission device will be described with reference to the drawings.

The digital transmission apparatus according to the second embodiment also has a monitoring control panel and a data input / output panel connected to each other by one data signal line, as in the first embodiment. The signal lines are pulled up in the monitoring control panel and the data input / output panel (see FIG. 2), and the relationship between the monitoring control panel and the data input / output panel is a master-slave relationship.

Also, in the digital transmission device of the second embodiment, the format of the monitoring control data transmitted and received between the monitoring control panel and the data input / output panel is the same (see FIG. 3).

As described above, also in the serial interface circuit of the present invention, as in the first embodiment, the data signal line is pulled up, and furthermore, the synchronization pattern "010" is provided in the monitoring control data. 5 enables high-speed data transmission between the monitoring control panel and the data input / output panel. FIG.

As shown in FIG. 5, the serial interface circuit includes a pull-up data signal line 100,
A driver 2, a receiver 3, a clock oscillation circuit 4,
Receive data shift register 5 and synchronization pattern storage 7
, A clock frequency dividing circuit 10, a data transmitting / receiving unit 11,
And a phase detection and synchronization detection unit 12. Here, FIG.
In the figure, the same or corresponding parts as those in FIG. 1 showing the configuration of the first embodiment are denoted by the same reference numerals.

The receiver 3 fetches incoming data from the data signal line 100 and supplies it to the received data shift register 5 and the data transmitting / receiving unit 11. The driver 2 receives the data output from the data transmitting / receiving unit 11. It drives the data signal line 100 during transmission. The receiver 3 and the driver 2 include a data transmitting / receiving unit 11
The receiver 3 operates alternatively in response to a transmission direction control signal from the receiver 3, and the receiver 3 can operate in a standby state in which transmission and reception are not performed.

The clock oscillation circuit 4 includes a monitoring control panel 200
Oscillates an eight-fold clock signal having a frequency that is eight times the frequency of the clock signal in the received data shift register 5, a phase detection and synchronization detection unit 12, a clock division circuit, and the like. 10. The eight-fold clock signal generated by the clock oscillation circuit 4 is, of course,
Is asynchronous with the clock signal at

The received data shift register 5 takes in the data supplied from the receiver 3 based on the eight-times clock signal generated by the clock oscillation circuit 4, latches the data, and performs a shift operation. The number of stages of the reception data shift register 5 is selected to be 20 stages.

The synchronization pattern storage section 7 of the second embodiment stores the first "0" and "1" of the synchronization pattern "010" set in the monitoring control data from the monitoring control panel.
And are always given to the phase detection and synchronization detection unit 12 in parallel with 6 bits.

The phase detection and synchronization detection unit 12 of the second embodiment determines the first “0” and “1” of the synchronization pattern “010” among the 20 bits latched in the reception data shift register 5. In order to detect each of them, continuous 6 bits of an appropriate portion are always collated, and when they are coincident, a coincidence signal is given to the clock frequency dividing circuit 10. When the phase detection and synchronization detection unit 12 supplies the coincidence signal, the phase detection and synchronization detection unit 12 holds the significant logical level of the coincidence signal until the data transmission / reception unit 11 instructs the end of the communication period.

The clock dividing circuit 10 is supplied from the clock oscillating circuit 4 with the timing at which the coincidence signal from the phase detection and synchronization detection section 12 is supplied (change edge of the coincidence signal to a significant logical level) as a phase reference. The octupled clock signal is frequency-divided by １ ／, and the clock signal obtained by frequency division is supplied to the data transmitting / receiving unit 11.

The clock signal output from the clock frequency dividing circuit 10 is not synchronized with the clock signal in the monitoring control panel 200, but has the same frequency. If a clock signal is transmitted from the monitoring control panel 200, the phase difference between the received clock signal and the clock signal output from the clock frequency dividing circuit 10 is 1 /
It is about eight clock cycles.

That is, the data transmission / reception unit 11 recognizes the start of communication based on the change of the coincidence signal to the significant logic level, and synchronizes with the clock signal output from the clock frequency dividing circuit 10 to transmit and receive the subsequent monitoring control data. Is what you do.

Next, the operation of the second embodiment will be described with reference to FIGS.

Data arriving from the data signal line 100 is received by the receiver 3 and supplied to the reception data shift register 5 and the data transmission / reception unit 11.

FIG. 6 is a timing chart showing the operation of the second embodiment. The waveform A is the monitor control data transmitted from the monitor and control device, the waveform B is the eight-fold clock signal oscillated from the clock transmission circuit 4, and the waveform C is 20.
The 20-bit (C0 to C20) value of the reception data shift register 5 selected for the stage, the waveform E is a coincidence signal supplied from the phase detection and synchronization detection unit 12, and the waveform F is supplied from the divided clock generation unit 10. It shows a clock signal.

First, when the monitoring control panel and the data input / output panel are not driven, the data signal line 10
Since 0 is pulled up to VCC, the received data becomes “1” as shown in the waveform A.

In the reception data shift register 5, the waveform B
At the rising edge of the 8 × clock signal shown in FIG. 7, the received data at that time shown in waveform A is first taken into C0, and at the next rising edge, the received data taken into C0 is shifted to C1 and at the same time, the received data at that time becomes C0. It is captured. At the next rising edge, the received data captured by C0 and C1 are shifted to C1 and C2, respectively, and at the same time, the received data at that time is captured by C0. At the next rising edge, the data is further transferred to C0, C1 and C2. The fetched received data is shifted to C1, C2 and C3 respectively, and at the same time the received data at that time is fetched into C0, and thereafter this process is repeated.

In the phase detection and synchronization detection section 12, the first "0" and "1" of the synchronization pattern "010" of the 20 bits latched in the reception data shift register 5 are used.
And 6 in each of the appropriate portions to detect
Bit, ie, C14 for the first "0"
C1 to C9, C6 to C1 are always collated for the next "1", where C14 to C9 are all "0" and C6 to C1
When all 1s are “1”, the coincidence signal shown by the waveform E is supplied to the clock frequency dividing circuit 10.

In the clock frequency dividing circuit 10, four times of the eight-times clock signal from the time when the coincidence signal is
The 8-fold clock signal shown in the waveform B is divided by 1/8 with the phase after the clock as the phase reference, and the waveform F obtained by the frequency division is obtained.
Is supplied to the data transmission / reception unit 11.

In the data transmission / reception section 11, subsequent data transmission / reception is performed in synchronization with the clock signal from the clock frequency dividing circuit 10. Here, in the second embodiment, after confirming that the data received by the first clock signal from the clock frequency dividing circuit 10 is the last “0” of the synchronization pattern, the subsequent data transmission / reception is performed. Done. When the last “0” of the synchronization pattern is not received, or when a series of transmission and reception of the monitoring control data is completed, the phase detection and synchronization detection unit 12 is instructed to end the communication period.

As described above, according to the second embodiment, by pulling up the data signal line and providing the synchronization pattern "010" in the monitoring control data, the first 16 bits of the reception data shift register can be obtained. The clock signal is reproduced by detecting only the first "0" and "1" of the synchronization pattern from the pattern, and the data transmission / reception unit determines that the data received based on the clock signal is the remaining synchronization pattern. Because it can be confirmed, the number of bit patterns to be matched can be reduced, and therefore,
The collation processing time is shorter than in the past, and it can be applied to high-speed data transmission.

(C) Other Embodiments In the above embodiments, the case where the number of data input / output panels is 1 has been described. However, there are a plurality of data input / output panels, and connection with the monitoring control panel is mainly performed by the monitoring control panel. 1 to N star-shaped connection.

In each of the above embodiments, the case where data transmission is always started from the monitoring and control panel has been described. However, the case where data transmission is started from the data input / output panel may be used.

Further, in each of the above embodiments, the data signal line is pulled up by VCC and the synchronization pattern is set to "010".
Has been described, but the same can be applied to the case where the data signal line is connected to the ground via a resistor, pulled down, and "101" is set in the synchronization pattern.

Further, in each of the above embodiments, the case where a clock having a frequency eight times the frequency of the transmission clock from the monitoring control panel is used has been described. However, if the deviation of the reproduced clock signal can be kept within an allowable range, A case where an appropriate number of consecutive bits is detected using a clock of another frequency may be used.

In the second embodiment, the case where the data signal line is pulled up by VCC and "010" is set in the synchronization pattern has been described. However, regardless of the data signal line, the data signal line is synchronized with the head of the synchronization pattern. The same applies to the case where a capture pattern is provided and only the synchronization capture pattern is collated to generate a reproduced clock.

[0064]

As described above, according to the first aspect of the present invention,
When the serial data is not transmitted from the data signal line, it is fixed to the first logical level, the first bit of the synchronization pattern is set to the second logical level, and the next bit is set to the first logical level. This makes it possible to detect the timing at which the synchronization pattern is compared by detecting a change from the second logic level to the first logic level, so that there is no need to always perform the matching, and the number of latch data patterns to be compared is at least synchronized. The number of patterns can be reduced, so that the collation processing time is shorter than in the past, and the present invention can be applied to high-speed data transmission.

According to the second aspect of the present invention, since the synchronization pattern is provided at the head of the synchronization pattern, only the synchronization pattern is detected from the latch data pattern to determine the synchronization timing. In order to confirm in the data communication means that the data given from the data signal line is the remaining synchronization pattern based on the divided clock signal, the latched data pattern to be compared is synchronously captured. Only the portion corresponding to the data pattern can be used, so that the collation processing time is shorter than in the past, and the present invention can be applied to high-speed data transmission.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a serial interface circuit according to a first embodiment.

FIG. 2 is a block diagram illustrating a configuration of the digital transmission device according to the first embodiment.

FIG. 3 is an image diagram showing a format of monitoring control data.

FIG. 4 is a timing chart showing the operation of the first embodiment.

FIG. 5 is a block diagram illustrating a configuration of a serial interface circuit according to a second embodiment.

FIG. 6 is a timing chart showing the operation of the second embodiment.

[Explanation of symbols]

2 ... Driver, 3 ... Receiver, 4 ... Clock oscillation circuit,
5: Received data shift register, 6: Edge detector, 7
... Synchronization pattern storage unit, 8 ... Collation unit, 9 ... Counter, 1
0: clock divider circuit, 11: data transmission / reception unit, 100
... Data signal lines.

Claims (2)

[Claims] A serial data which is connected to an opposing serial interface circuit by a data signal line and to which a synchronization pattern of a plurality of bits is added at the start of one communication period is supplied from the opposing serial interface circuit. In the serial interface circuit, the data signal line is connected to the first line when serial data is not transmitted from the opposing serial interface circuit.
The first two bits of the synchronization pattern are respectively set to the first level.
A second logic level different from the first logic level, which is different from the first logic level, is set to N times the frequency of the clock signal for causing the opposing serial interface circuit to perform the synchronous transmission operation at the time of data transmission. Clock oscillating means for oscillating a high-speed clock signal, shift register means for latching serial data from a data signal line based on the high-speed clock signal oscillated by the clock oscillating means, and latch latched by the shift register means Edge detection means for detecting a change edge from the second logic level to the first logic level from the data pattern; and a collation timing determined based on the detection time by the edge detection means, and latched by the shift register means. Latch data pattern matches the above synchronization pattern. Checking means for checking whether or not the clock signal is synchronized, based on a point in time when the checking means detects a match between the two patterns, such that the clock oscillation is performed so that the frequency-divided clock signal is substantially synchronized with the input serial data. Clock dividing means for dividing a high-speed clock signal from the means by 1 / N, and data communication means for transmitting and receiving serial data via the data signal line based on the divided clock signal from the clock dividing means And a serial interface circuit. 2. Serial data which is connected to an opposing serial interface circuit by a data signal line and to which a synchronization pattern of a plurality of bits is added at the start of one communication period is supplied from the opposing serial interface circuit. Clock oscillating means for oscillating a high-speed clock signal having a frequency which is N times higher than the frequency of a clock signal for synchronous transmission operation at the time of data transmission by the opposing serial interface circuit; Shift register means for latching serial data from the data signal line based on the high-speed clock signal; and detecting a predetermined number of bits on the head side of the synchronization pattern from the latch data pattern latched by the shift register means, Based on this detection A synchronous detecting means for determining a synchronous timing; and a high-speed signal from the clock oscillating means based on a point in time at which the synchronous detecting means determines the synchronous timing, so that the frequency-divided clock signal is substantially synchronized with the input serial data. A clock dividing means for dividing the clock signal by 1 / N; and transmitting and receiving serial data via the data signal line based on the divided clock signal from the clock dividing means. And a data communication unit for checking whether or not the initial pattern of the data does not match the synchronization pattern in a portion not subjected to the detection processing of the synchronization detection unit.