JPH11153642A - Test device and method for semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To stabilize settling time regardless of the capacity of low frequency capacitor, by impressing a first direct current via a power source line of semiconductor device, impressing a second direct current with the same characteristics as the first direct current to the power source line via a capacitor for frequency suppressing voltage fluctuation, and measuring the direct current flowing the power source line. SOLUTION: When a device to be measured is tested, a power source circuit 2 and a power source circuit 6 are simultaneously turned on at a specified time. Therefore, an electric potential difference between the terminal on a power source line 3 side of a capacitor 5 for low frequency and the terminal of the power source circuit 6 side is made 0. Then, output voltages of the circuit 2 and the circuit 6 elevate together. After passing a settling time from a specific time, the voltage of an input terminal 1a becomes stable. So no ringing occurs. The settling time is constant. In circuit 2, after conducting functional test such as source current (load current) measurement, the circuit 2 and the circuit 6 are turned off and the test is terminated.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device test apparatus and method used for testing semiconductor devices.

[0002]

2. Description of the Related Art FIG. 4 is a circuit diagram showing a configuration of a conventional semiconductor device test apparatus. In this figure, reference numeral 1 denotes a device to be measured such as a semiconductor device, and an input terminal 1a
have. Reference numeral 2 denotes a power supply circuit that supplies a DC voltage to the input terminal 1a of the device under test 1 via the power supply line 3. Reference numeral 4 denotes a high-frequency capacitor inserted between the power supply line 3 and GND (ground), and removes high-frequency noise in the power supply line 3. As the high-frequency capacitor 4, a capacitor having a load capacity of 0.1 to 1.0 [μF] is used. Reference numeral 5 denotes a low-frequency capacitor interposed between the power supply line 3 and GND, which suppresses voltage fluctuations in the power supply line 3. As the low-frequency capacitor 5, a capacitor having a load capacity of several [μF] to several tens [μF] and a larger capacity than the high-frequency capacitor 4 is used.

Next, a test procedure using the above-described conventional semiconductor device test apparatus will be described with reference to a flowchart shown in FIG. First, when measuring the power supply current of the device under test 1, in step SA1 shown in FIG. 5, the power supply circuit 2 is turned on. That is, when the power supply circuit 2 is turned on at time t0 shown in FIG. 6A, a power supply current (load current) is output from the power supply circuit 2. Then, this power supply current is charged in the high frequency capacitor 4 and the low frequency capacitor 5, respectively.

After the settling time Ts1 has elapsed from the time t0 shown in FIG. 6A, the voltage at the input terminal 1a is brought into a steady state through a transient state as shown by a waveform H1 shown in FIG. Here, in the transient state, ringing occurs as shown in FIG. FIG. 6B is a waveform diagram showing the voltage waveform of GND. As can be seen from FIG.
The GND voltage is 0 [V].

Here, the settling time Ts1 is defined as
The time from time t0 to time t2 shown in (a), which is the time from when the power supply circuit 2 is turned on until the voltage of the input terminal 1a (power supply line 3) falls to a preset value. Say. In step SA2, the power supply circuit 2 performs a functional test such as measurement of the power supply current (load current), and then in step SA3, the power supply circuit 2 is turned off and the test ends.

[0006]

By the way, in the conventional semiconductor device test apparatus, as can be seen from the waveform H1 shown in FIG. 6 (a), the setting from the rising of the voltage of the input terminal 1a to the steady state. Ring time Ts1
Is the settling time Ts in the voltage waveform H0 of the input terminal 1a when the low-frequency capacitor 5 is not connected.
There is a problem that the length is longer than 0 (time t0 to time t1). This is because a large-capacity low-frequency capacitor 5 must be used. The settling time Ts1 becomes longer as the capacitance of the low-frequency capacitor 5 increases. Moreover, in the conventional semiconductor device test apparatus, ringing occurs as can be seen from the waveform H1 shown in FIG. Therefore, the conventional semiconductor device test apparatus has a problem that the settling time Ts1 varies depending on the load capacitance of the low-frequency capacitor 5. The present invention has been made under such a background, and it is an object of the present invention to provide a semiconductor device test apparatus and method capable of keeping a settling time constant regardless of the load capacitance of a low-frequency capacitor. .

[0007]

According to a first aspect of the present invention, a first power supply for applying a first DC voltage to a semiconductor device via a power supply line, one end of which is connected to the power supply line, A low-frequency capacitor that suppresses voltage fluctuations in the power supply line; a second capacitor connected to the other end of the low-frequency capacitor and having the same characteristics as the first DC voltage to the power supply line via the low-frequency capacitor. And a measuring means for measuring an output current of the first power supply, the second power supply being turned on simultaneously with the first power supply. Further, according to the invention described in claim 2, the first device is connected to the semiconductor device via the power line.
A first step of applying a second DC voltage having the same characteristics as the first DC voltage to the power supply line via a frequency capacitor for suppressing voltage fluctuation of the power supply line at the same time as applying the DC voltage of And a second step of measuring a DC current flowing through the power supply line.

[0008]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing the configuration of the semiconductor device test apparatus according to the first embodiment of the present invention. In this figure, parts corresponding to the respective parts in FIG. 4 are denoted by the same reference numerals, and description thereof will be omitted. In FIG. 1, a power supply circuit 6 is newly provided, and a low-frequency capacitor 5 is interposed between the power supply circuit 6 and the power supply line 3.

A power supply circuit 6 shown in FIG. 1 is provided in parallel with the power supply circuit 2 and supplies a power supply voltage to the power supply line 3 via a low-frequency capacitor 5.

Next, a test procedure using the semiconductor device test apparatus according to the embodiment will be described with reference to a flowchart shown in FIG. First, when testing the device under test 1, in step SB1 shown in FIG.
At time t0 shown in (b), power supply circuit 2 and power supply circuit 6 are simultaneously turned on. That is, at time t
At 0, the potential difference between the terminal on the power supply line 3 side of the low-frequency capacitor 5 and the terminal on the power supply circuit 6 side becomes zero.
Therefore, in this case, since the transient current does not flow into the low-frequency capacitor 5, the load capacitance of the low-frequency capacitor 5 can be apparently regarded as zero. Thereafter, the output voltages of power supply circuit 2 and power supply circuit 6 both increase.

At time t1 when settling time Ts3 has elapsed from time t0 shown in FIG. 3B, the voltage at input terminal 1a is in a steady state as shown by waveform H3. Here, as can be seen from the waveform H3 shown in FIG. 3B, the ringing does not occur in the voltage of the input terminal 1a as in the related art.

Further, the settling time Ts3 shown in FIG. 3B corresponds to the waveform H2 of the voltage at the input terminal 1a when the low-frequency capacitor 5 is not connected, as shown in FIG.
Is almost the same value as the settling time Ts2. This is because the load capacitance of the low-frequency capacitor 5 is regarded as zero as described above.

In step SB2, the power supply circuit 2 performs a function test such as measurement of the power supply current (load current). In step SA3, the power supply circuit 2 and the power supply circuit 6 are turned off to end the test. I do.

As described above, according to the semiconductor device test apparatus of one embodiment of the present invention, the power supply circuit 2 and the power supply circuit 6 are simultaneously turned on, and the load capacitance of the low-frequency capacitor 5 is regarded as apparently zero. Therefore, the settling time can be constant regardless of the load capacitance of the low-frequency capacitor.

[0015]

According to the present invention, since the potential difference between both ends of the low-frequency capacitor is made zero, the load capacitance of the low-frequency capacitor is apparently made zero, and a transient current flows through the low-frequency capacitor. Absent. Therefore, according to the present invention, an effect is obtained that the settling time required until the voltage of the power supply line becomes a steady value can be constant regardless of the load capacitance of the low-frequency capacitor.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a configuration of a semiconductor device test apparatus according to one embodiment of the present invention.

FIG. 2 is a flowchart illustrating a test procedure using the semiconductor device test apparatus according to the same embodiment.

FIG. 3 is a diagram showing voltage waveforms at various parts of the semiconductor device test apparatus according to the same embodiment.

FIG. 4 is a circuit diagram showing a configuration of a conventional semiconductor device test apparatus.

FIG. 5 is a flowchart showing a test procedure using a conventional semiconductor device test apparatus.

FIG. 6 is a diagram showing voltage waveforms at various parts of a conventional semiconductor device test apparatus.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Device under test 1a Input terminal 2 Power supply circuit 3 Power supply line 4 High frequency capacitor 5 Low frequency capacitor 6 Power supply circuit

Claims (2)

[Claims] 1. A first power supply for applying a first DC voltage to a semiconductor device via a power supply line, a low-frequency capacitor having one end connected to the power supply line and suppressing voltage fluctuation of the power supply line. A second DC voltage having the same characteristic as the first DC voltage is applied to the power supply line via the low frequency capacitor, and the second DC voltage is connected to the other end of the low frequency capacitor;
A second power supply that is turned on at the same time as the first power supply; and a measuring unit that measures an output current of the first power supply. 2. A power supply line to a semiconductor device,
Simultaneously applying the first DC voltage, applying a second DC voltage having the same characteristics as the first DC voltage to the power supply line via a frequency capacitor for suppressing voltage fluctuations of the power supply line; And a second step of measuring a direct current flowing through the power supply line.