JPH09178820A - Test device for electronic circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To shorten the settling time of a voltage applying circuit by providing an A/D converter for sampling the voltage signal of the pin terminal of a device to be tested every unit time, a measurement control part, and a DA setting control part. SOLUTION: A certain voltage value is imparted to the data to be set to a DA converter 7 from 0V value, and just after it, settling time characteristics are sampled and measured by an AD converter 10. In a measurement control part 20, the average settling gradient is determined from the above measurement data, whereby the voltage rise/fall characteristic per unit time can be found. This settling inclination is supplied to a DA setting control part 50. The control part 50 calculates the value of a magnification forming a high speed settling based on the settling inclination every time when a new voltage set data D6a is received from the outside by the execution of a device test, and calculates the set data to the converter 7 on the basis of this to perform a continuous setting operation.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit for shortening the settling time of a voltage application circuit for supplying a device under test (DUT).

[0002]

2. Description of the Related Art FIG. 4 shows an example of the principle configuration of a conventional voltage application circuit used in a semiconductor test apparatus. The principle circuit configuration of the voltage applying circuit 300 is as follows: the power amplifier 3, the buffer amplifier 4, the DA converter 7, and the phase adjusting circuit 40.
And other. The voltage application circuit 300 receives the voltage setting data D6a from the outside and generates and supplies a predetermined voltage to the DUT pin end 101, for example, VSIM.
(Voltage source current I measure) and PPS (progr
ammable power supply). The voltage is generated by the amplifier 3 and the feedback circuit so that the voltage corresponding to the analog voltage set and output by the DA converter 7 is supplied to the DUT pin end 101.

By the way, the DUT pin end 1 of the test head
01 is connected and supplied by a long cable wiring 240, and a sensing cable 250 for detecting the voltage signal Vx at the DUT pin end 101 is provided to form a feedback loop so as not to be affected by the voltage drop by the cable wiring 240. The buffer amplifier 4
After being buffered by, the voltage is fed back to the power amplifier 3 to supply a predetermined voltage. The phase adjustment circuit 40 is a phase correction circuit of the power amplifier 3, and is for stabilizing the feedback loop against various load conditions of the DUT pin end 101 by the phase correction capacitors C1 and C2.

As described above, in the configuration of the voltage applying circuit for forming the feedback loop by the long cable, the frequency of the amplifier 3 is prevented in order to prevent the occurrence of abnormal oscillation and ringing due to the phase rotation of the feedback loop under different load conditions. It is necessary to add a phase adjusting circuit 40 that lowers the high frequency band of the characteristics to form a stable feedback loop under any condition. Further, the DUT pin end 101 has a capacitor C110 for high frequency bypass or for medium capacity low frequency bypass.
There is also a form of use in which a device is connected and tested, and stable operation is required even under these load conditions. However, with the provision of the stabilizing phase adjusting circuit 40, the settling time from voltage setting to reaching a predetermined voltage becomes long, and there is a drawback that it takes about 10 msec, for example.

[0005]

As described above, a stable operation is required in the voltage application circuit. Therefore, after the DUT pin 7 is set in the DA converter 7, the settling from the time when the DUT pin end 101 reaches a predetermined voltage is performed.・ This was a practical problem because the time was lengthened and it decreased the throughput of device testing. Therefore, the problem to be solved by the present invention is to shorten the settling time of the voltage application circuit by previously measuring the load state of the DUT pin and providing a settling control means for performing the setting in the shortest time from the measured data. The purpose is to measure.

[0006]

First, in order to solve the above-mentioned problems, in the configuration of the present invention, the voltage signal Vx at the DUT pin end 101 is received, sampled at every unit time, and converted into digital data. AD converter 10 for outputting
Is provided, and the measurement control unit 20 that receives the measurement data from the AD converter 10 and calculates and outputs the settling slope S0 of the DUT pin end 101 that is a load is provided, and the voltage setting to be set in the DA converter 7 from the outside is provided. Data D6a
A DA setting control unit 50 that calculates data for shortening the settling time based on the load settling inclination from the measurement control unit 20 each time the measurement control unit 20 receives it and continuously performs the setting operation in the DA converter 7 is provided. It is used as a constituent means. Accordingly, in the voltage application circuit having the DA converter 7 and the power amplifier 3 and applying the DC voltage to the DUT pin end 101 of the device under test DUT, the load state of the DUT pin is measured in advance, and the shortest set The setting data can be set in a short time by sequentially calculating the setting data of the DA converter so as to obtain the ring time and continuously setting the setting data.

Secondly, in order to solve the above problems, in the configuration of the present invention, the DUT pin end 10 of the voltage applying circuit 300 is used.
A switch 60 for receiving the voltage signals Vx from a plurality of channels and selecting and outputting the voltage signal Vx of any channel is provided, and the voltage signal Vx from the switch 60 is provided.
In response to this, an AD converter 10 is provided for sampling every unit time, converting it into digital data, and outputting it.
A measurement control unit 20 that receives the measurement data from the converter 10 and calculates and outputs the settling slope S0 of the DUT pin end 101, which is a load, for each channel is provided to the DA converter 7 of each channel from the outside. Every time the power setting data D6a is received, data for shortening the settling time is calculated based on the settling slope of the load for each channel from the measurement control unit 20 and is continuously supplied to the corresponding DA converter 7. The constituent means is provided with the DA setting control unit 50b for performing the setting operation. This realizes a short-time settling operation for a plurality of channels of the voltage application circuit.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below in detail with reference to examples.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS In the present invention, the load condition of the DUT pin, that is, the settling inclination is measured in advance, and based on this inclination, the setting data of the DA converter is set so that there is no overshoot and the settling time is the shortest. Is characterized by the method of calculating and sequentially setting.

An embodiment of the present invention will be described below with reference to FIGS. 1 and 2. The principle circuit configuration of the one-channel voltage application circuit of the present invention includes an AD converter 10, a measurement control unit 20, and a DA setting control unit 50 in addition to the voltage application circuit 300 of the conventional configuration. First, the settling slope S0 in the current load state is obtained. That is,
A certain voltage value is given to the setting data for the DA converter 7 from the 0v value, and immediately thereafter, the settling time characteristic is sampled and measured by the AD converter 10 as shown in FIG. That is, the voltage Vx at the DUT pin end 101 is continuously sampled at predetermined time intervals T0 and supplied to the measurement control unit 20. The measurement control unit 20 obtains the average settling slope S0 = ΔV / ΔT from this measurement data. From this, the voltage rise / fall characteristics per unit time can be known. This settling slope S0 value is supplied to the DA setting control unit 50 to complete the measurement.

The DA setting control unit 50 executes new device voltage test data D from the outside by performing the device test.
Each time 6a is received, as shown in FIG. 2 (b), the value of the magnification K for high-speed settling is calculated based on the settling slope S0, and the setting data for the DA converter 7 is calculated based on this value. Dset is calculated and the continuous setting operation is performed. FIG.
In (b), it is an example of dividing the magnification K into 30. The value of the magnification K at the divided unit times T1 to T30 is calculated to be the fastest and shortest value from the settling slope S0 without overshooting. In this example, the first is 3.
0, then 2.0, then 1.5, and so on.
After 11 is an example in which the magnification is 1.0. Here, the scaling factor K means a scaling factor for the difference data value ΔDab = D6b−D6a between the previous voltage setting data D6a and the current voltage setting data D6b.

As a first example, the previous voltage setting data D
Assuming that 6a = 0v and the current voltage setting data D6b = 3v, DA set at the magnification K = 3 of the first T1 time
As data, setting data of Dset = 0v + (3v-0v) × 3 = 9v is calculated and output. Next T2 time multiplication factor K
The DA data set at = 2 is set data of Dset = 0v + (3v-0v) × 2 = 6v, and the DA data set at T10 time magnification K = 1.05 is Dset = 0v +.
The setting data of (3v-0v) × 1.05 = 3.15v is calculated and output. As a second example, the previous voltage setting data D6a = 3v and the current voltage setting data D6b = 1
Assuming v, the DA data set at the magnification K = 3 for the first T1 time is Dset = 3v + (1v-3v) × 3 =
-3v setting data is calculated and output. The subsequent steps are the same as above.

As described above, by measuring the load state of the DUT pin and sequentially calculating and setting the setting data of the DA converter so as to obtain the shortest settling time, the setting data shown in FIG. As shown in (c), it is possible to realize a short settling time which is a fraction of the conventional one.

(Application Example) In the above description of the embodiment, the case where the DA setting control unit 50 calculates and controls the voltage application circuit 300 for one channel has been described. However, as shown in the configuration diagram of FIG. A channel switcher 60 is provided, and the settling slope S of each channel is measured sequentially.
0 is obtained from this, the voltage setting data D6a to be set in the DA converter 7 of each channel is externally received, data for shortening the settling time is calculated, and the setting operation is continuously set in the corresponding DA converter 7. Do D
The A setting control unit 50b may be provided, and the same operation can be performed.

Further, in the semiconductor test equipment, a current application circuit for supplying a predetermined current to the DUT pin, for example, ISVM (curr
ent I source voltage measure), and by providing a means for measuring the settling current in advance by the same method as in the above embodiment, the settling time of the applied constant current can be similarly shortened.

Further, in the description of the above-mentioned embodiments, the semiconductor test apparatus has been described as an example applied to the DUT pin. However, in other applications, it may be applied to another apparatus in which the settling time of DC voltage application is desired to be accelerated. Is also applicable.

[0017]

Since the present invention is configured as described above, it has the following effects. As described above, by measuring the load state of the DUT pin and sequentially calculating and setting the setting data of the DA converter so as to obtain the shortest settling time, a stable feedback loop is obtained. Figure 2 (c) while maintaining
As shown in, it is possible to realize a short settling time which is a fraction of the conventional one, and it is expected that the throughput of the device test will be improved.

[Brief description of the drawings]

FIG. 1 is a control configuration diagram for speeding up settling of a voltage application circuit 300 according to the present invention.

2A and 2B are views for explaining measurement and calculation of the settling slope S0, and FIG. 2B is a unit time T divided into 30 units.
It is an example of each magnification K value from 1 to T30, and (c) is a characteristic example of a high-speed settling result.

FIG. 3 is a diagram showing a voltage application circuit 3 of a plurality of channels of the present invention.
It is an example of a configuration for speeding up the settling of 00.

FIG. 4 is a configuration diagram of a conventional voltage applying circuit 300.

[Explanation of symbols]

 T1 to T30 unit time 3 power amplifier 4 buffer amplifier D6a, D6b voltage setting data 7 DA converter 10 AD converter 20 measurement control unit 40 phase adjustment circuit 50, 50b DA setting control unit 60 switcher 101 DUT pin end C110 capacitor 240 cable wiring 250 Sensing cable 300 Voltage application circuit

Claims (2)

[Claims] 1. A voltage applying circuit having a DA converter (7) and a power amplifier (3) for applying a DC voltage to a DUT pin end (101) of a device under test (DUT), the DUT pin end (101). ) Voltage signal (Vx)
An AD converter (10) for sampling at every unit time and converting into digital data and outputting the digital data is provided, and receives measurement data from the AD converter (10),
A measurement control unit (20) for calculating and outputting the settling inclination of the DUT pin end (101) as a load is provided, and each time the voltage setting data (D6a) to be set in the DA converter (7) is received from the outside, Based on the settling inclination of the load from the measurement control unit (20),
A DC voltage application device comprising a DA setting control unit (50) for calculating data for shortening time and continuously setting the DA converter (7), and including the above. 2. A multi-channel voltage application circuit having a DA converter (7) and a power amplifier (3) for applying a DC voltage to a DUT pin end (101) of a device under test (DUT). A switch (60) is provided for receiving voltage signals (Vx) from a plurality of channels at the DUT pin end (101) of the circuit (300) and selecting and outputting the voltage signal (Vx) of any channel, An AD converter (10) is provided which receives a voltage signal (Vx) from a switch (60), converts it into digital data by sampling at every unit time, and outputs the measured data from the AD converter (10). receive,
A measurement control unit (2) that calculates and outputs the settling inclination of the DUT pin end (101) which is a load for each channel.
0) is provided and each time the voltage setting data (D6a) to be set in the DA converter (7) of each channel is received from the outside, the load setting ring inclination for each channel from the measurement control unit (20) is used as the basis. The DA setting control unit (50b) that calculates data for shortening the settling time and continuously performs the setting operation in the corresponding DA converter (7) is provided. DC voltage application device.