JPH11150941A - Gate circuit for driving gate turn-off thyristor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a gate circuit for driving a gate turn-off(GTO) thyristor, which sufficiently reduces a circuit inductance. SOLUTION: A gate circuit for cutting-off a GTO thyristor is constituted in such a way that it is provided with a path which connects the gate and the cathode of the GTO thyristor, and with a switch for switching, and a capacitor for charging, which are interposed and inserted in series with every path, and that, when it is cut off, the switch is turned on so as to be cut off by pulling a current to the cathode from the gate. In this case, a plurality of paths 11a to 11c, 12a to 12c are connected in parallel across gates G and cathodes K. Respective switches, respective capacitors and the paths 11a to 11c, 12a to 12c are arranged in such a way that electric fields which are generated by loop currents Ipa to Ipc, Iqa to Iqc flowing to the respective paths 11a to 11c, 12a to 12c are offset alternately across the adjacent paths.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a gate circuit for driving a gate turn-off thyristor used in a power conversion device, a large-capacity power electronics device such as a railway, an inverter application product, and the like.

[0002]

2. Description of the Related Art In recent years, as a new improved type of a gate turn-off thyristor (hereinafter, referred to as GTO) used as a switching element in an inverter application product, etc., a gate commutated type thyristor (Gate Commutated Tu) has been recently developed.
An rn-Off thyristor (hereinafter referred to as GCT) has been known.

In the main current commutation at the time of the GCT interruption, a gate current (Ig) having a large gate reverse current increase rate (diGQ / dt) needs to be supplied, and an example of the interruption gate circuit is shown in FIG. It is shown below. The gate circuit (6) includes a switch (for example, a semiconductor switch) (S) and a ceramic capacitor (Ca) in a path (conductive path) (7) connecting the cathode (K) and the gate (G) of the GCT (4). ) Is inserted in series, and an electrolytic capacitor (Cb) and a DC power supply (Vo) are connected to a ceramic capacitor (Ca).
Are connected in parallel.

In the above configuration, a DC power supply (Vo) is
The capacitors (Ca) and (Cb) are charged in advance, and when the switch (S) is turned on at the time of shutoff, the capacitors (C) and (Cb) are turned on.
a) A current is drawn from the gate (G) to the cathode (K) at a high speed via (Cb), and the main current (Ia) is all diverted to the gate side to cut off between the anode and the cathode.

Here, according to the GTO driving gate circuit (6), all the main current (Ia) is commutated to the gate side at the time of cutoff, so that the restriction of the gate circuit (6) is increased. For example, the most important matter is the reverse current rise rate (diGQ / dt)
(For example, the conventional equivalent GTO is 60
~ 80A / μs, GCT 3000-6000A
/ Μs), and a large voltage drop {L (di / dt)} occurs due to the inherent circuit inductance (L).

In order to compensate for the voltage drop {L (di / dt)}, the power supply voltage (Vo) may be increased.
Since the gate / cathode reverse breakdown voltage of T (4) is equivalent to that of GTO, the power supply voltage (Vo) cannot be increased more than before. Therefore, the circuit inductance (L) is reduced to reduce the voltage drop {L (di / dt)}.

Therefore, the circuit inductance (L) in the gate circuit (6) is reduced, and the total main current (Ia) is reduced.
In order to form a circuit through which the current flows, the lead portion is formed of a laminate bar wiring, thereby reducing the inductance between the gate and the cathode in the gate circuit.

An electrolytic capacitor having a large capacity (Cb)
A ceramic capacitor (Ca) that has a small internal inductance and rises instantaneously when the gate reverse current rises is used in common, and an FET or SI transistor with a short turn-on time is used as the switch (S).

[0009]

SUMMARY OF THE INVENTION The above-mentioned GTO (GC
T) The drive gate circuit (6) is a ceramic capacitor (Ca) for reducing the circuit inductance (L).
However, the external dimensions of the element itself are increased, which leads to an increase in the inductance of the current loop.
Therefore, there is a problem that the circuit inductance (L) is not sufficiently reduced simply by arranging the ceramic capacitors (Ca) as they are.

An object of the present invention is to provide a GTO driving gate circuit with sufficiently reduced circuit inductance.

[0011]

SUMMARY OF THE INVENTION The present invention has a path connecting a gate and a cathode of a GTO, an open / close switch and a charging capacitor inserted in series in each path,
In a GTO cutoff gate circuit for turning on the switch at the time of cutoff and drawing a current from the gate to the cathode via a capacitor to cut off between the anode and the cathode, a plurality of paths are connected in parallel between the gate and the cathode for the switch. The circuit inductance is reduced by arranging each switch, capacitor, and path so that the magnetic field generated by the loop current flowing in each path cancels each other between adjacent paths, while interposing a capacitor and a capacitor. And

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a GTO driving gate circuit according to the present invention will be described below with reference to FIGS. First, in FIG. 1, (11a)... (12a)... Are a plurality of paths (for example, about 30) connected in parallel between the same gate (G) and cathode (K) of the GTO, and are not shown. As before, each path (11a)... (1
2a) each having a switch (S) and a ceramic capacitor (Ca) inserted in series.

The feature of the present invention is that the path (11a).
a) ... and ceramic capacitor (Ca) for each pass
, Switches (S) are arranged at predetermined positions, so that a loop current (Ip) flowing from the gate (G) to the cathode (K) in each path (11a) (12a).
a) The magnetic fields generated by (Iqa) cancel each other between adjacent paths, thereby reducing the circuit inductance (L) as much as possible.
If the current loop area of each path (11a)... (12a).
Can be further reduced.

That is, generally, the inductance of a circuit composed of a plurality of circuits is represented by each self inductance and mutual inductance. For simplicity, the total inductance (Lt) of the circuit as a configuration with two circuits
Is Lt = La + Lb-2M, where La: circuit (a)
, Lb: the self-inductance of the circuit (b), and M: the mutual inductance of the circuits (a), (b). Self inductance (La) (L
b) is reduced by minimizing the loop area of the circuit itself and the self-inductance (La)
The total inductance (Lt) represented by the difference between (Lb) and the mutual inductance (M) can be reduced by configuring the magnetic fluxes generated by the respective loop currents to cancel each other. Therefore, as described above, by arranging the switches (S), the ceramic capacitors (Ca) and the paths (11a) (12a) so that the magnetic fields generated between adjacent paths cancel each other, the gate circuit ( 6) The total inductance (L) in (2) can be reduced.

Then, the loop current (Ipa)... (Iq
a) The path (1) for canceling the magnetic fields generated from.
As a specific arrangement example of 1a) (12a), etc., for example, paths (11a) arranged vertically as shown in FIG.
, The paths (11a)... Are aligned in the horizontal direction and in parallel with each other. By changing the series arrangement of the switch (S) and the ceramic capacitor (Ca) alternately for each path, the direction of the loop current (Ipa) flowing in each path (11a) is changed between the adjacent paths. To reverse the direction.

Alternatively, in the case of the paths (12a) lying horizontally, the paths (12a) are arranged in parallel in layers in parallel with the paths (not shown) similarly lying horizontally. And a switch (S) ... and a ceramic capacitor (Ca)
Are alternately arranged for each path, and the direction of the loop current (Iqa) flowing through each path (12a) is reversed between the vertically adjacent paths.

According to the above configuration, each path (11a) ...
(11a) ... loop current (Ipa) ... (Iq
When a magnetic field is generated by a), the directions of the loop currents (Ipa)... (Iqa)... between the adjacent paths are opposite, so that the generated magnetic fields cancel each other between the adjacent paths. If the paths (11a)... (12a) are arranged vertically and horizontally at the same time, for example, a magnetic field component not canceled by the vertical path (11a) can be canceled by the horizontal path (12a). The components in various directions of the generated magnetic field can be canceled by any of the vertical and horizontal paths (11a)... (12a).

Next, specific examples of the present invention will be described with reference to FIGS.
Is shown with reference to FIG. First, FIGS. 3A, 3B, and 3C show a side view, a plan view, and a front view of the first configuration example of the present invention, in which (Dg) is a gate electrode plate, (Dk) is a cathode electrode plate, (Ba) and (Bb) are front and back printed circuit boards, and (S)
Is a semiconductor switch (FET), (Ca) is a ceramic capacitor, and (Cba) and (Cbb) are electrolytic capacitors. Gate and cathode electrode plates (Dg) (Dk)
Is an insulating sheet (T) as shown in FIGS.
, And are connected to the gate and cathode electrodes (G) and (K) of the GCT element, respectively. A wiring pattern is formed on the surface of the printed circuit boards (Ba) and (Bb), and they are joined together with the gate and cathode electrode plates (Dg) and (Dk) and the spacer (W) therebetween.

The semiconductor switch (S) and the ceramic capacitor (Ca) are printed circuit boards (Ba) and (Bb), respectively.
And two electrolytic capacitors (Cba) (Cb
b) are respectively mounted on the printed circuit boards (Ba) and (Bb). At this time, the semiconductor switch (S) and the ceramic capacitor (Ca) are alternately arranged on the printed circuit boards (Ba) and (Bb) as shown in FIG.
In FIG. 3B, (R) is a resistor, and gate and cathode electrode plates (Dg) and (Dk) are printed circuit boards (Ba).
Gate and cathode terminals (G) ... (K) ... (however,
The same symbols as those of the GCT element electrodes are used. ) Is connected and derived.

According to the first configuration example, in the case of a vertically flowing loop current (Ipa), for example, in FIG. 3A, a switch (A) is passed from the gate electrode plate (Dg) via the wiring pattern of the printed circuit board (Ba). S), goes around to the printed circuit board (Bb) side, and becomes a ceramic capacitor (Ca).
Through the cathode electrode plate (Dk). At this time, as shown in FIG. 3C, the switches (S) and the ceramic capacitors (Ca) are connected to the printed circuit board (Ba).
(Bb), the directions of the loop currents (Ipa) flowing through the switches (S) and the ceramic capacitors (Ca) are opposite to each other between the adjacent loops. The magnetic fields cancel each other out.

In the case of a loop current (Iqa) flowing laterally, for example, as shown in FIG.
qa) flows from the gate terminal (G) on the right end of the figure to the cathode terminal (K) on the left side via the switch (S) and the ceramic capacitor (Ca). Also, the loop current (Iqb)
Flows from the third gate terminal (G) from the right through the switch (S) and the ceramic capacitor (Ca) to the cathode terminal (K) on the right (the second from the right), in the opposite direction to the loop current (Iqa). Become. The direction of the loop current flowing from the gate terminal (G) to the cathode terminal (K) is alternately reversed in order toward the left in the figure, and the generated magnetic field is canceled between the upper and lower loop currents.

Next, FIGS. 4A and 4B show a side view and a front view of a second embodiment of the present invention. In the figure, (Dg) is a gate electrode plate, (Dk) is a cathode electrode plate, (Bc) is a printed circuit board, (S) is a semiconductor switch (FET), and (C)
a) is a ceramic capacitor. As shown in FIG. 4A, the gate and cathode electrode plates (Dg) and (Dk) are joined and integrated with an insulating sheet (T) interposed therebetween, and the gate and cathode electrodes (G) of the GCT element, respectively.
(K). A wiring pattern is formed on the surface of the printed board (Bc), and the gate and cathode electrode plates (Dg) and (Dk) are mounted. Semiconductor switch (S)
And the ceramic capacitor (Ca) are respectively mounted on the front and back surfaces of the printed circuit board (Bc). However, FIG.
The semiconductor switch (S) of (b) has two lead-outs and a back electrode, and the back electrode is directly and electrically connected to the gate electrode plate (Dg), and the current path is reduced accordingly.

According to the second configuration example, the vertical loop current (Ipa) flows from the gate electrode plate (Dg) to the cathode electrode plate (Dk) via the switch (S) and the ceramic capacitor (Ca). The current directions of the adjacent paths are opposite to each other. Note that the second configuration example has a smaller current path and man-hours than the first configuration example.

FIGS. 5A and 5B show a side view and a front view of a third embodiment of the present invention. In the figure, (Dg) is a gate electrode plate, (Dk) is a cathode electrode plate, (Bd) is a printed circuit board, (S) is a semiconductor switch (FET), and (C)
a) is a ceramic capacitor. As shown in FIG. 5A, the gate and cathode electrode plates (Dg) and (Dk) are joined and integrated with an insulating sheet (T) interposed therebetween, and the gate and cathode electrodes (G) of the GCT element, respectively.
(K). A wiring pattern is formed on the surface of the printed board (Bd), and gate and cathode electrode plates (Dg) and (Dk) are mounted. Semiconductor switch (S)
And the ceramic capacitor (Ca) are respectively mounted on the front and back surfaces of the printed circuit board (Bd).

According to the third configuration example, the vertical loop current (Ipa) flows from the gate electrode plate (Dg) to the cathode electrode plate (Dk) via the switch (S) and the ceramic capacitor (Ca). The current directions of the adjacent paths are opposite to each other. Also, similarly to the second configuration example, the current path and the number of steps are small.

FIGS. 6A and 6B are a side view, a side view and a front view of a fourth embodiment of the present invention. In the figure, (Dg) is a gate electrode plate, (Dk) is a cathode electrode plate, (Be) and (Bf) are printed circuit boards, (S) is a semiconductor switch (FET), (Ca) is a ceramic capacitor, and (Cb) is electrolytic. It is a capacitor. As shown in FIG. 6A, the gate and cathode electrode plates (Dg) and (Dk) are joined and integrated with an insulating sheet (T) interposed therebetween.
GCT element gate and cathode electrodes (G)
(K).

The wiring pattern is formed on the surface of the printed circuit board (Be), and the gate and cathode electrode plates (Dg)
(Dk) is implemented. The semiconductor switch (S) and the ceramic capacitor (Ca) are printed circuit boards (B
e) mounted on the front and back surfaces, and the electrolytic capacitor (Cb) is provided laterally on the printed circuit board (Bf). FIG.
As shown in (b), a negative potential bar (H) is arranged.

According to the fourth configuration example, the vertical loop current (Ipa) flows from the gate electrode plate (Dg) to the cathode electrode plate (Dk) via the ceramic capacitor (Ca) and the switch (S). The current directions of the adjacent paths are opposite to each other. Also, as in the second configuration example,
Current paths and man-hours are reduced.

[0029]

According to the present invention, there are provided paths for connecting the gate and the cathode of the GTO, and an open / close switch and a charging capacitor interposed in each path in series. In a GTO cutoff gate circuit that draws current from the gate to the cathode via the capacitor to cut off between the anode and the cathode, a plurality of paths are connected in parallel between the gate and the cathode, and the switch and the capacitor are interposed. Since the switches, capacitors, and paths are arranged so that the magnetic field generated by the loop current flowing in each path cancels each other between the adjacent paths, the circuit inductance is sufficiently reduced, and the voltage drop is significantly reduced.

[Brief description of the drawings]

FIG. 1 is a schematic diagram of a current loop of a GTO driving gate circuit according to the present invention.

FIG. 2 is a circuit diagram of a GTO driving gate circuit.

3A, 3B, and 3C are a side view, a plan view, and a front view of a first configuration example of the GTO driving gate circuit according to the present invention.
(D) is a side view of the gate and cathode electrode plates and the insulating sheet according to the present invention.

FIGS. 4A and 4B are a side view and a front view of a second configuration example of the GTO driving gate circuit according to the present invention.

FIGS. 5A and 5B are a side view and a front view of a third configuration example of the GTO driving gate circuit according to the present invention.

6A and 6B are a side view, a negative potential bar side view, and a front view of a fourth configuration example of the GTO driving gate circuit according to the present invention.

[Explanation of symbols]

 11a to 11c pass 12a to 12c pass Ipa to Ipc loop current Iqa to Iqc loop current G gate K cathode

Claims (1)

[Claims] A gate turn-off thyristor has a path connecting between a gate and a cathode, and an opening / closing switch and a charging capacitor inserted in series in each path. A gate turn-off thyristor cutoff gate circuit that draws a current from the gate to the cathode via the gate to cut off between the anode and the cathode, wherein a plurality of paths are connected in parallel between the gate and the cathode, and the switch and the capacitor are interposed. A gate for driving a gate turn-off thyristor, wherein a circuit inductance is reduced by arranging switches, capacitors and paths so that a magnetic field generated by a loop current flowing in each path cancels each other between adjacent paths. circuit.