JPH11150295A - Semiconductor light-emitting element, production of the semiconductor light-emitting element, and indicator thereof - Google Patents
Semiconductor light-emitting element, production of the semiconductor light-emitting element, and indicator thereofInfo
- Publication number
- JPH11150295A JPH11150295A JP31557997A JP31557997A JPH11150295A JP H11150295 A JPH11150295 A JP H11150295A JP 31557997 A JP31557997 A JP 31557997A JP 31557997 A JP31557997 A JP 31557997A JP H11150295 A JPH11150295 A JP H11150295A
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- layer
- light emitting
- type semiconductor
- light
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 334
- 238000004519 manufacturing process Methods 0.000 title claims description 28
- 239000004020 conductor Substances 0.000 claims description 15
- 239000000758 substrate Substances 0.000 claims description 15
- 239000011159 matrix material Substances 0.000 claims description 5
- 238000010030 laminating Methods 0.000 claims description 4
- 239000012212 insulator Substances 0.000 claims description 2
- 229920005989 resin Polymers 0.000 abstract description 13
- 239000011347 resin Substances 0.000 abstract description 13
- 239000010409 thin film Substances 0.000 abstract description 8
- 239000003822 epoxy resin Substances 0.000 abstract description 4
- 229920000647 polyepoxide Polymers 0.000 abstract description 4
- 230000000903 blocking effect Effects 0.000 abstract description 3
- 239000010410 layer Substances 0.000 description 182
- 238000000034 method Methods 0.000 description 22
- 239000010408 film Substances 0.000 description 11
- 229910052594 sapphire Inorganic materials 0.000 description 11
- 239000010980 sapphire Substances 0.000 description 11
- 238000000605 extraction Methods 0.000 description 9
- 238000007789 sealing Methods 0.000 description 9
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 8
- 239000012790 adhesive layer Substances 0.000 description 7
- 239000000565 sealant Substances 0.000 description 7
- 239000010931 gold Substances 0.000 description 6
- 229910052737 gold Inorganic materials 0.000 description 6
- 229910052751 metal Inorganic materials 0.000 description 5
- 239000002184 metal Substances 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 230000001681 protective effect Effects 0.000 description 4
- 239000000853 adhesive Substances 0.000 description 3
- 230000001070 adhesive effect Effects 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000017525 heat dissipation Effects 0.000 description 2
- 239000002245 particle Substances 0.000 description 2
- 230000005855 radiation Effects 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 229910000679 solder Inorganic materials 0.000 description 2
- 230000008646 thermal stress Effects 0.000 description 2
- 238000002834 transmittance Methods 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 239000011247 coating layer Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 239000000945 filler Substances 0.000 description 1
- CPLXHLVBOLITMK-UHFFFAOYSA-N magnesium oxide Inorganic materials [Mg]=O CPLXHLVBOLITMK-UHFFFAOYSA-N 0.000 description 1
- 239000000395 magnesium oxide Substances 0.000 description 1
- AXZKOIWUVFPNLO-UHFFFAOYSA-N magnesium;oxygen(2-) Chemical compound [O-2].[Mg+2] AXZKOIWUVFPNLO-UHFFFAOYSA-N 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 238000010023 transfer printing Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
- H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
- H01L33/58—Optical field-shaping elements
- H01L33/60—Reflective elements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48257—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a die pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/49105—Connecting at different heights
- H01L2224/49107—Connecting at different heights on the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1204—Optical Diode
- H01L2924/12041—LED
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Led Device Packages (AREA)
- Semiconductor Lasers (AREA)
- Led Devices (AREA)
Abstract
Description
【0001】[0001]
【発明の属する技術分野】本発明は半導体発光素子、半
導体発光素子の製造方法および前記半導体発光素子を用
いた表示装置に関する。The present invention relates to a semiconductor light emitting device, a method for manufacturing a semiconductor light emitting device, and a display device using the semiconductor light emitting device.
【0002】[0002]
【従来の技術】従来、例えば高輝度を必要とする屋外用
の表示装置の用いる発光ダイオードのうち、青色および
緑色の発光ダイオードは例えば図9に示す構造を有す
る。例えばGaNのPN接合による発光層を有する半導
体チップ23のN電極とN電極リード21が例えば金か
らなる細いワイヤ25により接続されている。一方、半
導体チップ23のP電極とP電極リード22もまた金の
細いワイヤ26により接続されている。上記の半導体チ
ップ23とN電極リード21およびP電極リード22と
の接続部は、酸化アルミニウムあるいは酸化マグネシウ
ムなどのフィラーを含有する可視光透過性のエポキシ樹
脂などからなり、レンズの役割を有する封止樹脂24に
より封止されている。また、図面と平行な方向と図面と
垂直な方向とで封止樹脂24によるレンズの度は異なっ
て設定されており、例えば図面と平行な方向のほうが度
が弱くなっている。2. Description of the Related Art Conventionally, among the light-emitting diodes used in outdoor display devices requiring high luminance, for example, blue and green light-emitting diodes have a structure shown in FIG. 9, for example. For example, an N electrode of a semiconductor chip 23 having a light emitting layer formed by a PN junction of GaN and an N electrode lead 21 are connected by a thin wire 25 made of, for example, gold. On the other hand, the P electrode of the semiconductor chip 23 and the P electrode lead 22 are also connected by a thin gold wire 26. The connection portion between the semiconductor chip 23 and the N electrode lead 21 and the P electrode lead 22 is made of a visible light transmitting epoxy resin containing a filler such as aluminum oxide or magnesium oxide, and has a role of a lens. It is sealed with a resin 24. The lens power of the sealing resin 24 is set differently in a direction parallel to the drawing and in a direction perpendicular to the drawing. For example, the power in the direction parallel to the drawing is weaker.
【0003】上記の発光ダイオードの要部を拡大した平
面図を図10(a)に、図10(a)中のB−B’にお
ける断面図を図10(b)に示す。N電極リード21に
はリフレクタ面27、27’が形成されており、リフレ
クタ面27、27’で形成される凹部内に半導体チップ
23が樹脂などの接着層36により接着されている。半
導体チップ23は例えばサファイア基板28とその上層
に形成されたGaNのPN接合体Jにより構成されてお
り、その上面に形成されたN電極30はワイヤ25によ
りN電極リード21へ、P電極34はワイヤ26により
P電極リード22へそれぞれ接続される。半導体チップ
23のうち、N電極30を除く領域が発光領域Eとなっ
ている。FIG. 10A is an enlarged plan view of a main part of the light emitting diode, and FIG. 10B is a sectional view taken along line BB ′ in FIG. 10A. Reflector surfaces 27 and 27 'are formed on the N-electrode lead 21, and the semiconductor chip 23 is adhered to a concave portion formed by the reflector surfaces 27 and 27' by an adhesive layer 36 such as a resin. The semiconductor chip 23 includes, for example, a sapphire substrate 28 and a GaN PN junction J formed on the sapphire substrate 28, the N electrode 30 formed on the upper surface thereof is connected to the N electrode lead 21 by a wire 25, and the P electrode 34 is The wires 26 are connected to the P electrode leads 22 respectively. The area of the semiconductor chip 23 other than the N electrode 30 is the light emitting area E.
【0004】上記の半導体チップ23をさらに拡大した
断面図を図11に示す。例えばサファイア基板28の上
層にN型GaN層29が形成されており、その上層に例
えばアルミニウムからなるN電極30が形成されてお
り、さらにN電極リードに接続するワイヤ25が接続し
ている。一方、N電極30を除く領域では、N型GaN
層29の膜厚が厚く形成されており、その上層に活性層
31を介してP型GaN層32が形成され、PN接合を
形成している。その上層には例えば半透明の薄膜である
金からなる第1P電極33と、第1P電極33よりも厚
く形成された同じく金からなる第2P電極34が形成さ
れており、P電極リードに接続するワイヤ26が接続し
ている。また、チップ表面には例えば酸化シリコンある
いは酸化アルミニウムなどからなる保護絶縁膜35が形
成されている。FIG. 11 is a sectional view showing the semiconductor chip 23 further enlarged. For example, an N-type GaN layer 29 is formed on an upper layer of a sapphire substrate 28, an N electrode 30 made of, for example, aluminum is formed on the upper layer, and a wire 25 connected to an N electrode lead is further connected. On the other hand, in a region excluding the N electrode 30, N-type GaN
The layer 29 is formed to have a large thickness, and a P-type GaN layer 32 is formed thereover via an active layer 31 to form a PN junction. On the upper layer, a first P electrode 33 made of, for example, a translucent thin film of gold and a second P electrode 34 made of the same gold and formed thicker than the first P electrode 33 are formed, and are connected to P electrode leads. Wire 26 is connected. A protective insulating film 35 made of, for example, silicon oxide or aluminum oxide is formed on the chip surface.
【0005】上記の発光ダイオードは封止樹脂により封
止されているが、例えば室内用の表示装置に用いる場合
には画素密度を上げるためにリフレクタやレンズを用い
ずにプリント基板上に例えばGaNのPN接合による発
光層を有する半導体チップを直接導電接着して形成する
こともある。The above light emitting diode is sealed with a sealing resin. For example, when the light emitting diode is used for an indoor display device, for example, GaN of GaN is formed on a printed circuit board without using a reflector or a lens in order to increase the pixel density. In some cases, a semiconductor chip having a light emitting layer based on a PN junction is formed by direct conductive bonding.
【0006】[0006]
【発明が解決しようとする課題】しかしながら、上記の
従来の発光ダイオードは、発光層の上層に電極が形成さ
れているために、光の透過率を下げてしまう。特に全発
光面積の約1/3を占めるワイヤボンディング部は全く
光を直接取り出すことができない。このため、光透過率
で35〜62%分しか光を直接取り出すことができな
い。一部の光はリフレクタにより反射されて全面に出て
くるが、それでも発生した光を有効に取り出していると
は言えない。However, in the above-mentioned conventional light emitting diode, since the electrode is formed on the light emitting layer, the light transmittance is reduced. In particular, the wire bonding portion occupying about 1/3 of the total light emitting area cannot directly take out light at all. For this reason, only 35 to 62% of the light transmittance can directly extract light. Although some light is reflected by the reflector and comes out on the entire surface, it cannot be said that the generated light is still effectively extracted.
【0007】本発明は上記の問題点を鑑みてなされたも
のであり、従って、本発明の目的は、発光層より発生し
た光を有効に取り出すことができる半導体発光素子、半
導体発光素子の製造方法および前記半導体発光素子を用
いた表示装置を提供することである。SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and it is therefore an object of the present invention to provide a semiconductor light emitting device capable of effectively extracting light generated from a light emitting layer, and a method of manufacturing a semiconductor light emitting device. And a display device using the semiconductor light emitting element.
【0008】[0008]
【課題を解決するための手段】上記の目的を達成するた
め、本発明の半導体発光素子は、P型半導体層とN型半
導体層とを積層させて形成され、前記P型半導体層と前
記N型半導体層の間に所定の電圧を印加することにより
光を発する発光層と、前記P型半導体層と前記N型半導
体層にそれぞれ接続するP電極およびN電極を有する半
導体チップと、表面が前記発光層の発する光の反射面と
なっている前記半導体チップ用凹部を有し、互いに絶縁
するように分割されている1対の電極リードと、前記1
対の電極リードと前記P電極あるいは前記N電極を接続
するように前記1対の電極リードと前記P電極あるいは
前記N電極の間に配置されている導電層とを有する。In order to achieve the above object, a semiconductor light emitting device according to the present invention is formed by laminating a P-type semiconductor layer and an N-type semiconductor layer, wherein the P-type semiconductor layer and the N-type semiconductor layer are stacked. A light emitting layer that emits light by applying a predetermined voltage between the type semiconductor layers; a semiconductor chip having a P electrode and an N electrode connected to the P type semiconductor layer and the N type semiconductor layer, respectively; A pair of electrode leads having the concave portion for a semiconductor chip serving as a reflecting surface of light emitted from the light emitting layer and being divided so as to be insulated from each other;
A conductive layer disposed between the pair of electrode leads and the P electrode or the N electrode so as to connect the pair of electrode leads and the P electrode or the N electrode;
【0009】上記の半導体発光素子においては、P型半
導体層とN型半導体層とを積層させた発光層と、P型半
導体層とN型半導体層にそれぞれ接続するP電極および
N電極を有する半導体チップが1対の電極リードの凹部
に装着されており、1対の電極リードとP電極あるいは
N電極の間に配置された導電層により1対の電極リード
とP電極あるいはN電極が接続されている。発光層はP
型半導体層とN型半導体層の間に所定の電圧を印加する
ことにより光を発し、この光の一部は電極リードの凹部
表面で反射されるようになっている。In the above semiconductor light emitting device, a light emitting layer in which a P-type semiconductor layer and an N-type semiconductor layer are laminated, and a semiconductor having a P electrode and an N electrode connected to the P-type semiconductor layer and the N-type semiconductor layer, respectively. The chip is mounted in the recess of the pair of electrode leads, and the pair of electrode leads and the P or N electrode are connected by a conductive layer disposed between the pair of electrode leads and the P or N electrode. I have. The light emitting layer is P
Light is emitted by applying a predetermined voltage between the type semiconductor layer and the N-type semiconductor layer, and a part of the light is reflected on the concave surface of the electrode lead.
【0010】上記の半導体発光素子によれば、半導体チ
ップと電極リードとがその間に配置された導電層により
接続されており、従来の発光ダイオードのような発光層
からの光を遮るワイヤボンディングや半透明の薄膜電極
がないために光の取り出し効率が向上する。According to the above-described semiconductor light emitting device, the semiconductor chip and the electrode lead are connected by the conductive layer disposed between them, and the wire bonding or the half bonding for blocking light from the light emitting layer such as a conventional light emitting diode is performed. Since there is no transparent thin film electrode, light extraction efficiency is improved.
【0011】また、P電極およびN電極の膜厚は十分に
厚くすることができるので、電極部分での光の反射率が
高まるので光の取り出し効率が向上し、電極リードの凹
部底面における光の反射率を高める必要性が少なくな
り、凹部底面を鏡面としないでよくなるので電極リード
の製造コストを抑えることができる。Further, since the thickness of the P electrode and the N electrode can be made sufficiently large, the light reflectance at the electrode portion is increased, so that the light extraction efficiency is improved, and the light at the bottom of the concave portion of the electrode lead is reduced. The need to increase the reflectance is reduced, and the concave bottom surface is not required to be a mirror surface, so that the manufacturing cost of the electrode lead can be suppressed.
【0012】また、発光層は通電により発熱するが、従
来の半導体発光素子においては、この熱は主としてサフ
ァイア基板および接着層を介して、あるいは細い金のワ
イヤを介して電極リードへ伝導され、放熱される。この
ため、放熱は不十分であったが、本発明の半導体発光素
子においては、導電層として金属などの熱伝導性の材料
を用いることにより、発光層の通電による発熱を直接電
極リードへ伝導し、放熱することが可能となり、放熱効
率を向上させることができる。また、P電極およびN電
極の膜厚は十分に厚くすることができるので、電極部分
の電気抵抗が下げることが可能となり、電極部分での発
熱量を少なくすることができる。さらに半導体チップと
電極リードの凹部底面との熱膨張率の違いによる熱スト
レスを吸収するアンダーフィル封止剤に、通常の半導体
装置で実績のある不透明で熱抵抗の小さい材料を用いる
ことが可能となる。The light-emitting layer generates heat when energized. In a conventional semiconductor light-emitting device, this heat is conducted to the electrode lead mainly through the sapphire substrate and the adhesive layer or through a thin gold wire, and the heat is radiated. Is done. For this reason, heat dissipation was insufficient, but in the semiconductor light emitting device of the present invention, by using a heat conductive material such as a metal as the conductive layer, heat generated by energization of the light emitting layer was directly conducted to the electrode leads. In this case, heat can be dissipated, and the heat dissipation efficiency can be improved. Further, since the thickness of the P electrode and the N electrode can be made sufficiently large, the electric resistance of the electrode portion can be reduced, and the amount of heat generated at the electrode portion can be reduced. Furthermore, it is possible to use an opaque, low thermal resistance material that has been proven in ordinary semiconductor devices as an underfill sealant that absorbs thermal stress due to the difference in the thermal expansion coefficient between the semiconductor chip and the bottom of the concave part of the electrode lead. Become.
【0013】上記の半導体発光素子は、好適には、前記
発光層が光透過性の絶縁基板に形成されている。これに
より、発光層の発する光が絶縁基板を透過してくること
となるので、発光層の発する光の取り出し効率を向上さ
せることができる。In the above-mentioned semiconductor light-emitting device, the light-emitting layer is preferably formed on a light-transmitting insulating substrate. Thus, light emitted from the light-emitting layer passes through the insulating substrate, so that the efficiency of extracting light emitted from the light-emitting layer can be improved.
【0014】上記の半導体発光素子は、好適には、前記
1対の電極リードがほぼ面対称形状である。また、好適
には、前記半導体チップの対角線位置で前記1対の電極
リードが分割されている。電極リードをこのような構造
とすることで凹部形成が容易となり、部品のコストを下
げることが可能となり、さらに半導体チップと電極リー
ドの位置合わせが容易になるので光軸の取り方が容易と
なる。In the above-mentioned semiconductor light emitting device, preferably, the pair of electrode leads have a substantially plane-symmetric shape. Preferably, the pair of electrode leads is divided at diagonal positions of the semiconductor chip. By forming the electrode lead in such a structure, the concave portion can be easily formed, the cost of parts can be reduced, and the alignment of the semiconductor chip and the electrode lead becomes easy, so that the optical axis can be easily taken. .
【0015】上記の半導体発光素子は、好適には、前記
1対の電極リードの前記凹部の底面形状が前記半導体チ
ップの形状と略相似形である。また、好適には、前記半
導体チップが略方形形状であり、前記一方の電極リード
の前記凹部の底面形状が三角形形状であり、前記三角形
の頂角の角度が、前記半導体チップの頂角のなす角度と
同じである。電極リードの凹部の底面形状を半導体チッ
プの形状に合わせることにより、半導体チップと電極リ
ードの位置合わせが容易になる。In the semiconductor light emitting device described above, preferably, the bottom surface of the concave portion of the pair of electrode leads is substantially similar to the shape of the semiconductor chip. Preferably, the semiconductor chip has a substantially square shape, the bottom shape of the concave portion of the one electrode lead has a triangular shape, and the angle of the apex angle of the triangle forms the apex angle of the semiconductor chip. Same as angle. By adjusting the bottom shape of the concave portion of the electrode lead to the shape of the semiconductor chip, the alignment of the semiconductor chip and the electrode lead becomes easy.
【0016】上記の半導体発光素子は、好適には、前記
電極リードの前記凹部の深さと前記半導体チップの厚さ
がほぼ同じである。電極リードの凹部側壁の傾斜面での
反射により半導体チップの側面からの光を有効に取り出
すことができ、また、凹部側壁が高すぎて半導体チップ
を保持する治具が側壁にぶつかるということがなく、位
置合わせを正確に行うことができる。In the above semiconductor light emitting device, preferably, the depth of the concave portion of the electrode lead and the thickness of the semiconductor chip are substantially the same. Light from the side surface of the semiconductor chip can be effectively extracted by reflection on the inclined surface of the side wall of the concave portion of the electrode lead, and the jig holding the semiconductor chip does not hit the side wall because the concave side wall is too high. , Positioning can be performed accurately.
【0017】上記の半導体発光素子は、好適には、前記
電極リードの前記凹部表面が実質的に前記発光層の発す
る光を反射する鏡面に形成されている。また、好適に
は、前記電極リードの凹部表面の側壁面が、開口側ほど
広がっているテーパ形状である。電極リードの凹部表面
を鏡面とすることで、実質的に発光層の発する光のほと
んどを反射することになり、また、側壁面を上方ほど広
がっているテーパ形状とすることで発光層の発する光を
有効に一方向に反射させることができ、半導体チップか
らの光の取り出し効率を向上させることができる。In the above-mentioned semiconductor light emitting device, preferably, the surface of the concave portion of the electrode lead is formed substantially as a mirror surface for reflecting light emitted from the light emitting layer. Preferably, the side wall surface of the concave portion surface of the electrode lead has a tapered shape that becomes wider toward the opening side. By making the concave surface of the electrode lead a mirror surface, substantially all of the light emitted from the light emitting layer is reflected. Also, the light emitted from the light emitting layer is formed by making the side wall surface tapered upward. Can be effectively reflected in one direction, and the light extraction efficiency from the semiconductor chip can be improved.
【0018】上記の半導体発光素子は、好適には、前記
電極リードの前記凹部の底面に前記半導体チップの位置
決め用孔が開孔されており、前記孔が前記P電極あるい
は前記N電極に接続する導電体で埋め込まれている。こ
れにより、半導体チップと電極リードの位置合わせが容
易になる。In the above semiconductor light emitting device, preferably, a positioning hole for the semiconductor chip is formed in the bottom surface of the concave portion of the electrode lead, and the hole is connected to the P electrode or the N electrode. It is embedded with a conductor. This facilitates the alignment between the semiconductor chip and the electrode leads.
【0019】上記の半導体発光素子は、好適には、導電
体により前記電極リードと接続する領域を除いて前記P
電極と前記N電極が導電体に対するぬれ性が悪い絶縁体
で被覆されている。これにより、P電極とN電極を保護
することが可能となり、エレクトロマイグレーションな
どの効果を防ぐことができ、さらにハンダなどの溶融金
属を用いて半導体チップと電極リードを接続するときに
自己整合的に位置決めを行うことが可能となる。Preferably, in the semiconductor light emitting device, the P light is removed except for a region connected to the electrode lead by a conductor.
The electrode and the N electrode are covered with an insulator having poor wettability to the conductor. As a result, the P electrode and the N electrode can be protected, and effects such as electromigration can be prevented. Further, when connecting the semiconductor chip and the electrode leads using a molten metal such as solder, self-alignment is achieved. Positioning can be performed.
【0020】上記の半導体発光素子は、好適には、前記
凹部底面と前記半導体チップのP型半導体層とN型半導
体層の接合面とを略平行に位置決めするための少なくと
も三個の突起が前記1対の電極リードの凹部底面に形成
されている。製造上のばらつきにより、半導体チップと
凹部表面(リフレクタ)の軸がずれたり、半導体チップ
と封止樹脂のレンズとの軸がずれたりするために最大輝
度となる方向のばらつきを発生させ、最大輝度となる方
向にばらつきのある発光ダイオードを用いて表示装置を
組み立てると、画面の一様性を損なうこととなるが、位
置決めするため突起を凹部底面に形成することで、半導
体チップと凹部表面(リフレクタ)、あるいは封止樹脂
のレンズとの軸合わせ(軸角度合わせ)が容易となり、
最大輝度となる方向のばらつきを抑えることができる。Preferably, in the semiconductor light emitting device, at least three protrusions for positioning the bottom surface of the concave portion and the bonding surface of the P-type semiconductor layer and the N-type semiconductor layer of the semiconductor chip substantially in parallel are provided. The pair of electrode leads are formed on the bottom surface of the concave portion. Due to manufacturing variations, the axis of the semiconductor chip deviates from the axis of the concave surface (reflector), or the axis of the semiconductor chip deviates from the axis of the sealing resin lens. Assembling a display device using light-emitting diodes that vary in the direction in which the display becomes uneven will impair the uniformity of the screen. However, by forming projections on the bottom surface of the recess for positioning, the semiconductor chip and the surface of the recess (reflector) are formed. ) Or alignment of the sealing resin with the lens (axis angle alignment) becomes easier,
Variations in the direction of the maximum luminance can be suppressed.
【0021】上記の半導体発光素子は、好適には、前記
導電層が、異方性導電物質である。異方性導電フィル
ム、あるいは異方性導電材料の塗布層を1対の電極リー
ドとP電極あるいはN電極を接続する導電層とすること
ができる。この場合、電極リードへの半導体チップの接
続、位置決め、固定を同時に行うことができるので、工
程を簡略化して容易に製造することができる。In the above semiconductor light emitting device, preferably, the conductive layer is an anisotropic conductive material. An anisotropic conductive film or a coating layer of an anisotropic conductive material can be a conductive layer that connects a pair of electrode leads to a P electrode or an N electrode. In this case, connection, positioning, and fixing of the semiconductor chip to the electrode lead can be performed at the same time, so that the process can be simplified and the semiconductor chip can be easily manufactured.
【0022】また、上記の目的を達成するため、本発明
の半導体発光素子の製造方法は、光透過性の絶縁性ウェ
ハ上に、N型半導体層とP型半導体層との接合体であ
り、前記P型半導体層と前記N型半導体層の間に所定の
電圧を印加することにより光を発する発光層を形成する
工程と、前記P型半導体層に接続するP電極を形成する
工程と、前記N型半導体層に接続するN電極を形成する
工程と、前記P電極および前記N電極を被覆して異方性
導電層を形成する工程と、前記ウェハをダイシングして
個々の半導体チップに分割する工程と、表面が前記発光
層の発する光の反射面となっている前記半導体チップ用
凹部を有し、互いに絶縁するように分割されている1対
の電極リードに、前記1対の電極リードと前記P電極あ
るいは前記N電極を前記異方性導電層を介して接続する
ように、前記半導体チップを固定する工程とを有する。According to another aspect of the present invention, there is provided a method for manufacturing a semiconductor light emitting device, comprising the steps of: bonding a N-type semiconductor layer and a P-type semiconductor layer on a light-transmitting insulating wafer; Forming a light-emitting layer that emits light by applying a predetermined voltage between the P-type semiconductor layer and the N-type semiconductor layer; and forming a P electrode connected to the P-type semiconductor layer; A step of forming an N electrode connected to the N-type semiconductor layer, a step of covering the P electrode and the N electrode to form an anisotropic conductive layer, and dicing the wafer into individual semiconductor chips And a pair of electrode leads having the concave portion for the semiconductor chip, the surface of which is a reflection surface of light emitted from the light emitting layer, and being divided so as to be insulated from each other. The P electrode or the N electrode To connect via a serial anisotropic conductive layer, and a step of fixing the semiconductor chip.
【0023】上記の本発明の半導体発光素子の製造方法
は、光透過性の絶縁性ウェハ上に、N型半導体層とP型
半導体層との接合体であり、P型半導体層とN型半導体
層の間に所定の電圧を印加することにより光を発する発
光層を形成し、P型半導体層に接続するP電極を形成
し、N型半導体層に接続するN電極を形成する。その
後、P電極およびN電極を被覆して異方性導電層を形成
し、ウェハをダイシングして個々の半導体チップに分割
する。次に、表面が発光層の発する光の反射面となって
いる半導体チップ用凹部を有し、互いに絶縁するように
分割されている1対の電極リードに、1対の電極リード
とP電極あるいはN電極を異方性導電層を介して接続す
るように、半導体チップを固定する。According to the method of manufacturing a semiconductor light emitting device of the present invention described above, an N-type semiconductor layer and a P-type semiconductor layer are bonded on a light-transmitting insulating wafer, and the P-type semiconductor layer and the N-type semiconductor A light-emitting layer that emits light by applying a predetermined voltage between the layers is formed, a P-electrode connected to the P-type semiconductor layer is formed, and an N-electrode connected to the N-type semiconductor layer is formed. Thereafter, the P electrode and the N electrode are covered to form an anisotropic conductive layer, and the wafer is diced to be divided into individual semiconductor chips. Next, a pair of electrode leads having a concave portion for a semiconductor chip whose surface is a reflection surface of light emitted from the light emitting layer and divided so as to be insulated from each other are provided on a pair of electrode leads and a P electrode or The semiconductor chip is fixed so that the N electrodes are connected via the anisotropic conductive layer.
【0024】上記の本発明の半導体発光素子の製造方法
によれば、半導体チップと電極リードとを異方性導電層
により接続するので、従来のような発光層からの光を遮
るワイヤや半透明の薄膜電極がなく、さらにP電極およ
びN電極の膜厚は十分に厚くすることができるので、電
極部分での光の反射率が高まり、光の取り出し効率を向
上させた半導体発光素子を製造することができる。電極
リードの凹部底面における光の反射率を高める必要性が
少なくなるので、凹部底面を鏡面としないでよくなるの
で電極リードの製造コストを抑えることができる。ま
た、ウェハのダイシング工程の前に異方性導電層を形成
するので製造が容易であり、さらに電極リードへの半導
体チップの接続、位置決め、固定を同時に行うことがで
きるので、工程を簡略化して容易に製造することができ
る。According to the method for manufacturing a semiconductor light emitting device of the present invention, the semiconductor chip and the electrode leads are connected by the anisotropic conductive layer. Since there is no thin film electrode and the thickness of the P electrode and the N electrode can be made sufficiently large, the light reflectance at the electrode portion is increased, and a semiconductor light emitting device with improved light extraction efficiency is manufactured. be able to. Since the necessity of increasing the light reflectance on the bottom surface of the concave portion of the electrode lead is reduced, the concave bottom surface does not have to be a mirror surface, so that the manufacturing cost of the electrode lead can be reduced. Further, since the anisotropic conductive layer is formed before the wafer dicing step, manufacturing is easy, and connection, positioning and fixing of the semiconductor chip to the electrode lead can be performed at the same time. It can be easily manufactured.
【0025】また、上記の目的を達成するため、本発明
の半導体発光素子の製造方法は、光透過性の絶縁性ウェ
ハ上に、N型半導体層とP型半導体層との接合体であ
り、前記P型半導体層と前記N型半導体層の間に所定の
電圧を印加することにより光を発する発光層を形成する
工程と、前記P型半導体層に接続するP電極を形成する
工程と、前記N型半導体層に接続するN電極を形成する
工程と、前記ウェハに格子状のスリットを入れる工程
と、前記P電極および前記N電極を被覆して異方性導電
層を形成する工程と、前記ウェハのスリット部を拡げて
個々の半導体チップに分割する工程と、表面が前記発光
層の発する光の反射面となっている前記半導体チップ用
凹部を有し、互いに絶縁するように分割されている1対
の電極リードに、前記1対の電極リードと前記P電極あ
るいは前記N電極を前記異方性導電層を介して接続する
ように、前記半導体チップを固定する工程とを有する。In order to achieve the above object, a method for manufacturing a semiconductor light emitting device according to the present invention is a method for manufacturing a semiconductor light emitting device, comprising the steps of: bonding a N-type semiconductor layer and a P-type semiconductor layer on a light-transmitting insulating wafer; Forming a light-emitting layer that emits light by applying a predetermined voltage between the P-type semiconductor layer and the N-type semiconductor layer; and forming a P electrode connected to the P-type semiconductor layer; Forming an N-electrode connected to the N-type semiconductor layer, forming a grid-like slit in the wafer, forming the anisotropic conductive layer by covering the P-electrode and the N-electrode, A step of expanding the slit portion of the wafer to divide the semiconductor chip into individual semiconductor chips, and the semiconductor chip concave portion whose surface is a reflection surface of light emitted from the light emitting layer, and is divided so as to be insulated from each other. The above-mentioned pair of electrode leads The P electrode or the N electrode and the pair of electrode leads so as to be connected through the anisotropic conductive layer, and a step of fixing the semiconductor chip.
【0026】光透過性の絶縁性ウェハ上に、N型半導体
層とP型半導体層との接合体であり、P型半導体層とN
型半導体層の間に所定の電圧を印加することにより光を
発する発光層を形成し、P型半導体層に接続するP電極
を形成し、N型半導体層に接続するN電極を形成する。
その後、ウェハに格子状のスリットを入れ、P電極およ
びN電極を被覆して異方性導電層を形成した後、ウェハ
のスリット部を拡げて個々の半導体チップに分割する。
次に、表面が発光層の発する光の反射面となっている半
導体チップ用凹部を有し、互いに絶縁するように分割さ
れている1対の電極リードに、1対の電極リードとP電
極あるいはN電極を異方性導電層を介して接続するよう
に、半導体チップを固定する。A joined body of an N-type semiconductor layer and a P-type semiconductor layer on a light-transmitting insulating wafer, wherein the P-type semiconductor layer
A light emitting layer that emits light by applying a predetermined voltage between the type semiconductor layers is formed, a P electrode connected to the P type semiconductor layer is formed, and an N electrode connected to the N type semiconductor layer is formed.
Thereafter, a lattice-shaped slit is formed in the wafer to cover the P electrode and the N electrode to form an anisotropic conductive layer. Then, the slit portion of the wafer is expanded and divided into individual semiconductor chips.
Next, a pair of electrode leads having a concave portion for a semiconductor chip whose surface is a reflection surface of light emitted from the light emitting layer and divided so as to be insulated from each other are provided on a pair of electrode leads and a P electrode or The semiconductor chip is fixed so that the N electrodes are connected via the anisotropic conductive layer.
【0027】上記の本発明の半導体発光素子の製造方法
によれば、半導体チップと電極リードとを異方性導電層
により接続するので、従来のような発光層からの光を遮
るワイヤや半透明の薄膜電極がなく、さらにP電極およ
びN電極の膜厚は十分に厚くすることができるので、電
極部分での光の反射率が高まり、光の取り出し効率を向
上させた半導体発光素子を製造することができる。電極
リードの凹部底面における光の反射率を高める必要性が
少なくなるので、凹部底面を鏡面としないでよくなるの
で電極リードの製造コストを抑えることができる。ま
た、ウェハの個々の半導体チップへの分割の前に異方性
導電層を形成するので製造が容易であり、さらに電極リ
ードへの半導体チップの接続、位置決め、固定を同時に
行うことができるので、工程を簡略化して容易に製造す
ることができる。According to the method of manufacturing a semiconductor light emitting device of the present invention described above, the semiconductor chip and the electrode leads are connected by the anisotropic conductive layer. Since there is no thin film electrode and the thickness of the P electrode and the N electrode can be made sufficiently large, the light reflectance at the electrode portion is increased, and a semiconductor light emitting device with improved light extraction efficiency is manufactured. be able to. Since the necessity of increasing the light reflectance on the bottom surface of the concave portion of the electrode lead is reduced, the concave bottom surface does not have to be a mirror surface, so that the manufacturing cost of the electrode lead can be reduced. In addition, since the anisotropic conductive layer is formed before dividing the wafer into individual semiconductor chips, manufacturing is easy, and connection, positioning, and fixing of the semiconductor chips to the electrode leads can be performed at the same time. The process can be simplified and easily manufactured.
【0028】また、上記の目的を達成するため、本発明
の表示装置は、P型半導体層とN型半導体層とを積層さ
せて形成され、前記P型半導体層と前記N型半導体層の
間に所定の電圧を印加することにより光を発する発光層
と、前記P型半導体層と前記N型半導体層にそれぞれ接
続するP電極およびN電極を有する半導体チップと、表
面が前記発光層の発する光の反射面となっている前記半
導体チップ用凹部を有し、互いに絶縁するように分割さ
れている1対の電極リードと、前記1対の電極リードと
前記P電極あるいは前記N電極を接続するように前記1
対の電極リードと前記P電極あるいは前記N電極の間に
配置されている導電層とを有する半導体発光素子をマト
リクス状に複数個並べて形成されている。In order to achieve the above object, a display device of the present invention is formed by laminating a P-type semiconductor layer and an N-type semiconductor layer, and is provided between the P-type semiconductor layer and the N-type semiconductor layer. A light emitting layer that emits light by applying a predetermined voltage to the semiconductor chip, a semiconductor chip having a P electrode and an N electrode connected to the P-type semiconductor layer and the N-type semiconductor layer, respectively, and a light emitted from the light emitting layer on the surface. A pair of electrode leads having the concave portion for the semiconductor chip serving as a reflection surface and being divided so as to be insulated from each other; and connecting the pair of electrode leads to the P electrode or the N electrode. Above 1
A plurality of semiconductor light emitting devices each having a pair of electrode leads and a conductive layer disposed between the P electrode or the N electrode are arranged in a matrix.
【0029】上記の表示装置は、半導体発光素子をマト
リクス状に複数個並べて形成されていて、この半導体発
光素子は、P型半導体層とN型半導体層とを積層させた
発光層と、P型半導体層とN型半導体層にそれぞれ接続
するP電極およびN電極を有する半導体チップが1対の
電極リードの凹部に装着されており、1対の電極リード
とP電極あるいはN電極の間に配置された導電層により
1対の電極リードとP電極あるいはN電極が接続されて
おり、発光層はP型半導体層とN型半導体層の間に所定
の電圧を印加することにより光を発し、この光は電極リ
ードの凹部表面で反射されるようになっている。The above-described display device is formed by arranging a plurality of semiconductor light emitting elements in a matrix. The semiconductor light emitting element includes a light emitting layer in which a P-type semiconductor layer and an N-type semiconductor layer are stacked, and a P-type semiconductor layer. A semiconductor chip having a P electrode and an N electrode connected to the semiconductor layer and the N-type semiconductor layer, respectively, is mounted in a recess of the pair of electrode leads, and is disposed between the pair of electrode leads and the P electrode or the N electrode. The pair of electrode leads and the P electrode or the N electrode are connected by the conductive layer, and the light emitting layer emits light by applying a predetermined voltage between the P type semiconductor layer and the N type semiconductor layer. Are reflected on the concave surface of the electrode lead.
【0030】上記の表示装置によれば、表示装置を構成
する各半導体発光素子は、半導体チップと電極リードと
がその間に配置された導電層により接続されており、従
来のような発光層からの光を遮るワイヤボンディングや
半透明の薄膜電極がないために光の取り出し効率が向上
する。According to the above-described display device, each semiconductor light-emitting element constituting the display device is connected with the semiconductor chip and the electrode lead by the conductive layer disposed between the semiconductor chip and the electrode lead. Since there is no wire bonding for shielding light or a translucent thin film electrode, light extraction efficiency is improved.
【0031】また、導電層として金属などの熱伝導性の
材料を用いることにより、発光層の通電による発熱を直
接電極リードへ伝導し、放熱することが可能となり、放
熱効率を向上させることができる。Further, by using a heat conductive material such as a metal as the conductive layer, heat generated by energization of the light emitting layer can be directly conducted to the electrode lead and radiated, thereby improving heat radiation efficiency. .
【0032】上記の表示装置は、好適には、前記複数個
の半導体発光素子のP電極とN電極の位置関係が一方向
に揃えられている。また、好適には、前記複数個の半導
体発光素子の発光中心が上側に揃えられている。また、
好適には、前記1対の電極リードの分割面が略水平方向
になるように揃えられている。これにより、表示装置の
画面の上方方向よりも下方方向、垂直方向よりも水平方
向の視野角を拡げることができる。In the above display device, preferably, the positional relationship between the P electrode and the N electrode of the plurality of semiconductor light emitting elements is aligned in one direction. Preferably, the light emission centers of the plurality of semiconductor light emitting elements are aligned on the upper side. Also,
Preferably, the split surfaces of the pair of electrode leads are aligned so as to be substantially horizontal. This makes it possible to increase the viewing angle in the lower direction than the upper direction of the screen of the display device and in the horizontal direction than in the vertical direction.
【0033】[0033]
【発明の実施の形態】以下に、本発明の実施の形態につ
いて、図面を参照して説明する。Embodiments of the present invention will be described below with reference to the drawings.
【0034】第1実施形態 本実施形態にかかる半導体発光素子の断面図を図1に示
す。P電極リード1およびN電極リード2からなる1対
の電極リードに、半導体チップ用の凹部が設けられてお
り、例えばGaNのP型半導体層とN型半導体層のPN
接合による発光層を有する半導体チップ3が凹部内に装
着されており、P型半導体層とP電極リード1が接続さ
れて、一方、N型半導体層とN電極リード2が接続され
ている。上記の半導体チップ3とP電極リード1および
N電極リード2との接続部は、可視光透過性のエポキシ
樹脂などからなり、レンズの役割を有する封止樹脂4に
より封止されている。 First Embodiment FIG. 1 is a sectional view of a semiconductor light emitting device according to the first embodiment. A pair of electrode leads including a P electrode lead 1 and an N electrode lead 2 is provided with a recess for a semiconductor chip, for example, a GaN P-type semiconductor layer and an N-type semiconductor layer PN.
A semiconductor chip 3 having a light emitting layer formed by bonding is mounted in the recess, and the P-type semiconductor layer and the P-electrode lead 1 are connected, while the N-type semiconductor layer and the N-electrode lead 2 are connected. A connection portion between the semiconductor chip 3 and the P electrode lead 1 and the N electrode lead 2 is made of a visible light transmitting epoxy resin or the like, and is sealed by a sealing resin 4 having a role of a lens.
【0035】上記の半導体発光素子の要部を拡大した平
面図を図2(a)に、図2(a)中のA−A’における
断面図を図2(b)に示す。略面対称形状であり、対称
的に配置されたP電極リード1とN電極リード2からな
る1対の電極リードに、表面が半導体チップ3の発光層
の発する光の反射面となっている凹部が設けられてお
り、半導体チップ3が装着されている。凹部の底面5’
は略正方形形状の半導体チップ3と略相似形で半導体チ
ップ3よりも僅かに大きな形状であり、一方の電極リー
ドの底面形状は略二等辺直角三角形となっている。ま
た、電極リードの凹部の側壁面5は底面に対して約45
度に傾いた斜面で構成されており、開口側ほど広がって
いるテーパ形状となっている。電極リードの凹部の少な
くとも側壁面は、半導体チップ3の発光層の発する光を
ほとんど反射する鏡面となっていることが好ましい。個
々の電極リードの略二等辺直角三角形形状の底面の直角
の近傍には、半導体チップとの接続部に位置決め用の孔
H1、H2が開孔されており、また、底面の長辺近傍に
は位置決め用の突起15が1対の電極リードに対して少
なくとも3か所以上、図面上は個々の電極リードに対し
て2か所づつ(計4か所)形成されている。FIG. 2A is an enlarged plan view of a main part of the semiconductor light emitting device, and FIG. 2B is a cross-sectional view taken along line AA 'in FIG. 2A. A concave portion whose surface is a reflection surface of light emitted from the light emitting layer of the semiconductor chip 3 is formed on a pair of electrode leads, which are substantially symmetrical in shape and are symmetrically arranged and include a P electrode lead 1 and an N electrode lead 2. And the semiconductor chip 3 is mounted. The bottom of the recess 5 '
Is substantially similar to the semiconductor chip 3 having a substantially square shape, is slightly larger than the semiconductor chip 3, and the bottom shape of one electrode lead is a substantially isosceles right triangle. Also, the side wall surface 5 of the concave portion of the electrode lead is approximately 45
It is formed of a slope inclined at an angle, and has a tapered shape that becomes wider toward the opening side. It is preferable that at least the side wall surface of the concave portion of the electrode lead is a mirror surface that reflects most of the light emitted from the light emitting layer of the semiconductor chip 3. Positioning holes H1 and H2 are opened near the right angles of the bottom surfaces of the substantially isosceles right triangles of the individual electrode leads at the connection portion with the semiconductor chip, and near the long sides of the bottom surface. At least three or more positioning projections 15 are formed on a pair of electrode leads, and two projections are formed on each electrode lead (four in total).
【0036】上記の突起上15に、半導体チップ3が配
置されている。半導体チップ3は例えばサファイア基板
6とGaNのPN接合体Jにより構成されており、例え
ばPN接合体中のP型半導体層に接続するようにはんだ
などの金属、あるいは導電性接着剤などからなり熱伝導
性である半球形状の導電層12が形成され、P電極リー
ド1の凹部底面の孔H1に埋め込まれている。同じく、
N型半導体層にも熱伝導性である半球形状の導電層13
が形成され、N電極リード2の凹部底面の孔H2に埋め
込まれている。導電層12、13以外の領域は、アンダ
ーフィル封止剤14により封止され、アンダーフィル封
止剤14を接着剤として半導体チップ3が凹部底面に固
定される。半導体チップ3のうち、N電極に接続する導
電層13を除く領域が発光領域Eとなっている。凹部の
深さと半導体チップ3の厚さがほぼ同じであり、半導体
チップの表面と電極リードの発光面側の表面の高さがほ
ぼ同じになっている。The semiconductor chip 3 is arranged on the projection 15. The semiconductor chip 3 is composed of, for example, a sapphire substrate 6 and a PN junction J of GaN. For example, the semiconductor chip 3 is made of a metal such as solder or a conductive adhesive so as to be connected to the P-type semiconductor layer in the PN junction. A conductive hemispherical conductive layer 12 is formed and is buried in the hole H1 on the bottom surface of the concave portion of the P electrode lead 1. Similarly,
Hemispherical conductive layer 13 that is also thermally conductive to the N-type semiconductor layer
Is formed and is buried in the hole H2 on the bottom surface of the concave portion of the N electrode lead 2. Areas other than the conductive layers 12 and 13 are sealed with an underfill sealant 14, and the semiconductor chip 3 is fixed to the bottom of the recess using the underfill sealant 14 as an adhesive. In the semiconductor chip 3, a region other than the conductive layer 13 connected to the N electrode is a light emitting region E. The depth of the concave portion and the thickness of the semiconductor chip 3 are substantially the same, and the height of the surface of the semiconductor chip and the surface of the electrode lead on the light emitting surface side are substantially the same.
【0037】上記の半導体チップ3近傍をさらに拡大し
た断面図を図3に示す。例えば光透過性である透明なサ
ファイア基板6の下層にN型GaNからなるN型半導体
層7が形成されており、その下層に例えば金からなるN
電極10が形成されており、導電層13を介してN電極
リード2の底面表面の孔H2において接続している。一
方、N電極10を除く領域では、N型半導体層7とP型
GaNのP型半導体層8が積層されている。P型半導体
層8の下層には、P型半導体層8に接続する例えば金か
らなるP電極9が一様な膜厚で厚く形成されており、導
電層12を介してP電極リード1の底面表面の孔H1に
おいて接続している。一様な厚い膜厚のP電極は、発光
層の下面を完全反射面とすることができる。また、P電
極9およびN電極13を例えば酸化シリコンあるいは酸
化アルミニウムなどからなる保護絶縁膜11が被覆して
形成されていて、エレクトロマイグレーションなどの効
果を防ぐことができる。さらに、半導体チップと電極リ
ードの間隙はアンダーフィル封止剤14により封止され
ている。FIG. 3 is a sectional view showing the vicinity of the semiconductor chip 3 further enlarged. For example, an N-type semiconductor layer 7 made of N-type GaN is formed under a transparent sapphire substrate 6 which is light-transmitting, and an N-type semiconductor layer
An electrode 10 is formed and is connected via a conductive layer 13 at a hole H2 on the bottom surface of the N electrode lead 2. On the other hand, in a region other than the N-electrode 10, the N-type semiconductor layer 7 and the P-type GaN P-type semiconductor layer 8 are stacked. Below the P-type semiconductor layer 8, a P-electrode 9 made of, for example, gold, which is connected to the P-type semiconductor layer 8, is formed to have a uniform thickness and a large thickness. The connection is made at the hole H1 on the surface. The uniform thickness of the P electrode allows the lower surface of the light emitting layer to be a completely reflecting surface. Further, the P electrode 9 and the N electrode 13 are formed by covering with a protective insulating film 11 made of, for example, silicon oxide or aluminum oxide, so that effects such as electromigration can be prevented. Further, the gap between the semiconductor chip and the electrode lead is sealed with an underfill sealant 14.
【0038】上記の本実施形態の発光素子によれば、半
導体チップと電極リードとがその間に配置された導電層
により接続されており、従来のような発光層からの光を
遮るワイヤボンディングや半透明の薄膜電極がないため
に光の取り出し効率が向上する。また、電極リードと導
電層を接続する部位の電極リードの凹部底面に位置決め
用の孔が開孔されており、さらに底面に位置決め用の突
起が形成されているので、半導体チップと凹部表面(リ
フレクタ)、あるいは封止樹脂のレンズとの軸合わせが
容易となり、最大輝度となる方向のばらつきを抑えるこ
とができる。According to the light emitting element of the present embodiment, the semiconductor chip and the electrode lead are connected by the conductive layer disposed therebetween, and the conventional wire bonding or half bonding for blocking light from the light emitting layer is performed. Since there is no transparent thin film electrode, light extraction efficiency is improved. In addition, a positioning hole is formed in the bottom surface of the concave portion of the electrode lead at a portion connecting the electrode lead and the conductive layer, and a positioning protrusion is formed on the bottom surface. ) Or the alignment of the sealing resin with the lens is facilitated, and variations in the direction of maximum brightness can be suppressed.
【0039】また、導電層として金属などの熱伝導性の
材料を用いることにより、発光層の通電による発熱を直
接電極リードへ伝導し、放熱することが可能となり、放
熱効率を向上させることができる。また、P電極および
N電極の膜厚は十分に厚くすることができるので、電極
部分の電気抵抗が下げることが可能となり、電極部分で
の発熱量を少なくすることができる。さらに半導体チッ
プと電極リードの凹部底面との熱膨張率の違いによる熱
ストレスを吸収するアンダーフィル封止剤に、通常の半
導体装置で実績のある不透明で熱抵抗の小さい材料を用
いることが可能となる。In addition, by using a heat conductive material such as a metal as the conductive layer, heat generated by energization of the light emitting layer can be directly conducted to the electrode lead and radiated, thereby improving heat radiation efficiency. . Further, since the thickness of the P electrode and the N electrode can be made sufficiently large, the electric resistance of the electrode portion can be reduced, and the amount of heat generated at the electrode portion can be reduced. Furthermore, it is possible to use an opaque, low thermal resistance material that has been proven in ordinary semiconductor devices as an underfill sealant that absorbs thermal stress due to the difference in the thermal expansion coefficient between the semiconductor chip and the bottom of the concave part of the electrode lead. Become.
【0040】また、従来の半導体発光素子において、半
導体チップの裏面側から出る光はエポキシ樹脂などの接
着剤層を介してリフレクタ面(電極リード凹部表面)で
反射し、凹部の開口側へ出るようにしていたが、半導体
チップの発光が接着剤層に照射して茶色などの色に変色
するため、特に青色の半導体発光素子は発光する光を接
着剤層に吸収されてしまい、寿命が短くなってしまう
が、上記の本実施形態の半導体発光素子はP電極および
N電極の発光層側表面が反射面となり、発光する光は接
着剤層あるいはアンダーフィル封止剤に実質的に到達し
なく、上記の問題を回避でき、寿命を従来よりものばす
ことができる。Further, in the conventional semiconductor light emitting device, light emitted from the back surface side of the semiconductor chip is reflected on the reflector surface (surface of the electrode lead concave portion) through an adhesive layer such as an epoxy resin, and exits toward the opening side of the concave portion. However, since the light emitted from the semiconductor chip irradiates the adhesive layer and changes its color to a color such as brown, the light emitted from the semiconductor light-emitting element is particularly absorbed by the adhesive layer, thereby shortening the life of the semiconductor light-emitting element. However, in the semiconductor light emitting device of the present embodiment described above, the light emitting layer side surfaces of the P electrode and the N electrode serve as reflection surfaces, and emitted light does not substantially reach the adhesive layer or the underfill sealant. The above problem can be avoided, and the life can be made longer than before.
【0041】第2実施形態 本実施形態にかかる半導体発光素子は、図1に示す第1
実施形態の半導体発光素子と実質的に同じである。本実
施形態の半導体発光素子の要部を拡大した平面図を図4
(a)に、図4(a)中のA−A’における断面図を図
4(b)に示す。第1実施形態の半導体発光素子と異な
り、個々の電極リード半導体チップとの接続部に位置決
め用の孔が開孔されておらず、また、底面の長辺近傍に
は位置決め用の突起も形成されていない。PN接合体中
のP型半導体層に接続するP電極にはP電極凸部16が
形成されており、また、N電極にはN電極凸部17が形
成されている。例えば異方性導電フィルムからなる異方
性導電層18を介して、P電極凸部16はP電極リード
1へ、N電極凸部17はN電極リード2へ、それぞれ接
続しており、P電極およびN電極間は異方性導電層18
により絶縁されている。また、異方性導電層18により
半導体チップ3が電極リードの凹部底面に固定されてい
る。 Second Embodiment The semiconductor light emitting device according to the second embodiment is the first light emitting device shown in FIG.
This is substantially the same as the semiconductor light emitting device of the embodiment. FIG. 4 is an enlarged plan view of a main part of the semiconductor light emitting device of the present embodiment.
FIG. 4A is a cross-sectional view taken along the line AA ′ in FIG. Unlike the semiconductor light emitting device of the first embodiment, no positioning hole is formed in the connection portion with each electrode lead semiconductor chip, and a positioning projection is formed near the long side of the bottom surface. Not. The P electrode connected to the P-type semiconductor layer in the PN junction has a P electrode projection 16 formed thereon, and the N electrode has an N electrode projection 17 formed thereon. For example, the P-electrode protrusion 16 is connected to the P-electrode lead 1 and the N-electrode protrusion 17 is connected to the N-electrode lead 2 via an anisotropic conductive layer 18 made of an anisotropic conductive film. And an anisotropic conductive layer 18 between the N electrodes
Insulated by Further, the semiconductor chip 3 is fixed to the bottom of the concave portion of the electrode lead by the anisotropic conductive layer 18.
【0042】上記の半導体チップ3近傍をさらに拡大し
た断面図を図5に示す。例えば光透過性である透明なサ
ファイア基板6の下層にN型GaNからなるN型半導体
層7が形成されており、その下層に例えば金からなるN
電極10およびN電極凸部17が形成されている、一
方、N電極10を除く領域では、N型半導体層7とP型
GaNのP型半導体層8が積層されている。P型半導体
層8の下層には、P型半導体層8に接続する例えば金か
らなるP電極9が一様な膜厚で厚く形成されており、そ
の下層にP電極凸部16が形成されている。上記のP電
極9、P電極凸部16、N電極10およびN電極凸部1
7は例えば異方性導電フィルムからなる異方性導電層1
8に被覆されている。P電極凸部16下部およびN電極
凸部17下部の異方性導電層は押しつぶされて薄くなっ
ており、異方性導電層中の導電性粒子(図中黒い点で表
示)が、その下部にあるP電極リード1とP電極凸部1
6の間、あるいはN電極リード2とN電極凸部17の間
の導通をもたらす。FIG. 5 shows a further enlarged sectional view of the vicinity of the semiconductor chip 3. For example, an N-type semiconductor layer 7 made of N-type GaN is formed under a transparent sapphire substrate 6 which is light-transmitting, and an N-type semiconductor layer
The electrode 10 and the N-electrode projection 17 are formed, while the N-type semiconductor layer 7 and the P-type GaN P-type semiconductor layer 8 are laminated in a region other than the N-electrode 10. Under the P-type semiconductor layer 8, a P-electrode 9 made of, for example, gold connected to the P-type semiconductor layer 8 is formed with a uniform thickness and thick, and a P-electrode projection 16 is formed under the P-electrode 9. I have. The above-mentioned P electrode 9, P electrode convex portion 16, N electrode 10, and N electrode convex portion 1
Reference numeral 7 denotes an anisotropic conductive layer 1 made of, for example, an anisotropic conductive film.
8. The anisotropic conductive layers below the P-electrode protrusions 16 and the N-electrode protrusions 17 are crushed and thinned, and the conductive particles (indicated by black dots in the figure) in the anisotropic conductive layers are underneath. Electrode lead 1 and P electrode protrusion 1
6 or between the N electrode lead 2 and the N electrode projection 17.
【0043】上記の本実施形態の半導体発光素子は、異
方性導電フィルム、あるいは異方性導電材料を塗布して
形成した異方性導電層を1対の電極リードとP電極ある
いはN電極を接続する導電層としており、電極リードへ
の半導体チップの接続、位置決め、固定を同時に行うこ
とができるので、工程を簡略化して容易に製造すること
ができる。また、第1実施形態の個々の電極リード半導
体チップとの接続部に形成する位置決め用の孔、あるい
は底面の長辺近傍などに形成される位置決め用の突起は
必要なく、容易に形成することができる半導体発光素子
である。The semiconductor light emitting device of this embodiment described above comprises an anisotropic conductive film or an anisotropic conductive layer formed by applying an anisotropic conductive material, and a pair of electrode leads and a P electrode or an N electrode. Since it is a conductive layer to be connected, connection, positioning, and fixing of the semiconductor chip to the electrode lead can be performed simultaneously, so that the process can be simplified and the device can be easily manufactured. Further, a positioning hole formed in a connection portion between each electrode lead semiconductor chip of the first embodiment and a positioning protrusion formed near the long side of the bottom surface is not required, and can be easily formed. A semiconductor light emitting device that can be used.
【0044】上記の半導体発光素子の製造方法について
説明する。まず、図6(a)に示すように、例えば光透
過性である透明なサファイアウェハ6上に例えばエピタ
キシャル成長によりN型GaNからなるN型半導体層7
を形成し、その上層にP型GaNのP型半導体層8を形
成する。P型半導体層8の上層には例えば金からなるP
電極9およびP電極凸部16を形成し、一方N型半導体
層7の上層にも同じく例えば金からなるN電極10およ
びN電極凸部17を形成する。A method for manufacturing the above semiconductor light emitting device will be described. First, as shown in FIG. 6A, an N-type semiconductor layer 7 made of N-type GaN by, for example, epitaxial growth on a transparent sapphire wafer 6 that is light-transmissive, for example.
Is formed, and a P-type semiconductor layer 8 of P-type GaN is formed thereon. The upper layer of the P-type semiconductor layer 8 is made of P
The electrode 9 and the P-electrode projection 16 are formed, while the N-electrode 10 and the N-electrode projection 17 made of, for example, gold are also formed on the upper layer of the N-type semiconductor layer 7.
【0045】次に、図6(b)に示すように、P電極
9、P電極凸部16、N電極10およびN電極凸部17
上に例えば異方性導電フィルムを被覆して、あるいは異
方性導電材料を塗布して、異方性導電層18を形成す
る。Next, as shown in FIG. 6B, the P electrode 9, the P electrode convex portion 16, the N electrode 10 and the N electrode convex portion 17 are formed.
The anisotropic conductive layer 18 is formed by coating an anisotropic conductive film or applying an anisotropic conductive material thereon.
【0046】次に、図6(c)に示すように、ダイシン
グ工程により、1つのウェハを個々の半導体チップ(図
面上C1、C2)に分割する。以降の工程としては、各
半導体チップを電極凸部側から1対の電極リードに押し
つけて、異方性導電層18を押しつぶし、異方性導電層
18の接着力により固定する。このとき、P電極凸部1
6とP電極リード1との間、あるいは、N電極凸部17
とN電極リード2との間の異方性導電層18は薄く押し
つぶされ、異方性導電層18中の導電性粒子により、P
電極凸部16とP電極リード1との間およびN電極凸部
17とN電極リード2との間に導通がもたらされる。次
に、例えば封止樹脂で全体を封止するなどして半導体発
光素子とする。Next, as shown in FIG. 6C, one wafer is divided into individual semiconductor chips (C1, C2 in the drawing) by a dicing process. In the subsequent steps, each semiconductor chip is pressed against the pair of electrode leads from the side of the electrode protrusions to crush the anisotropic conductive layer 18 and fix the semiconductor chip by the adhesive force of the anisotropic conductive layer 18. At this time, the P electrode protrusion 1
6 and the P electrode lead 1, or the N electrode projection 17
The anisotropic conductive layer 18 between the anisotropic conductive layer 18 and the N electrode lead 2 is thinly crushed.
Electrical continuity is provided between the electrode projection 16 and the P electrode lead 1 and between the N electrode projection 17 and the N electrode lead 2. Next, for example, the whole is sealed with a sealing resin to obtain a semiconductor light emitting element.
【0047】次に、上記の製造方法と別の製造方法につ
いて説明する。まず、図7(a)に至るまでの工程は上
記の方法と同様である。次に、図7(b)に示すよう
に、ウェハの各半導体チップに分割位置に格子状のスリ
ットSを入れる。このとき、個々の半導体チップに完全
に分割しないように、スリットはウェハの途中まで入れ
て止める。Next, another manufacturing method different from the above manufacturing method will be described. First, steps up to FIG. 7A are the same as in the above method. Next, as shown in FIG. 7B, a lattice-shaped slit S is formed at each division position in each semiconductor chip of the wafer. At this time, the slit is partially inserted into the wafer and stopped so as not to be completely divided into individual semiconductor chips.
【0048】次に、図7(c)に示すように、P電極
9、P電極凸部16、N電極10およびN電極凸部17
上に例えばロール転写印刷法などにより異方性導電材料
を塗布して、異方性導電層18を形成する。このとき、
スリット部Sには異方性導電層は形成しないようにす
る。Next, as shown in FIG. 7C, the P electrode 9, the P electrode convex portion 16, the N electrode 10 and the N electrode convex portion 17 are formed.
An anisotropic conductive material is applied thereon by, for example, a roll transfer printing method to form an anisotropic conductive layer 18. At this time,
An anisotropic conductive layer is not formed in the slit portion S.
【0049】次に、図7(d)に示すように、ウェハに
図示しないエキスパンドフィルムを貼り付け、スリット
部Sを拡げるようにして分割し、1つのウェハを個々の
半導体チップ(図面上D1、D2)に分割する。以降の
工程としては、上記の方法と同様にして、例えば各半導
体チップを電極凸部側から1対の電極リードに押しつけ
て、P電極凸部16とP電極リード1との間、あるい
は、N電極凸部17とN電極リード2との間を異方性導
電層18中の導電性粒子により導通するようにして固定
し、封止樹脂で全体を封止するなどして半導体発光素子
とする。Next, as shown in FIG. 7D, an expanded film (not shown) is attached to the wafer, and the wafer is divided so as to expand the slit portion S. One wafer is divided into individual semiconductor chips (D1, D1 in the drawing). D2). In the subsequent steps, for example, each semiconductor chip is pressed against a pair of electrode leads from the side of the electrode protrusions to form a gap between the P electrode protrusion 16 and the P electrode lead 1 or N The electrode projection 17 and the N-electrode lead 2 are fixed so as to be conductive by the conductive particles in the anisotropic conductive layer 18, and the whole is sealed with a sealing resin to obtain a semiconductor light emitting element. .
【0050】上記の本実施形態の半導体発光素子の製造
方法によれば、半導体チップと電極リードとを異方性導
電層により接続するので、従来のような発光層からの光
を遮るワイヤや半透明の薄膜電極がなく、さらにP電極
およびN電極の膜厚は十分に厚くすることができるの
で、電極部分での光の反射率が高まり、光の取り出し効
率を向上させた半導体発光素子を製造することができ
る。電極リードの凹部底面における光の反射率を高める
必要性が少なくなるので、凹部底面を鏡面としないでよ
くなるので電極リードの製造コストを抑えることができ
る。また、ウェハの個々の半導体チップへの分割の前に
異方性導電層を形成するので製造が容易であり、さらに
電極リードへの半導体チップの接続、位置決め、固定を
同時に行うことができるので、工程を簡略化して容易に
製造することができる。According to the method for manufacturing a semiconductor light emitting device of the present embodiment, the semiconductor chip and the electrode leads are connected by the anisotropic conductive layer, so that a wire or a half that blocks light from the light emitting layer as in the prior art is used. Since there is no transparent thin-film electrode and the thickness of the P electrode and the N electrode can be made sufficiently thick, the light reflectance at the electrode portion is increased, and a semiconductor light emitting device with improved light extraction efficiency is manufactured. can do. Since the necessity of increasing the light reflectance on the bottom surface of the concave portion of the electrode lead is reduced, the concave bottom surface does not have to be a mirror surface, so that the manufacturing cost of the electrode lead can be reduced. In addition, since the anisotropic conductive layer is formed before dividing the wafer into individual semiconductor chips, manufacturing is easy, and connection, positioning, and fixing of the semiconductor chips to the electrode leads can be performed at the same time. The process can be simplified and easily manufactured.
【0051】第3実施形態 本実施形態にかかる表示装置の模式図を図8に示す。第
1実施形態あるいは第2実施形態にかかる半導体発光素
子を複数個マトリクス状に並べて形成した表示装置であ
る。図面上は3個の半導体発光素子(LED1、LED
2、LED3)で代表して示している。表示画面を垂直
に置いて用いられる表示装置としたときの表示画面の水
平方向を方向Hで、垂直方向を方向Vで示している。各
半導体発光素子のP電極12とN電極13の位置関係が
一方向に揃えられている。ここでは、各半導体発光素子
のP電極12が上側(図面上u側)となるように揃えら
れている。また、複数個の半導体発光素子3の発光中心
ECが上側に揃えられている。また、1対の電極リード
1、2の分割面が略水平方向(図面上H方向)になるよ
うに揃えられている。これにより、表示装置の画面の上
方方向よりも下方方向、垂直方向よりも水平方向の視野
角を拡げることができる。各半導体発光素子が高輝度で
あるので、屋外用の高輝度が必要な表示装置を提供する
ことができる。 Third Embodiment FIG. 8 is a schematic diagram of a display device according to the third embodiment . This is a display device in which a plurality of the semiconductor light emitting devices according to the first embodiment or the second embodiment are arranged in a matrix. In the drawing, three semiconductor light-emitting elements (LED1, LED
2, LED 3). The horizontal direction of the display screen when the display screen is used as a display device placed vertically is indicated by a direction H, and the vertical direction is indicated by a direction V. The positional relationship between the P electrode 12 and the N electrode 13 of each semiconductor light emitting element is aligned in one direction. Here, the P electrodes 12 of the respective semiconductor light emitting elements are arranged so as to be on the upper side (u side in the drawing). The light emission centers EC of the plurality of semiconductor light emitting elements 3 are aligned on the upper side. Further, the pair of electrode leads 1 and 2 are aligned so that the divided surfaces thereof are substantially in the horizontal direction (the H direction in the drawing). This makes it possible to increase the viewing angle in the lower direction than the upper direction of the screen of the display device and in the horizontal direction than in the vertical direction. Since each semiconductor light emitting element has high luminance, it is possible to provide a display device which requires outdoor high luminance.
【0052】本発明は、上記の実施の形態に限定されな
い。例えば、半導体チップの基板はサファイア基板に限
らず、透明であればどんな基板でも用いることができ
る。また、半導体層もGaNの他の半導体を用いること
が可能である。P電極およびN電極は特に限定はない
が、膜厚を厚くすることで光を反射することができる材
料であることが望ましい。その他、本発明の要旨を逸脱
しない範囲で種々の変更を行うことができる。The present invention is not limited to the above embodiment. For example, the substrate of the semiconductor chip is not limited to a sapphire substrate, and any transparent substrate can be used. Further, another semiconductor such as GaN can be used for the semiconductor layer. The P electrode and the N electrode are not particularly limited, but are preferably made of a material that can reflect light by increasing the film thickness. In addition, various changes can be made without departing from the spirit of the present invention.
【0053】[0053]
【発明の効果】本発明の半導体発光素子によれば、発光
層より発生した光を有効に取り出すことが可能な半導体
発光素子を提供することができる。According to the semiconductor light emitting device of the present invention, it is possible to provide a semiconductor light emitting device capable of effectively extracting light generated from the light emitting layer.
【0054】本発明の半導体発光素子の製造方法によれ
ば、本発明の半導体発光素子を容易に製造可能で、光の
取り出し効率を向上させた半導体発光素子を製造するこ
とができる。According to the method for manufacturing a semiconductor light emitting device of the present invention, the semiconductor light emitting device of the present invention can be easily manufactured, and a semiconductor light emitting device with improved light extraction efficiency can be manufactured.
【0055】また本発明の表示装置によれば、上記の本
発明の半導体発光素子をマトリクス状に複数個並べて形
成した、発光層より発生した光を有効に取り出すことが
可能な表示装置を提供することができる。Further, according to the display device of the present invention, there is provided a display device formed by arranging a plurality of the semiconductor light emitting elements of the present invention in a matrix and capable of effectively extracting light generated from the light emitting layer. be able to.
【図1】図1は第1実施形態にかかる半導体発光素子の
模式図である。FIG. 1 is a schematic diagram of a semiconductor light emitting device according to a first embodiment.
【図2】図2(a)は第1実施形態にかかる半導体発光
素子の要部を拡大した平面図であり、図2(b)は図2
(a)のA−A’における断面図である。FIG. 2A is an enlarged plan view of a main part of the semiconductor light emitting device according to the first embodiment, and FIG. 2B is a plan view of FIG.
It is sectional drawing in AA 'of (a).
【図3】図3は図2(b)の半導体チップ近傍をさらに
拡大した断面図である。FIG. 3 is a sectional view further enlarging the vicinity of the semiconductor chip of FIG. 2 (b).
【図4】図4(a)は第2実施形態にかかる半導体発光
素子の要部の平面図であり、図4(b)は図4(a)の
A−A’における断面図である。FIG. 4A is a plan view of a main part of a semiconductor light emitting device according to a second embodiment, and FIG. 4B is a cross-sectional view taken along line AA ′ of FIG. 4A.
【図5】図5は図4(b)の半導体チップ近傍をさらに
拡大した断面図である。FIG. 5 is a cross-sectional view further enlarging the vicinity of the semiconductor chip of FIG. 4 (b).
【図6】図6は第2実施形態にかかる半導体発光素子の
製造方法の製造工程を示す断面図であり、(a)はN電
極凸部およびP電極凸部の形成工程まで、(b)は異方
性導電層の形成工程まで、(c)はダイシング工程まで
を示す。FIGS. 6A and 6B are cross-sectional views illustrating a manufacturing process of a method for manufacturing a semiconductor light emitting device according to a second embodiment, in which FIG. 6A illustrates up to the process of forming an N-electrode projection and a P-electrode projection, and FIG. Shows up to the step of forming an anisotropic conductive layer, and (c) shows up to the dicing step.
【図7】図7は第2実施形態にかかる半導体発光素子の
製造方法の製造工程を示す断面図であり、(a)はN電
極凸部およびP電極凸部の形成工程まで、(b)はウェ
ハに格子状のスリットを入れる工程まで、(c)は異方
性導電層の形成工程まで、(d)は個々の半導体チップ
に分割する工程までを示す。FIGS. 7A and 7B are cross-sectional views illustrating a manufacturing process of a method for manufacturing a semiconductor light emitting device according to a second embodiment, in which FIG. 7A illustrates up to a process of forming an N-electrode projection and a P-electrode projection, and FIG. 5A shows a process of forming a lattice-shaped slit in a wafer, FIG. 5C shows a process of forming an anisotropic conductive layer, and FIG. 5D shows a process of dividing an individual semiconductor chip.
【図8】図8は第3実施形態にかかる表示装置の模式図
である。FIG. 8 is a schematic diagram of a display device according to a third embodiment.
【図9】図9は従来例にかかる半導体装置の模式図であ
る。FIG. 9 is a schematic diagram of a semiconductor device according to a conventional example.
【図10】図10(a)は従来例にかかる半導体装置の
要部拡大図であり、図10(b)は図10(a)のB−
B’における断面図である。FIG. 10A is an enlarged view of a main part of a semiconductor device according to a conventional example, and FIG. 10B is a sectional view taken along line B-B of FIG.
It is sectional drawing in B '.
【図11】図11は図10(b)の半導体チップ近傍を
さらに拡大した断面図である。FIG. 11 is a cross-sectional view further enlarging the vicinity of the semiconductor chip of FIG. 10 (b).
1…P電極リード、2…N電極リード、3…半導体チッ
プ、4…封止樹脂(レンズ)、5…半導体チップ用凹部
側壁面、5’…半導体チップ用凹部底面、6…サファイ
ア基板、7…N型半導体層、8…P型半導体層、9…P
電極、10…N電極、11…保護絶縁膜、12、13…
導電層、14…アンダーフィル封止剤、15…位置決め
用突起、16…P電極凸部、17…N電極凸部、18…
異方性導電層、H1、H2…位置決め用孔、J…PN接
合体、E…発光領域、C1、C2、D1、D2…半導体
チップ、S…スリット、LED1〜LED3…半導体発
光素子、21…N電極リード、22…P電極リード、2
3…半導体チップ、24…封止樹脂(レンズ)、25、
26…ワイヤ、27…半導体チップ用凹部側壁面、2
7’…半導体チップ用凹部底面、28…サファイア基
板、29…N型半導体層、30…N電極、31…活性
層、32…P型半導体層、33…第1P電極、34…第
2P電極、35…保護絶縁膜、36…接着層。DESCRIPTION OF SYMBOLS 1 ... P electrode lead, 2 ... N electrode lead, 3 ... Semiconductor chip, 4 ... Seal resin (lens), 5 ... Semiconductor chip recess side wall surface, 5 '... Semiconductor chip recess bottom surface, 6 ... Sapphire substrate, 7 ... N-type semiconductor layer, 8 ... P-type semiconductor layer, 9 ... P
Electrode, 10 ... N electrode, 11 ... Protective insulating film, 12, 13 ...
Conductive layer, 14: underfill sealant, 15: projection for positioning, 16: convex portion of P electrode, 17: convex portion of N electrode, 18 ...
Anisotropic conductive layer, H1, H2: positioning hole, J: PN junction, E: light emitting area, C1, C2, D1, D2: semiconductor chip, S: slit, LED1 to LED3: semiconductor light emitting element, 21 ... N electrode lead, 22 ... P electrode lead, 2
3 ... semiconductor chip, 24 ... sealing resin (lens), 25,
26: Wire, 27: Side wall surface of recess for semiconductor chip, 2
7 ′: bottom surface of concave portion for semiconductor chip, 28: sapphire substrate, 29: N-type semiconductor layer, 30: N electrode, 31: active layer, 32: P-type semiconductor layer, 33: first P electrode, 34: second P electrode, 35: protective insulating film, 36: adhesive layer.
Claims (19)
て形成され、前記P型半導体層と前記N型半導体層の間
に所定の電圧を印加することにより光を発する発光層
と、前記P型半導体層と前記N型半導体層にそれぞれ接
続するP電極およびN電極を有する半導体チップと、 表面が前記発光層の発する光の反射面となっている前記
半導体チップ用凹部を有し、互いに絶縁するように分割
されている1対の電極リードと、 前記1対の電極リードと前記P電極あるいは前記N電極
を接続するように前記1対の電極リードと前記P電極あ
るいは前記N電極の間に配置されている導電層とを有す
る半導体発光素子。A light-emitting layer formed by laminating a p-type semiconductor layer and an n-type semiconductor layer and emitting light by applying a predetermined voltage between the p-type semiconductor layer and the n-type semiconductor layer; A semiconductor chip having a P-electrode and an N-electrode connected to the P-type semiconductor layer and the N-type semiconductor layer, respectively; and a recess for the semiconductor chip, the surface of which is a reflection surface of light emitted from the light emitting layer. A pair of electrode leads divided so as to be insulated from each other, and the pair of electrode leads and the P electrode or the N electrode to connect the pair of electrode leads to the P electrode or the N electrode. A semiconductor light-emitting device having a conductive layer disposed between them.
れている請求項1記載の半導体発光素子。2. The semiconductor light emitting device according to claim 1, wherein said light emitting layer is formed on a light transmitting insulating substrate.
ある請求項1記載の半導体発光素子。3. The semiconductor light emitting device according to claim 1, wherein said pair of electrode leads have a substantially plane-symmetric shape.
の電極リードが分割されている請求項1記載の半導体発
光素子。4. The semiconductor light emitting device according to claim 1, wherein said pair of electrode leads are divided at diagonal positions of said semiconductor chip.
状が前記半導体チップの形状と略相似形である請求項1
記載の半導体発光素子。5. The semiconductor device according to claim 1, wherein the shape of the bottom surface of the concave portion of the pair of electrode leads is substantially similar to the shape of the semiconductor chip.
The semiconductor light-emitting device according to claim 1.
記一方の電極リードの前記凹部の底面形状が三角形形状
であり、前記三角形の頂角の角度が、前記半導体チップ
の頂角のなす角度と同じである請求項5記載の半導体発
光素子。6. The semiconductor chip has a substantially square shape, the bottom shape of the concave portion of the one electrode lead has a triangular shape, and the angle of the apex angle of the triangle is the angle formed by the apex angle of the semiconductor chip. 6. The semiconductor light emitting device according to claim 5, which is the same as described above.
導体チップの厚さがほぼ同じである請求項1記載の半導
体発光素子。7. The semiconductor light emitting device according to claim 1, wherein a depth of said concave portion of said electrode lead is substantially equal to a thickness of said semiconductor chip.
前記発光層の発する光を反射する鏡面に形成されている
請求項1記載の半導体発光素子。8. The semiconductor light emitting device according to claim 1, wherein said concave surface of said electrode lead is substantially formed as a mirror surface for reflecting light emitted from said light emitting layer.
口側ほど広がっているテーパ形状である請求項1記載の
半導体発光素子。9. The semiconductor light emitting device according to claim 1, wherein the side wall surface of the concave surface of the electrode lead has a tapered shape that becomes wider toward the opening.
半導体チップの位置決め用孔が開孔されており、前記孔
が前記P電極あるいは前記N電極に接続する導電体で埋
め込まれている請求項1記載の半導体発光素子。10. A positioning hole for the semiconductor chip is formed in a bottom surface of the concave portion of the electrode lead, and the hole is filled with a conductor connected to the P electrode or the N electrode. 2. The semiconductor light emitting device according to 1.
領域を除いて前記P電極と前記N電極が導電体に対する
ぬれ性が悪い絶縁体で被覆されている請求項1記載の半
導体発光素子。11. The semiconductor light emitting device according to claim 1, wherein the P electrode and the N electrode are covered with an insulator having poor wettability to the conductor except for a region connected to the electrode lead by a conductor.
半導体層とN型半導体層の接合面とを略平行に位置決め
するための少なくとも三個の突起が前記1対の電極リー
ドの凹部底面に形成されている請求項1記載の半導体発
光素子。12. At least three protrusions for positioning the bottom surface of the recess and the bonding surface of the P-type semiconductor layer and the N-type semiconductor layer of the semiconductor chip substantially in parallel are provided on the bottom surface of the recess of the pair of electrode leads. 2. The semiconductor light emitting device according to claim 1, wherein the semiconductor light emitting device is formed.
求項1記載の半導体発光素子。13. The semiconductor light emitting device according to claim 1, wherein said conductive layer is an anisotropic conductive material.
体層とP型半導体層との接合体であり、前記P型半導体
層と前記N型半導体層の間に所定の電圧を印加すること
により光を発する発光層を形成する工程と、 前記P型半導体層に接続するP電極を形成する工程と、 前記N型半導体層に接続するN電極を形成する工程と、 前記P電極および前記N電極を被覆して異方性導電層を
形成する工程と、 前記ウェハをダイシングして個々の半導体チップに分割
する工程と、 表面が前記発光層の発する光の反射面となっている前記
半導体チップ用凹部を有し、互いに絶縁するように分割
されている1対の電極リードに、前記1対の電極リード
と前記P電極あるいは前記N電極を前記異方性導電層を
介して接続するように、前記半導体チップを固定する工
程とを有する半導体発光素子の製造方法。14. A bonded body of an N-type semiconductor layer and a P-type semiconductor layer on a light-transmitting insulating wafer, and a predetermined voltage is applied between the P-type semiconductor layer and the N-type semiconductor layer. Forming a light-emitting layer that emits light, forming a P-electrode connected to the P-type semiconductor layer, forming an N-electrode connected to the N-type semiconductor layer, Forming an anisotropic conductive layer by covering the N-electrode, dicing the wafer into individual semiconductor chips, and forming a surface on which a light-reflecting surface of the light-emitting layer is reflected. The pair of electrode leads and the P electrode or the N electrode are connected via the anisotropic conductive layer to a pair of electrode leads having a recess for a semiconductor chip and divided so as to be insulated from each other. So that the semiconductor chip is fixed The method of manufacturing a semiconductor light emitting device and a that step.
体層とP型半導体層との接合体であり、前記P型半導体
層と前記N型半導体層の間に所定の電圧を印加すること
により光を発する発光層を形成する工程と、 前記P型半導体層に接続するP電極を形成する工程と、 前記N型半導体層に接続するN電極を形成する工程と、 前記ウェハに格子状のスリットを入れる工程と、 前記P電極および前記N電極を被覆して異方性導電層を
形成する工程と、 前記ウェハのスリット部を拡げて個々の半導体チップに
分割する工程と、 表面が前記発光層の発する光の反射面となっている前記
半導体チップ用凹部を有し、互いに絶縁するように分割
されている1対の電極リードに、前記1対の電極リード
と前記P電極あるいは前記N電極を前記異方性導電層を
介して接続するように、前記半導体チップを固定する工
程とを有する半導体発光素子の製造方法。15. A joined body of an N-type semiconductor layer and a P-type semiconductor layer on a light-transmitting insulating wafer, and a predetermined voltage is applied between the P-type semiconductor layer and the N-type semiconductor layer. Forming a light emitting layer that emits light, forming a P electrode connected to the P-type semiconductor layer, forming an N electrode connected to the N-type semiconductor layer, and forming a lattice on the wafer. Forming an anisotropic conductive layer by covering the P-electrode and the N-electrode; expanding the slit portion of the wafer to divide the wafer into individual semiconductor chips; The pair of electrode leads having the concave portion for the semiconductor chip serving as a reflection surface of light emitted by the light emitting layer and being divided so as to be insulated from each other, the pair of electrode leads and the P electrode or the P electrode N electrode is anisotropic conductive To connect through a method of manufacturing a semiconductor light emitting device and a step of fixing the semiconductor chip.
せて形成され、前記P型半導体層と前記N型半導体層の
間に所定の電圧を印加することにより光を発する発光層
と、前記P型半導体層と前記N型半導体層にそれぞれ接
続するP電極およびN電極を有する半導体チップと、 表面が前記発光層の発する光の反射面となっている前記
半導体チップ用凹部を有し、互いに絶縁するように分割
されている1対の電極リードと、 前記1対の電極リードと前記P電極あるいは前記N電極
を接続するように前記1対の電極リードと前記P電極あ
るいは前記N電極の間に配置されている導電層とを有す
る半導体発光素子をマトリクス状に複数個並べて形成さ
れている表示装置。16. A light emitting layer which is formed by laminating a P-type semiconductor layer and an N-type semiconductor layer, and emits light by applying a predetermined voltage between the P-type semiconductor layer and the N-type semiconductor layer. A semiconductor chip having a P-electrode and an N-electrode connected to the P-type semiconductor layer and the N-type semiconductor layer, respectively; and a recess for the semiconductor chip, the surface of which is a reflection surface of light emitted from the light emitting layer. A pair of electrode leads divided so as to be insulated from each other, and the pair of electrode leads and the P electrode or the N electrode to connect the pair of electrode leads to the P electrode or the N electrode. A display device in which a plurality of semiconductor light-emitting elements having a conductive layer disposed therebetween are arranged in a matrix.
N電極の位置関係が一方向に揃えられている請求項16
記載の表示装置。17. The semiconductor device according to claim 16, wherein the P electrodes and the N electrodes of the plurality of semiconductor light emitting elements are aligned in one direction.
The display device according to the above.
が上側に揃えられている請求項16記載の表示装置。18. The display device according to claim 16, wherein the light emission centers of said plurality of semiconductor light emitting elements are aligned upward.
方向になるように揃えられている請求項16記載の表示
装置。19. The display device according to claim 16, wherein the division surfaces of the pair of electrode leads are aligned so as to be substantially horizontal.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP31557997A JPH11150295A (en) | 1997-11-17 | 1997-11-17 | Semiconductor light-emitting element, production of the semiconductor light-emitting element, and indicator thereof |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP31557997A JPH11150295A (en) | 1997-11-17 | 1997-11-17 | Semiconductor light-emitting element, production of the semiconductor light-emitting element, and indicator thereof |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH11150295A true JPH11150295A (en) | 1999-06-02 |
Family
ID=18067057
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP31557997A Pending JPH11150295A (en) | 1997-11-17 | 1997-11-17 | Semiconductor light-emitting element, production of the semiconductor light-emitting element, and indicator thereof |
Country Status (1)
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JP (1) | JPH11150295A (en) |
Cited By (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2001274462A (en) * | 2000-03-27 | 2001-10-05 | Aiwa Co Ltd | Light emitting device |
JP2002094128A (en) * | 2000-09-20 | 2002-03-29 | Stanley Electric Co Ltd | Light emitting diode and its manufacturing method |
WO2002089221A1 (en) * | 2001-04-23 | 2002-11-07 | Matsushita Electric Works, Ltd. | Light emitting device comprising led chip |
WO2004051757A2 (en) * | 2002-11-29 | 2004-06-17 | Osram Opto Semiconductors Gmbh | Optoelectronic component |
EP1113506A3 (en) * | 1999-12-28 | 2005-03-16 | Toyoda Gosei Co., Ltd. | Light emitting diode |
JP2007049045A (en) * | 2005-08-11 | 2007-02-22 | Rohm Co Ltd | Semiconductor light emitting device and semiconductor device using the same |
WO2009047727A1 (en) * | 2007-10-09 | 2009-04-16 | Koninklijke Philips Electronics N.V. | Light emitting device package, light output system and light output method |
JP2011258675A (en) * | 2010-06-07 | 2011-12-22 | Toshiba Corp | Optical semiconductor device |
-
1997
- 1997-11-17 JP JP31557997A patent/JPH11150295A/en active Pending
Cited By (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP1113506A3 (en) * | 1999-12-28 | 2005-03-16 | Toyoda Gosei Co., Ltd. | Light emitting diode |
US6906459B2 (en) | 1999-12-28 | 2005-06-14 | Toyoda Gosei Co., Ltd. | Light emitting diode |
JP2001274462A (en) * | 2000-03-27 | 2001-10-05 | Aiwa Co Ltd | Light emitting device |
JP2002094128A (en) * | 2000-09-20 | 2002-03-29 | Stanley Electric Co Ltd | Light emitting diode and its manufacturing method |
WO2002089221A1 (en) * | 2001-04-23 | 2002-11-07 | Matsushita Electric Works, Ltd. | Light emitting device comprising led chip |
WO2004051757A2 (en) * | 2002-11-29 | 2004-06-17 | Osram Opto Semiconductors Gmbh | Optoelectronic component |
WO2004051757A3 (en) * | 2002-11-29 | 2004-12-23 | Osram Opto Semiconductors Gmbh | Optoelectronic component |
US7271425B2 (en) | 2002-11-29 | 2007-09-18 | Osram Opto Semiconductors Gmbh | Optoelectronic component |
JP2007049045A (en) * | 2005-08-11 | 2007-02-22 | Rohm Co Ltd | Semiconductor light emitting device and semiconductor device using the same |
WO2009047727A1 (en) * | 2007-10-09 | 2009-04-16 | Koninklijke Philips Electronics N.V. | Light emitting device package, light output system and light output method |
JP2011258675A (en) * | 2010-06-07 | 2011-12-22 | Toshiba Corp | Optical semiconductor device |
US8754429B2 (en) | 2010-06-07 | 2014-06-17 | Kabushiki Kaisha Toshiba | Optical semiconductor device and method for manufacturing same |
US8981412B2 (en) | 2010-06-07 | 2015-03-17 | Kabushiki Kaisha Toshiba | Optical semiconductor device and method for manufacturing same |
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