JPH11149721A - Phase-locked loop circuit, phase information detector and phase-information detecting method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a PLL(phase locked loop) circuit, in which wide capture and wide locking are carried out even by simple constitution. SOLUTION: In a wide mode, wide capture is attained by inputting error information between an output from an FCO(frequency, comparator output) counter 45 and the measured value (EFM (8-14 modulation) frequency) of a CLV(constant linear velocity) speed counter 33 as the error control signal of a VCO(voltage controlled oscillation circuit) 44 through an integrating circuit 48, a D/A converter 49 and an adder 43 at the time of servo leading-in. An input to the integrating circuit 38 is changed over to the phase-error low-pass component of a PLCK by a PCI (phase comparator integration) circuit 50 and an EFM signal under the state, in which a PLL circuit is locked. Accordingly, the oscillation frequency of the VCO is operated so as to be followed up to EFM signal frequency corresponding to disk rotational speed, and a lock range is widened. The PCI circuit 50 is constituted so as to conduct counting at a level obtained by sampling the PLCK at EFM edge timing.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase-locked loop circuit for generating a clock synchronized with a run-length limited code read from a disk-shaped recording medium to be driven to rotate at a constant linear velocity, and a phase-locked loop circuit. The present invention relates to a phase information detecting apparatus and method for detecting a low-frequency component of a phase error between a run-length limited code and a clock, which is used for expanding a lock range in the present invention.

[0002]

2. Description of the Related Art Systems using a disk such as a CD (compact disk) as a recording medium have become widespread. In such a system, recording data that has been subjected to EFM modulation (8-14 modulation), which is a type of run-length limited code, is recorded on a disk. In addition, a CLV (constant linear velocity) method is employed for rotating the disk.

For the CLV rotation servo, for example, conventionally, an EFM signal read from a disk is converted to a phase locked loop circuit (hereinafter referred to as a PLL (Phase Locked Loop)).
op) circuit to reproduce a clock, and compare the clock with a reference clock obtained by a crystal to obtain rotation error information. The rotation error information is fed back to a spindle motor that rotates the disk, so that a rotation state with a constant linear velocity can be obtained. In order for such a CLV servo circuit to function, the PLL circuit must first be locked and the clock must be accurately extracted. Therefore, when the spindle motor starts up, the EFM that is extracted first is
A configuration for performing rough servo control for drawing a signal into a capture range of a PLL circuit is required. That is, in the disk reproducing apparatus, for example, when the spindle rotation is started, first, a certain degree of rotational servo control is performed by the rough servo circuit, and then, when the PLL circuit is locked, C
The LV servo operation is switched from a rough servo circuit to a normal CLV servo circuit.

FIG. 15 shows a CLV in a disk reproducing apparatus.
2 shows a configuration of a servo system. As shown in this figure, the CLV servo system includes a rough servo circuit 100 and a CLV speed detection circuit 110. Rough servo circuit 100
First, the EFM signal reproduced from the disk is input to the pit length measuring circuit 101. The EFM signal is a run-length limited code defined such that the maximum inversion interval of the code sequence is 11T and the minimum inversion interval is 3T. The pit length of the crystal (X
TAL) is measured based on a reference measurement clock, and information on the measured value is supplied to the maximum value hold circuit 102. The maximum value hold circuit 102 holds the maximum value of the pit length measurement information input from the pit length measurement circuit 101 and outputs the information to the subsequent minimum value hold circuit 103. The minimum value hold circuit 103 holds and outputs the minimum value from the maximum values output from the maximum value hold circuit 102. Here, the hold value in the minimum value hold circuit 103 is calculated from the maximum pit length obtained in the maximum value hold circuit 102.
The minimum pit length will be taken. That is, for example, even if an inversion interval of 11 T or more occurs in the EFM signal due to a reading error due to a scratch on the disk, the EFM signal is canceled, and information of a maximum pit length nearly equal to 11 T is obtained.

In this manner, the minimum value hold circuit 103
In this case, information of a pit length close to the maximum inversion interval of 11T can be obtained within a certain range. However, in the 11T detection circuit 104, the pit length (inversion interval value) held by the minimum value hold circuit 103 is obtained. And the reference 1
By comparing the pit length with the pit length of 1T, a ternary error signal is output. That is, the minimum value hold circuit 103
The hold value and the reference 11T pit length are different when the two are equal, when the reference 11T pit length is larger, and when the reference 11T pit length is smaller. A value comparison signal is output. The error signal obtained in this manner is supplied as a pull-in servo signal CLV-1 to a spindle motor (not shown), whereby rough servo control for CLV is performed.

[0006] The CLV speed detection circuit 110 is first provided with a sync pattern detection circuit 111.
As shown, EFM signal and PLL for clock extraction
A signal PLCK (for example, 4.3218 MHz) corresponding to a clock output from a circuit (not shown) is input. Here, one frame (588 bits) of the EFM signal
A 24-bit sync pattern is encoded at the beginning of the file, and this sync pattern is 11 bits from the top.
It is formed by a fixed pattern of T, 11T, and 2T. Then, in the sync pattern detection circuit 111,
EFM input using signal PLCK as a reference clock
The sync pattern is detected by counting the signal in units of pits (ie, counting every 588 bits).

The detection output of the sync pattern detection circuit 111 is supplied to an interpolation protection circuit 112. If a sync pattern is detected at a position where does not exist, processing such as interpolation of the sync pattern and window protection is performed. The information of the sync pattern output from the interpolation protection circuit 112 is
3 and to the speed counter 114. The frame sync generation circuit 113 generates a frame sync signal based on the input frame sync detection signal, and this frame sync signal is used for required signal processing and the like. Also, the speed counter 114
In this case, speed error information is obtained by counting a frame sync at a timing synchronized with the signal PLCK at a predetermined frequency by a crystal system, and this speed error information is output as a speed detection signal CLV-2. By supplying the speed detection signal CLV-2 to a driver of a spindle motor (not shown), it is possible to execute CLV control in a state where a sync pattern is detected (that is, a state where the PLL circuit is locked). it can. Although not shown here, for the CLV control, for example, a phase error signal obtained by comparing a phase of a clock generated by a PLL circuit with a predetermined frequency signal of a crystal system is used together with the speed detection signal CLV-2. To be.

In the CLV servo system having such a configuration, for example, when the rotation of the spindle motor is started, rough servo control is performed using the system of the rough servo circuit 100, so that the PLL circuit is pulled into the capture range as described above. Control the rotation speed of the spindle motor until In a state where the PLL circuit is locked, the CLV speed detection circuit 11
By switching to the system of 0, the disk rotation speed is controlled to a constant linear velocity.

As a PLL circuit for reproducing a bit clock synchronized with an EFM signal, there is known a PLL circuit having a so-called wide capture function for expanding a capture range and a lock range.
FIG. 16 shows a configuration example of a PLL circuit having such a wide capture function. It should be noted that the PLL circuit shown in this figure is configured to be capable of switching between a normal mode in which the capture range is not expanded and a wide mode in which a wide capture function is provided. The PLL circuit 200 shown in FIG. 16 is formed by two PLL circuit systems of a system clock PLL circuit 300 and an RF PLL circuit 400. System clock PL
The L circuit 300 first divides the frequency of a reference signal of a predetermined frequency generated by an external crystal oscillator 301 and inputs the frequency as a comparison reference signal of a phase comparator 303.
2 are provided. The phase comparator 303 has a frequency divider 307 →
A frequency controlled oscillator (VCO (Voltage Controlled Oscillat) which is divided via a frequency divider 308 → variable frequency divider 309
or)) The phase and frequency of the oscillation frequency signal 306 and the reference signal are compared, and an error signal is output. In this case, this error signal is
Supplied to N.

The switch 304 selects the terminal Tout with respect to the terminal TW (in the wide mode) or the terminal TN (in the normal mode) according to a normal / wide mode switching signal output from a system controller (not shown). It is controlled so as to be connected uniquely. in this case,
An error signal output from the phase comparator 303 is supplied to a terminal T · N, and spindle rotation information is supplied to a terminal T · W. Here, the spindle rotation information is
This signal is a signal having an information value corresponding to the rotation speed of the spindle motor that drives the disk to rotate. Switch 304
Is filtered through a low-pass filter 305 and input to the VCO 306 as an error control signal. In the VCO 306, the oscillation frequency is controlled based on the voltage value as the error control signal. The oscillation frequency is output to the frequency divider 307.

The switch 310 is connected to a terminal T by a normal / wide mode switching signal, similarly to the switch 304.
out is alternatively connected to the terminal T · W or the terminal T · N. In this case, a frequency signal obtained by dividing the oscillation output of the VCO 306 by the frequency divider 307 is supplied to the terminal T · W of the switch 310, and the terminal T · N is supplied to the terminal T · N.
A reference signal from the crystal oscillator 301 is supplied. Terminal T
The output from out is the RFPLL circuit 4 described below.
00 is input to the frequency divider 401.

In the RF PLL circuit 400, a frequency divider 401
, And the frequency signal obtained by dividing the oscillation frequency signal of the VCO 404 through the frequency divider 405 → frequency divider 406 are input to the phase comparator 402 and subjected to error control through the low-pass filter 403. VC as signal
O404. The oscillation frequency signal of the VCO 404 is divided into a frequency divider 405 by a digital PLL circuit 407.
Is input, and an EFM signal reproduced from a disc (not shown) is input. Based on a detection signal obtained by performing a phase comparison based on these two signals, E
A clock synchronized with the FM signal is extracted.

As an operation of the PLL circuit 200 having the above configuration, an operation in a normal mode is as follows. In the normal mode, the switch 304 and the switch 310
In both cases, the terminal Tout is connected to the terminal TN. In this case, the system clock PLL circuit 30
0 of the VCO 306 is output to the RFPLL circuit 400 of the subsequent stage.
Will not be supplied. Therefore, in the normal mode, the system clock PLL circuit 30
0 will not be used as a circuit.

At this time, in the RFPLL circuit 400, the reference signal of the crystal oscillator 301 is supplied to the phase comparator 4 as a comparison reference signal via the switch 310 and the frequency divider 401.
02 will be input. In the phase comparator 402, the comparison reference signal based on the reference signal of the crystal oscillator 301 and the oscillation frequency signal of the VCO 404 are divided by the frequency divider 40.
5 → The phase comparison is performed with respect to the frequency signal input via the frequency divider 406. Thereby, the RFPL
The L circuit 400 converges so that the oscillation frequency of the VCO 404 synchronized with the reference signal of the crystal oscillator 301 is obtained. The digital PLL circuit 407 reproduces a clock synchronized with the EFM signal by using the oscillation frequency of the VCO 404, for example. That is, the RFPLL circuit 400
In the normal mode, the crystal oscillator 30
The PLL circuit loop operates so as to converge on the basis of the reference signal obtained from 1.

The operation of the PLL circuit 200 in the wide mode is as follows. In this case, switch 3
04 and switch 310 both have terminal Tout at terminal T.
W will be connected. Accordingly, in the system clock PLL circuit 300, the phase comparator 3
The output of 03 is invalidated. Instead, the spindle rotation information is input to the VCO 306 from the switch 304 via the low-pass filter 305 as an error control signal. In this case, the oscillation frequency of the VCO 306 is variably controlled according to the rotation speed of the spindle motor.

In the RFPLL circuit 400, instead of the reference signal of the crystal oscillator 301, a frequency signal obtained by dividing the frequency of the VCO 306 by the divider 307 is further divided via the switch 310 → divider 401. Thus, the signal is input to the phase comparator 402 as a comparison reference signal. Therefore, the VCO 404 of the RFPLL circuit 400 is
VCO 30 on the system clock PLL circuit 300 side
The oscillation frequency is controlled so as to synchronize with the frequency signal based on No. 6. This is an operation in which the oscillation frequency of the VCO 404 is varied so as to follow the rotation speed of the spindle motor. Then, as a result of the digital PLL circuit 407 operating based on the output of the VCO 404, even if the disk rotation speed does not reach the specified CLV speed, for example, the digital PLL circuit 407 synchronizes with a clock having a frequency obtained according to the disk rotation speed. Thus, the locking operation is obtained. That is, the capture range of the PLL circuit is widened. Thus, even if a state synchronized with the crystal oscillator 301 is not obtained, data can be read out of the signal processing system as long as the PLL circuit is locked following the disk rotation speed.

[0017]

By the way, in the configuration of the CLV servo system as shown in FIG. 15, the CLV servo is disengaged or lengthened due to disturbances such as when the spindle motor is started or vibrations applied from the outside. In the case where the signal is lost over the period, the system is switched to the rough servo circuit 100 and the rough servo control is resumed. However, as described above, the rough servo circuit 100 sets the pull-in servo signal CLV-1 as 3. Since only a value can be obtained, servo control can be performed only in a narrow band of, for example, 1 Hz or less. For this reason,
It takes a relatively long time to restore the PLL circuit to the locked state again. In the configuration of the CLV servo system as shown in FIG. 15, the CLV speed detection circuit 1
10 and a rough servo circuit 100 for rough servo control, which requires two CLV servo circuit systems, and the circuit scale has been increased accordingly.

Further, in the case of the CLV servo system as shown in FIG. 15, since the rough servo circuit 100 and the CLV speed detection circuit 110 have greatly different servo characteristics, for example, a wide circuit configuration as shown in FIG. Even if a PLL circuit having a capture function is used, for example, if disturbances or the like continue during the pull-in servo, the disk rotation speed error exceeds the tracking range of the PLL circuit, and
There was a high possibility that the L circuit would be unlocked. Particularly in a portable CD player or the like, there is a high possibility that disturbance due to shaking along the disk rotation direction will occur, but the disturbance will cause a remarkable change in the disk rotation speed with respect to the optical pickup. In consideration of such situations, the lock range obtained by the PLL circuit system shown in FIG. 16 and the control operation of the CLV servo system shown in FIG.
It was not enough to expect the servo pull-in operation.

In the circuit configuration of the PLL circuit 200 shown in FIG.
Since the two-stage PLL circuit system of the PLL circuit 400 is required, as in the case of the CLV servo system shown in FIG.

[0020]

SUMMARY OF THE INVENTION In view of the above-mentioned problems, the present invention relates to a PLL circuit used for CLV control of disk rotation and clock reproduction, particularly when it is configured so that the lock range is expanded. It is another object of the present invention to simplify the circuit configuration as much as possible to promote the reduction of the circuit scale and the accompanying cost reduction.

For this reason, in a phase locked loop circuit for extracting a clock synchronized with a run-length limited code read from a rotationally driven disk-shaped recording medium, at least a voltage controlled oscillating means, a disk-shaped recording medium, Phase information detecting means for outputting a low-frequency component of a phase error with respect to a clock obtained based on the output of the voltage-controlled oscillation circuit with respect to the run-length limited code read from the disk, and run-length limited read from the disk-shaped recording medium Phase comparing means for comparing the phase of the frequency signal obtained based on the code and the clock and outputting the phase comparison result (phase error high frequency component);
The voltage-controlled oscillation circuit is based on a control signal component obtained based on a phase error low-frequency component output from the phase information detection means and a control signal component obtained based on a phase comparison result output from the phase comparison means. And an oscillation frequency control means for controlling the oscillation frequency.

Also, a control signal component obtained based on a low-frequency component of a phase error between a clock obtained based on an output of a voltage-controlled oscillation circuit and a run-length limited code read from a disk-shaped recording medium driven in rotation. And a control signal component (phase error high frequency component) obtained by comparing the phase of a run-length limited code read from the disk-shaped recording medium with a frequency signal obtained based on the clock by a phase comparator. A phase information detection device provided in a phase locked loop circuit operable to variably control the oscillation frequency of the control oscillation circuit and for detecting the low-frequency component of the phase error is configured as follows. That is, an edge detecting means for detecting an edge of the run-length limited code read from the disk-shaped recording medium, and a sampling capable of sampling a clock at a timing at which the edge of the run-length limited code is detected by the edge detecting means. Means for performing a counting operation at a timing at which an edge of a run-length limited code is detected by the code edge detecting means, and setting the counting operation to up-counting in accordance with a clock level state at the time of sampling by the sampling means. A counter for setting whether to count down, and outputting a count value of the counter as the low-frequency component of the phase error. Further, during a period in which the phase of the clock to be sampled by the sampling means is inverted from the phase to be originally detected, a sampling operation control means for inhibiting the sampling operation by the sampling means is provided. An offset value set corresponding to the phase error with the detection output of the comparator is held, and the offset value is given to the count value.

Also, a control signal component obtained based on a low-frequency component of a phase error between a run-length limited code read from the rotationally driven disk-shaped recording medium and a clock obtained based on the output of the voltage-controlled oscillation circuit. And a control signal component (phase error high frequency component) obtained by comparing the phase of a run-length limited code read from the disk-shaped recording medium with a frequency signal obtained based on the clock by a phase comparator. A phase information detection method for detecting a phase error low frequency component in a phase locked loop circuit operable to variably control the oscillation frequency of the control oscillation circuit is configured as follows. That is, an edge detection process for detecting an edge of the run-length limited code read from the disk-shaped recording medium, and a clock can be sampled at a timing at which the edge of the run-length limited code is detected by the edge detection process. The counting operation is performed at the timing when the edge of the run-length limited code is detected by the sampling process and the code edge detection process, and the counting operation is up-counted according to the clock level state at the time of sampling by the sampling process. By executing a counter process for setting whether to count down or to count down, the count value obtained by this counter process is output as a detection output of the low-frequency component of the phase error.

According to the above configuration, the configuration of the phase locked loop circuit for extracting a clock synchronized with the run length limited code read from the rotationally driven disk-shaped recording medium is different from that of the run length limited code. A phase information detecting means for outputting a low-frequency component of a phase error with a clock obtained based on the output of the voltage-controlled oscillation circuit will be provided. The PLL circuit operates so as to follow the frequency of the run-length limited code corresponding to the disk rotation speed and variably control the center frequency of the voltage-controlled oscillation circuit. The basic configuration for detecting phase information is as follows:
For example, a configuration in which a clock is sampled at the edge detection timing of a run-length limited code and a configuration as a counter that performs up-counting / down-counting in accordance with the level state of the sampled clock may be provided. .

[0025]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS. The following description will be made in the following order. 1. 1. Configuration of playback device PLL / CLV servo circuit (2-a. Configuration of PLL / CLV servo circuit) (2-b. Configuration of CLV target setting circuit) (2-c. Configuration of PCI circuit) (2-d. Operation in normal mode) (2-e. CLV target variable setting operation by software) (2-f. Operation in wide mode) (2-g. Variable speed reproduction operation)

1. FIG. 1 shows an example of the configuration of a main part of a CD player as a playback device provided with a rotation speed control device and a rotation drive device for CLV servo control according to an embodiment of the present invention. It is a block diagram. Note that C of the present embodiment is
The D player is assumed to be portable, for example, and in response to this, a vibration-proof mode (wide mode) for enabling reproduction sound to be output as stably as possible irrespective of disturbance due to vibration or shaking when the CD player is carried. And a normal mode for performing a normal playback operation.

In FIG. 1, information is read by an optical head 3 while a disk 1 is rotated by a spindle motor 2 at a constant linear velocity (CLV). The optical head 3 irradiates the disk 1 with a laser beam, and reads, for example, information recorded in a pit form on the disk 1 from the reflected light.

In order to perform the data reading operation from the disk 1 as described above, the optical head 3 includes a laser diode 3c for outputting a laser, a polarizing beam splitter,
An optical system 3d including a quarter-wave plate or the like, an objective lens 3a serving as a laser output end, a detector 3b for detecting reflected light, and the like are provided. Objective lens 3
a is held by a biaxial mechanism 4 so as to be displaceable in a disk radial direction (tracking direction) and in a direction of coming into contact with and separating from the disk.
By this, the disk can be moved in the radial direction.

By the reproducing operation of the optical head 3 described above,
Information detected from the disk 1 is supplied to the RF amplifier 6. In this case, the RF amplifier 6 performs amplification processing and necessary arithmetic processing on the input information to obtain a reproduced RF signal, a tracking error signal, a focus error signal, and the like. The optical system servo circuit 12 generates various servo drive signals based on a tracking error signal and a focus error signal supplied from the RF amplifier 6, a track jump command and an access command from the system controller 14, and the like. And the thread mechanism 5 to perform focus and tracking control

The reproduced RF obtained by the RF amplifier 6
The signal is supplied to the binarization circuit 20 in the signal processing circuit 7 to be output as a binarized EFM signal (8-14 modulation signal), and the register 21, the PLL / CLV servo circuit 25, and It is supplied to the synchronization detection circuit 26. Further, the tracking error signal and the focus error signal are supplied to the optical system servo circuit 12.

The EFM signal supplied from the binarization circuit 20 to the EFM decoding circuit 22 via the register 21 is subjected to EFM demodulation. That is, a 14-8 conversion process is performed. Data EFM-demodulated by the EFM decoding circuit 22 is sent to an ECC / deinterleave processing circuit 23.
Supplied to ECC / deinterleave processing circuit 23
Then, the error correction process and the deinterleave process are executed while performing the write and read operations of the data supplied to the RAM 24 at a predetermined timing. E
The data subjected to the error correction processing and the deinterleave processing by the CC / deinterleave processing circuit 23 are supplied to a memory controller 8 described later.

The PLL / CLV servo circuit 25 receives the EFM signal supplied from the binarization circuit 20 and
By operating the circuit, a signal PLCK is output as a reproduction clock synchronized with the EFM signal. This signal PLCK is used as a master clock by the signal processing circuit 7.
It becomes a processing reference clock in the inside. Therefore, the operation timing of the signal processing system of the signal processing circuit 7 follows the rotation speed of the spindle motor 2. Here, the frequency of the signal PLCK in a state where the PLL circuit is locked under the condition that the disk 1 is driven at CLV at n times speed is, for example, n × 4.3218 MHz.

In the present embodiment, the signal processing circuit 7 operates with a clock corresponding to the rotation speed of the spindle motor 2 so that, for example, even when the spindle motor 2 is not rotating at a specific CLV speed. As long as the PLL circuit is locked and the sync pattern can be detected, the processing for the read data can be executed.

The PLL / CLV servo circuit 25 uses a signal obtained by the operation of the PLL circuit, an input EFM signal, and the like to perform CLV control for CLV control.
A servo signal is generated and supplied to the motor driver 13.
The internal configuration of the PLL / CLV servo circuit 25 will be described later. The motor driver 13 is a PLL / CLV
A motor drive signal is generated based on the CLV servo signal supplied from the servo circuit 25 and supplied to the spindle motor 2. Thus, the spindle motor 2 is driven to rotate at a constant linear speed with respect to the disk.

The synchronization detection circuit 26 performs an operation for detecting a frame sync from the EFM signal input from the binarization circuit 20, using the signal PLCK input from the PLL / CLV servo circuit 25 as a reference clock. Here, FIG. 10 shows the structure of one frame of the EFM signal.
Of the 588 bits forming one frame, the first 24 bits are used as a sync pattern. This sync pattern is a fixed pattern formed by a continuous inversion interval of 11T, 11T, and 2T as shown in the figure. Also,
In the synchronization detection circuit 26, the frame sync pattern in the data is lost due to the effect of dropout or jitter,
In the case where the same frame sync pattern is detected, processing such as frame sync interpolation and window protection is also performed. The register 21 stores the synchronization detection circuit 2
6 will be operated in accordance with the output. In the synchronization detection circuit 26, for example, in a state where the number of bits of the frame sync '24' is properly obtained as the count value at the timing of the signal PLCK, a signal indicating that the frame sync is properly detected. The GFS is output, and in this case, is output to the system controller 14.

Here, as described above, the synchronization detection circuit 2
The state where the 6-frame sync is properly detected is determined by the PLL
Since this corresponds to the state where the PLL circuit in the / CLV servo circuit 25 is locked, the system controller 14 locks the PLL circuit in the locked state during the period in which the signal GFS is output. The signal S · LOCK can be output. Although not shown in FIG. 1, the lock signal S · LOCK is used for switching the operation in the PLL / CLV servo circuit 25 as described later.

As described above, the ECC of the signal processing circuit 7
The data output from the / deinterleave processing circuit 23 is so-called digital audio data based on 16-bit quantization and 44.1 kHz sampling, and this digital audio data is supplied to the memory controller 8.

For example, when the above-described vibration proof mode (wide mode) is set, the rotation of the spindle motor 2 is controlled in a speed range higher than that in the normal mode (1 × speed) so that the signal processing circuit is controlled. The signal processing in 7 is also performed at a higher rate than in the normal mode according to the rotation measurement of the spindle motor 2. The digital audio data output from the signal processing circuit 7 at a high rate is written into a RAM (buffer memory) 9 under the control of a memory controller 8 to accumulate the data. 8 performs control according to the normal rate. Thereby, the D / A converter 1
The audio signal converted to an analog signal by 0 and output from the audio output terminal 11 has a normal pitch and speed. When the normal mode is set, the rotation of the spindle motor 2 is controlled in a speed range corresponding to the normal mode, and the signal processing in the signal processing circuit 7 is executed at a rate corresponding to the rotation speed. In this case, the time axis correction of the data is performed by controlling the writing and reading of the RAM 9 by the memory controller 8, whereby the audio output terminal 1 in the normal mode is set.
The pitch and speed of the audio signal output from 1 are made normal. The operation of the memory controller 8 is controlled by the system controller 14.

The system controller 14 is provided with a microcomputer and the like, and appropriately executes control processing according to required operations to be performed by the respective functional circuit units constituting the CD player. The operation unit 15 is provided with various keys for the user to perform various operations such as playback, pause, stop, search, and the like. Is supplied to the system controller 14. The system controller 14 appropriately performs a required control operation based on the input operation information. In particular, in the present embodiment, it is assumed that the operation unit 15 is provided with a mode switching key for performing switching setting between the normal mode and the vibration proof mode described above.

2. PLL / CLV Servo Circuit (2-a. Configuration of PLL / CLV Servo Circuit) FIG.
FIG. 2 is a block diagram illustrating a configuration example of a PLL / CLV servo circuit 25 in the signal processing circuit 7 illustrated in FIG. 1. As shown in the figure, the PLL / CLV servo circuit 25 includes a CLV servo circuit system 25A and a PLL circuit system 25B. CL
In the V servo circuit system 25A, for example, an EFM signal divided by the divider 30 based on a predetermined dividing ratio,
The oscillation frequency output from the crystal oscillator 31 (for example, 16.9
34 MHz) is divided by the frequency divider 32 into a frequency signal FS.
The data is input to the LV speed counter 33. Here, the frequency signal F output from the frequency divider 32
S is represented by FS = n × RFCK / 64. RFCK is a lead frame clock, which is a 7.35 KHz frequency signal based on a crystal system. The variable n indicates a double speed based on a speed at which the disk 1 is driven at a CLV at a normal speed. Therefore, if the disk 1 is driven at CLV at 1 × speed, n = 1, so that the frequency signal FS becomes FS = 1 × 7350/64 = 1114.84375 Hz, which is almost 115 Hz. Become. This is a relatively long cycle of about 9 ms in terms of time.

The CLV speed counter 33 counts the number of edges of the input EFM signal using, for example, the frequency signal FS as a sampling cycle. In the present embodiment, the frequency value of the EFM signal that can be detected based on the information on the number of edges of the EFM signal obtained for each cycle of the frequency signal FS is treated as CLV speed information, and the measurement result is output. The measurement output of the CLV speed counter 33 is supplied to the subtractor 34 and the PLL target variable circuit 39 on the side of the PLL circuit system 25A. In the subtractor 34, C
By subtracting the measurement output of the CLV speed counter 33 from the CLV target value output from the LV target setting circuit 35, the speed error signal C which is error information of the current CLV speed error with respect to the target CLV speed is obtained.
Obtain LV-S. In this embodiment, when the PLL circuit is unlocked due to a servo drop or a long-term loss of a signal during start-up of the spindle motor 2 or during reproduction, a “CLV scan” for pulling the PLL circuit into the capture range is performed. Mode "is set. And
In the CLV scan mode in the normal mode,
In the CLV target setting circuit 35, the CLV target value is varied so as to be swept in a range corresponding to a frequency range that the EFM signal can take as described later. In the vibration mode, the normal CLV
A CLV target value with a predetermined fixed value is set regardless of the servo control mode and the CLV scan mode. This control is performed for the control signal SC1 supplied from the system controller 14.

The speed error signal CLV-S output from the subtractor 34 is output to the adder 36. This adder 3
The other input of 6 receives a phase error signal CLV-P (terminal T / L side) or a fixed value (terminal T / UL side) by '0' via a switch SW1. In this case, the switch SW1 is configured such that the terminal Tout is alternatively connected to either the terminal T • L or the terminal T • UL, and in the normal mode,
The switching state is controlled by a lock signal S.LOCK output from the system controller 14 shown in FIG. The lock signal S • LOCK is set to PL as described above.
The signal indicates whether or not the L circuit system is locked. Here, it is assumed that the signal is at the H level when the PLL circuit system is locked, and is at the L level when the PLL circuit system is not locked.

The switch SW1 outputs the lock signal S
・ If LOCK is at H level, terminal Tout is connected to terminal T
The terminal Tout is connected to the terminal T.UL if the terminal is at the L level. Therefore, the adder 36
, The phase error signal CLV-P is supplied when the PLL circuit is locked, and a fixed value of '0' is supplied when the PLL circuit is not locked. . However, the mode switch signal S · NW corresponding to the normal / wide mode output from the system controller 14 is also input to the switch SW1. When the mode switching signal S · NW corresponds to the wide mode, the lock signal S ·
LOCK is invalidated for switching control of the switch SW1, and the switch SW1 is fixed to the terminal T • UL. That is, regardless of whether the PLL circuit is locked or not, a fixed value of “0” is constantly set to the switch SW.
1 will be output.

The phase error signal CLV-P is a signal obtained by comparing the phase of the oscillation frequency of the voltage controlled oscillator (VCO) 44 of the PLL circuit system 25B with the reference frequency signal of the crystal system, for example. , CL
This is handled as rotation phase error information in the V servo.

The output of the adder 36 is passed through a low boost circuit 37 formed by combining, for example, a digital low-pass filter and a bypass circuit to extract low-frequency components, and is supplied to a D / A converter 38. You. The D / A converter 38 converts the output of the low boost circuit 37 as a digital signal into an analog value and outputs the analog value as a CLV servo control signal to the motor driver 13.
(See FIG. 1). The motor driver 13 supplies a motor drive signal generated based on the supplied CLV servo control signal to the spindle motor 2, whereby the spindle motor 2 changes its rotation speed according to the CLV servo control signal. It will be variably controlled.

Further, the PLL circuit 25B includes a voltage controlled oscillator (VCO) 44 for generating a frequency signal PLCK as a reproduction clock. This VCO4
The oscillation frequency of No. 4 is variably controlled according to the output of the adder 43 described later. In this figure, for convenience, V
Although it is assumed that the frequency signal PLCK is directly output from the CO 44, a frequency obtained by dividing the oscillation frequency of the VCO 44 by 1/2 is used as the frequency signal PLCK.
For example, when the PLL circuit is locked while rotating the disk at 1 × speed, the frequency signal P
LCK = 4.3218 MHz.

Analog PCO circuit 4 as phase comparator
1, the reproduction clock signal PLCK for the EFM signal
And outputs the detection output to the filter 42. The filter 42 filters the detection output of the analog PCO circuit 41 and outputs it as an error control signal SE for controlling the oscillation frequency of the VCO 44. This error control signal SE is supplied to the adder 43 via the switch SW4.

The switch SW4 is on / off controlled by a training signal S.TRN output from the system controller 14. In the case of the present embodiment, in the normal mode, for example, when the disk rotation is started or when the disk read signal is lost, there is a state where the EFM signal is not input to the PLL circuit for a long time. When such a state is detected, a training mode for maintaining the oscillation frequency of the VCO 44 at the center frequency is set as the operation of the PLL circuit. Or,
The training mode can be set by a predetermined manual operation. The training signal S • TRN
Is a signal output when the training mode is set, and the switch SW4 is turned off in the training mode and turned on in a normal operation other than the training mode by the training signal S · TRN. Is controlled. That is, in the training mode, the signal component based on the detection output of the analog PCO circuit 41 is not used for controlling the oscillation frequency of the VCO 44. Although a detailed description is omitted here, in a training mode, an FCO counter 45 described later is used.
An error signal is obtained by subtracting the measured output of the VCO 44 from the PLL target value output from the PLL target fixed value register 40, and the oscillation frequency of the VCO 44 is controlled by a control signal obtained by integrating the error signal by the integration circuit 48. As a result, an operation that converges so that the oscillation frequency of the VCO 44 is maintained at the required center frequency is obtained.

The basic configuration of the PLL circuit 25B is as follows.
It is formed by a loop of the analog PCO circuit 41 → filter 42 → (switch SW4 → adder 43) → VCO 44. In addition to this, an FCO (Frequency Compar
ator Output) A circuit for automatically adjusting the center frequency of the VCO 44 having a counter 45 and a PCI (Phase Compara
(Tor Integration) circuit 50 to provide a wide lock circuit system for expanding the lock range of the PLL circuit. In the above automatic adjustment circuit system, FC
By making the PLL target value to be compared with the measurement output of the O counter 45 variable, the capture range of the PLL circuit can be expanded.

In the present embodiment, the above-described circuit operation for expanding the capture range and the lock range is performed in the anti-vibration mode. Therefore, hereinafter, the PLL / CLV servo circuit 2 in the anti-vibration mode is used.
The operation mode 5 is also referred to as a “wide mode”.

The FCO counter 45 sets the frequency signal P
By counting LCK / 36, the frequency signal P
Measure the frequency of LCK. The measurement output of the FCO counter 45 is supplied to a subtractor 46. The subtractor 46 subtracts the measurement output of the FCO counter 45 from the PLL target value input via the switch SW2. P
The LL target value is a target value of the frequency of the frequency signal PLCK for converging to the center frequency to be set in the VCO 44. Therefore, the subtractor 46 provides error information of the current frequency signal PLCK. Will be.

The switch SW2 has a terminal TW or a terminal TN connected to the terminal Tout, and the connection is switched by a mode switching signal corresponding to the normal / wide mode supplied from the system controller 14. It is controlled by S · NW. Mode switching signal SN
As W, the terminal Tout is connected to the terminal TN in the case of the normal mode, and the terminal TT in the case of the wide mode.
Connected to W. Here, the terminal TN of the switch SW2
Is connected to a PLL target fixed value register 40 in which a predetermined PLL target value is set as a fixed value. The output of the PLL target variable circuit 39 is supplied to terminals T and W. In the PLL target variable circuit 39,
Speed information signal CL output from CLV speed counter 33
VS is varied and output within a predetermined range as described later. The variable control of the value of the speed information signal CLV-S is performed by a control signal SC2 output from the system controller 14.

The error information output from the subtractor 46 is supplied to the terminal T.UL of the switch SW3 via the amplifier 47. Here, as in the case of the switch SW1, the switch T3 is connected to the terminal Tout to the terminal TL when the lock signal S.LOCK is at the H level (the PLL circuit is in a locked state), and to the L level (the PLL circuit is locked) when the lock signal S.LOCK is at the H level. In the state (not performed), the terminal Tout is connected to the terminal T • UL. Note that a detection output of a PCI circuit 50 described later is supplied to the terminal T • UL via the amplifier 51 and the switch SW5.

The integrating circuit 48 is connected to the terminal T of the switch SW3.
The information value output from out is integrated, and the integrated output is output to the D / A converter 49. D
The / A converter 49 converts an information value from the terminal Tout as digital information into an information signal based on an analog signal and outputs the information signal to the adder 43. In the adder 43,
Output of D / A converter 49 and analog PCO circuit 41
The phase error signal supplied from the VCO 44 is added, and the added signal is output as a control voltage for controlling the oscillation frequency of the VCO 44.

A PCI (Phase Comparator Integration) circuit 50 is a phase information detecting circuit formed by a digital circuit, and detects and outputs a low-frequency component of a phase error of the frequency signal PLCK with respect to the input EFM signal. By the way, for example, the analog PCO circuit 41 is an analog circuit and the PCI circuit 50 is a digital circuit, so that an error occurs in both phase detection outputs. By providing an offset value corresponding to the error to the detection output of the PCI circuit 50, the error between the two is eliminated. This PC
The output of the I circuit 50 is E in the range where the phase is locked.
This can be regarded as information indicating the frequency difference between the FM signal and the frequency signal PLCK. The output signal of the PCI circuit 50 is supplied to the terminal TL of the switch SW3 via the amplifier 51 and the switch SW5. Here, assuming that the output signal of the PCI circuit 50 is input to the integrating circuit 48 via the switch SW5 → the switch SW3, the integrated value output from the integrating circuit 48 is converted into an analog signal by the D / A converter 49. Then, the phase error signal S · PC is output. An example of the internal configuration of the PCI circuit 50 will be described later.

(2-b. Configuration of CLV Target Setting Circuit) Subsequently, C provided in the CLV servo circuit system 25A
The configuration of the LV target setting circuit 35 will be described.
In the CLV scan mode in the normal mode, the V of the PLL circuit system 25B is controlled by the center frequency automatic adjustment mode.
Assuming that the CO44 operates so as to be fixed at the center frequency (PLCK = 4.3218 MHz), in the CLV target setting circuit 35 of the CLV servo circuit system 25A, in the CLV scan mode, the CLV target is set in accordance with the control signal SC1. The value is varied so as to sweep in a predetermined range. This makes it possible to perform CLV control so that the PLL circuit is locked without using the rough servo control as in the related art.

Here, a method of setting the sweep range of the target value set in the CLV target setting circuit 35 will be described. The CLV target value is compared with CLV speed information detected by the CLV speed counter 33. As described with reference to FIG. 1, the CLV speed information detected by the CLV speed counter 33 includes the lead frame clock RFCK. This is frequency information of the EFM signal obtained based on counting the number of edges of the EFM signal using / 64 as a sample clock. Therefore, the possible values of the CLV target value are EFM
It is necessary to correspond to the frequency that the signal can assume. However, the frequency of the EFM signal changes within a certain range according to the state of the code string having the inversion interval of 3T to 11T. Therefore, in the present embodiment, the maximum value and the minimum value of the CLV target value to be changed are determined as follows.

Here, FIG. 11, FIG. 12, FIG. 13, FIG.
Shows 256 EFM words (14 bits) that are EFM-encoded corresponding to each of the original 8-bit data from 0 to FF. That is, it is an EFM conversion table. This EFM word is a pulse inversion signal of the so-called NRZI system. Therefore, the position of "1" is the pulse inversion position for each EFM word. Each figure shows the EFM word and the number of pulse inversions of the EFM word (that is, the number of “1”).

This EFM word is selected from 256 patterns of 16384 (2 to the 14th power) patterns that are possible with 14 bits so as to correspond to 8-bit data. In particular, "1" and "1" , The condition that two or more “0” s are included between the two is satisfied, and the minimum reversal interval is 3T as the reversal interval (the interval between “1” and “1”).
The maximum inversion interval is 11T.

Here, FIG. 11, FIG. 12, FIG. 13, FIG.
The total number of inversions in one word shown for each EFM word is as follows. EFM word with one reversal: 4 words EFM word with two reversals: 56 words EFM word with three reversals: 120 words EFM word with four reversals: 70 words EFM word with five reversals: 6 words

From this, the average number of inversions within one word is (4 × 1 + 56 × 2 + 120 × 3 + 70 × 4 + 6 × 5)
/ 256 = 786/256, which is almost three times more.

As shown in FIG. 10, the EFM frame has a sync pattern of 11T + 11T + 2T (that is, three inversions) and a margin bit of 3 bits arranged between each 14-bit EFM word. Therefore,
Assuming that the data to be EFM encoded is a random number,
If the inversion occurrence probability at each margin bit is と, the average number of inversions in one EFM frame is (786/256) × 33 + (）) × 34 + 3 ≒ 1.
21.32 [times]. Note that “33” is the number of words as main data, parity, and subcode, “34” is the number of margin bits, and “3” is the number of inversions of the sync pattern. (See Fig. 10)

For this reason, the average frequency of the EFM signal is (121.32 × 7.35 [KHz]) = 891.17.
02 [KHz]. In the format according to the normal CD system, the PCM audio data subjected to the EFM modulation is not completely random numbers, so that the average frequency of the EFM signal may be somewhat unreliable. Value. Therefore, the above E
Based on 891.1702 which is the average frequency of the FM signal, in the present embodiment, 900K is set as the maximum value of the CLV target value in consideration of a certain margin on the higher frequency side. .

For example, when a silent pattern or a random pattern of -60 dB or less is included in the EFM signal, the average number of bits per sample period is 2.27 bits, and the frequency of the EFM signal at this time is 790K.
Hz, which is regarded as the lowest theoretically possible value.

Here, for example, in order to have a certain margin as the CLV target value, consideration is given to the fact that two-edge (twice-inversion) patterns (twice-inversion) are concentrated on the smaller numerical value in the EFM conversion. Then, assuming that the number of inversions of the symbol of each main data (see FIG. 10) is about 2.85 on average, but the number of inversions of each symbol of the main data is two, the EFM
It has been found that the frequency of the signal is about 750 KHz. Therefore, the center of the frequency of the EFM signal is approximately 9
It can be seen as being in the range of 00 KHz to 750 KHz. Therefore, the CLV speed is 900
It is assumed that there is a center speed between K and 750K. As described above, in the present embodiment, the maximum value of the sweep range of the CLV target value set in the CLV target setting circuit 35 is 9
00K and the minimum value is set to 750K.

When a CLV target variable setting circuit that functions in the normal mode is configured by hardware as the CLV target setting circuit 35, for example, FIG.
Can be configured as shown in the block diagram of FIG.
Although FIG. 3 also shows the configuration of the CLV servo circuit system 25A shown in FIG. 2, this configuration is the same as that of FIG. I do.

FIG. 3 shows a CLV target setting circuit 35.
The configuration of the CLV target variable setting circuit 35A that is operated only in the normal mode is shown. In the CLV target variable setting circuit 35A, the counter unit 60 counts up and down with respect to the CLV target value. Further, the selector 61 sets the maximum value (900K) of the CLV target value held in the minimum value register 62 and the maximum value register 63, respectively.
And the minimum value (750K) is selected and output. The set / reset unit 64 sets the counter unit 60 when the count value of the counter unit 60 reaches the maximum value (900K), and sets the count value to the minimum value (750K) or when the load signal LD When the edge is detected, the counter unit 60 performs a reset operation. A set output terminal of the set / reset unit 64 receives a detection output of a maximum value detection unit 65 that detects that the count value (CLV target value) of the counter unit 60 has reached a maximum value. . In addition, for the reset input terminal, a detection output of a minimum value detection unit 66 for detecting that the count value of the counter unit 60 has reached a minimum value, and a detection output of an edge detection circuit 67 for detecting an edge of the load signal. Is input to the OR gate 68 to which the OR is input. Here, the control signal SC1 supplied to the CLV target variable setting circuit 35A is a load signal LD and a lock signal S • LOCK.

For example, if the load signal LD is supplied from the system controller 14 to the counter unit 60, the counter unit 60 loads the initial count value and starts the counting operation. The initial value here is the maximum value (900
K) and the minimum value (750K), an appropriate value may be arbitrarily set. For example, when the maximum value is set as the initial value, the CLV target value of 900K is loaded and the minimum value is set. A down count is started with a certain 750K as a target value. This count timing is, for example, R
It is performed at a timing synchronized with the frequency signal FS by FCK / 64. That is, although not shown here, for example, the frequency signal FS is supplied as a timing clock for the counter unit 60 to perform counting.
Here, assuming that the down-counting operation by the counter unit 60 is continued to the minimum value (750K), the minimum value detection unit 66 outputs a detection signal that detects that the CLV target value has reached the minimum value, A reset signal is output from the reset unit 64. As a result, the counter unit 60 switches to the operation of performing up-counting with the maximum value (900K) as the count target value. It should be noted that the reset is also performed depending on the timing at which the inversion of the load signal is obtained, and the count is switched to the up-count.

If the up-counting operation of the counter unit 60 is continued up to the maximum value (900K), the maximum value detection unit 65 outputs a detection signal indicating that the CLV target value has reached the maximum value. As a result, a set signal is output from the set / reset unit 64, whereby the counter unit 60 switches to an operation of performing down-counting with the minimum value (750K) as the count target value. The counter section 60 operates until the lock signal S · LOCK (output from the system controller 14) at the H level is input to the enable inversion input terminal, that is, until the PLL circuit is locked. In this way, the CLV target value is varied in the range from the maximum value to the minimum value held in the minimum value register 62 and the maximum value register 63. When the PLL circuit is locked and the H-level lock signal S · LOCK is input to the enable inversion input terminal, the counter unit 60 stops the counting operation and the count value (CLV) at this time. (Target value). The above operation is performed in the CLV scan mode in the normal mode described later.

In the above configuration, the counter section 60
Switching between up count and down count of EF
It is also conceivable to perform the measurement based on the measurement result of the M pit length. For example, an EFM pit length measuring circuit (not shown) measures a pit length of a pattern of 11T (maximum inversion interval), and based on a comparison result of the measurement result with a required reference value, a mode of up-counting and down-counting of the counter unit 60. Switching can be performed.

(2-c. Configuration of PCI Circuit) Next, an example of the internal configuration of the PCI circuit 50 provided as the wide lock circuit system of the PLL circuit system 25B and its operation will be described with reference to FIGS. I do. FIG. 4 is a block diagram illustrating a configuration example of the PCI circuit 50. PCI circuit 50
Is input to the clock terminal of the flip-flop 70, is inverted via the inverter 71, and is input to the clock terminal of the flip-flop 72. These flip-flops 70 and 72 have VC
Frequency signal PLCK obtained by dividing the O44 oscillation frequency by ２
Is input to the data input terminal. Accordingly, the flip-flop 70 samples the frequency signal PLCK at the time when the rising edge of the EFM signal is obtained, and the flip-flop 72 samples the frequency signal PLCK at the time when the falling edge of the EFM signal is obtained. . The output of the flip-flop 70 is supplied to the terminal T1 of the switch 73, and the output of the flip-flop 72 is
2 is supplied. The switch 73 connects the terminal Tout to the terminal T1 when the EFM signal is at the H level, and connects the terminal Tout to the terminal T2 when the EFM signal is at the L level.
Are connected. Therefore, the terminal Tout
From the output of the flip-flop 70 when the EFM signal is at the H level (PL at the rising edge of the EFM signal).
CK sample data), and when the signal is at the L level, the output of the flip-flop 72 (PLCK sample data at the time of falling of the EFM signal) is obtained. The signal output from the terminal Tout is input to the up / down input of the up / down counter 77.

The exclusive OR gate 74 inputs the frequency signal PLCK and the frequency signal 1 / 2PLCK obtained by dividing the frequency signal PLCK by 、, and supplies the output to one input of the AND gate 76. . The edge detection circuit 75 outputs a single H-level pulse when the rising / falling edge of the EFM signal is detected, and supplies the pulse to the other input of the AND gate 76. The output of the AND gate 76 is input to the enable terminal of the up / down counter 77.

The up / down counter 77 counts up or down based on the output of the terminal Tout supplied to the up / down input when the H level is input to the enable terminal. The up-down counter 77 receives, for example, a crystal clock of 8 MHz as an operation clock. The reset terminal has a lead frame clock RFCK.
Is input, and the count value is cleared every cycle of the read frame clock RFCK, and the value held in the PCI initial value register 78 is loaded as the count initial value.

For example, since the PCI circuit 50 is formed of a digital circuit with respect to the analog PCO circuit 41, the phase information detected by the two circuits will be shifted if they are not used. Assuming that the output of the analog PCO circuit 41 (S ·
PC) and a signal (S) obtained from the output of the PCI circuit 50 side.
E) is added by the adder 43 to generate a control signal, and when this control signal is input to the VCO 44, a variable control operation of an appropriate oscillation frequency cannot be obtained. Therefore, in this embodiment, the analog PCO is used as the count initial value held in the PCI initial value register 78.
The value corresponding to the error of the detection output of the PCI circuit 50 with respect to the detection output of the circuit 41 is set. As a result, the error in the phase detection output between the analog PCO circuit 41 and the PCI circuit 50 is cancelled.

The PCI register 79 stores an up / down counter 77 every cycle of the read frame clock RFCK.
Is latched, and the latched value is output to the subsequent amplifier 51 (see FIG. 2) via the output terminal 80. That is, the value of the detection output of the PCI circuit 50 can be changed every cycle of the lead frame clock RFCK.

FIG. 5 is a timing chart showing the operation of the PCI circuit 50 having the above configuration. Here, PCI
If an EFM signal as shown in FIG. 5F is input to the circuit 50, the frequency signal PLCK obtained at the timing of the rising edge of the EFM signal is supplied from the flip-flop 70 to the terminal T1 of the switch 73. And the frequency signal PLCK obtained at the timing of the falling edge of the EFM signal is input from the flip-flop 72 to the terminal T2 of the switch 73. Then, from the terminal Tout of the switch 73,
While the EFM signal is at the H level, the data of the flip-flop 70 (sampled frequency signal PLCK) is output, and during the L level, the data of the flip-flop 72 is output and input to the up-count input of the up-down counter 77. Will be. Here, the switch 7
3 can be regarded as the instantaneous phase information of the frequency signal PLCK obtained corresponding to the edge timing of the EFM signal.

Assuming that the frequency signal PLCK is input as shown in FIG. 5A, the frequency signal 1 / 2PLCK obtained by dividing the frequency signal PLCK by 例 え ば by a frequency divider (not shown) is obtained as shown in FIG. It is obtained as shown in FIG. Then, the frequency signal PLCK and the frequency signal 1 /
The signal obtained by inputting 2PLCK to the exclusive OR gate 74 is, as shown in FIG.
/ 2PLCK is a waveform whose phase is delayed by 90 °.
Here, for example, based on the time point t1 corresponding to the edge timing of the EFM signal, a section corresponding to ±± PLCK thereof is a section in which the phase of the frequency signal PLCK to be detected is inverted from the original phase. In the output waveform of the exclusive OR gate 74 shown in FIG.
For example, the section having the L level corresponds to the frequency signal PL described above.
This corresponds to a section where the detected phase of CK is inverted from the original phase. That is, as shown as an effective phase in FIG.
The section indicated by the solid line (periods t0 to t2, t3 to t4...) Is valid as the detection phase, whereas the section indicated by the broken line (periods t2 to t3, t4 to t6...) Is invalid as the detection phase. It is said.

In the edge detection circuit 75, FIG.
As shown in (d), a single pulse at H level is output in accordance with the edge timing of the EFM signal. Here, the output of the exclusive OR gate 74 and the output of the edge detection circuit 75 are supplied to the AND gate 76. Is input, the logical product output from the AND gate 76 has a waveform shown in FIG. 5E, and a signal having this waveform is input to the enable terminal of the up / down counter 77. Therefore, in the up / down counter 77, the output waveform of the exclusive OR gate 74 becomes L
In a section corresponding to the level period in which the detection phase of the frequency signal PLCK is inverted from the original phase (a section indicated by a broken line in FIG. 5G), the count operation is not performed, and the phase detection error noise is reduced. , And the signal state (H / H) of the frequency signal PLCK obtained only at the moment of the edge timing of the EFM signal.
L) to perform up-counting or down-counting.

In the timing chart of FIG. 5, the counting operation of the up / down counter 77 is as follows. For example, suppose that the count value before time t1 was '0'. When the time t1 at which the rising edge of the EFM signal has been reached is reached, the up-down counter 77 is in a state where the count operation is possible because the enable input is at the H level. The frequency signal PLCK at this time point t1 is at the L level, and the L level value is input to the up / down input, so that the up / down counter 77 counts down by one step. As a result, the count value becomes “−1” as shown in FIG.

Thereafter, at time t5, a falling edge of the EFM signal is obtained.
Is a period (FIG. 5 (g)) in which the detection phase of the frequency signal PLCK is inverted from the original phase, and therefore, the enable input is set to the L level as shown in FIG. 5 (e). Therefore, the counting operation at this point is not performed,
The count value obtained at the time point t1 is maintained.

Thereafter, the count operation is activated at time t7 when the rising edge of the EFM signal is obtained. At this time, the frequency signal P at the H level at this time is activated.
When the LCK is input to the up / down input, up counting is performed here. As a result, the count value after time t7 becomes '0'. Thereafter, the counting operation is prohibited at the edge timing of the EFM signal at time t8 when the enable input (the AND gate output in FIG. 5E) becomes L level according to the operation up to now, and the next time t
At the EFM signal edge timing at 9, the count operation is performed because the enable input is at the H level. Frequency signal PLC sampled at time t9
Since K is at the H level, the count is up at this time, and the count value is “1”. The counting operation by the up / down counter 77 is performed in this manner, which can be regarded as an operation of holding the instantaneous phase information obtained at the edge timing of the EFM signal as an integral value. That is, the frequency signal PLC which is a clock
The low frequency component of the phase error with respect to the K EFM signal is represented by the count value of the up / down counter 77.

The PCI circuit 50 operates in the wide mode in a state where the PLL circuit is locked, so that
As described later, the lock range of the PLL circuit is expanded. The count value thus obtained (including the offset amount due to the count initial value of the PCI initial value register 78) is fetched into the PCI register at the RFCK cycle as described above, and is reset to the count initial value. Then, the operation described with reference to FIG. 5 is repeated for each RFCK cycle.

As an actual PCI circuit 50 obtained based on the above configuration, for example, a high-speed clock or an A /
There is no particular need to use a D converter or the like, and the scale of the hardware can be configured with 500 gates or less. Therefore, in realizing a wide lock range by the PCI circuit 50, it is possible to reduce the cost and the size of the circuit as compared with a conventional configuration using two PLL circuits. .
In addition, since the PCI circuit 50 is formed by a digital circuit as shown in FIG. 4, even when a process corresponding to an abnormality during operation and a change in loop characteristics are required, it is possible to easily cope with the case.

(2-d. Operation in Normal Mode) Next, the operation in the normal mode of the PLL servo circuit 25 having the configuration described above will be described. The normal mode is a normal reproduction mode in which the CD player is not provided with a vibration damping function as described above. The high-speed writing of the used data and the reading control by the steady speed are not performed.

In the normal mode, P shown in FIG.
In the LL servo circuit 25, the switch SW2 is connected to the terminals TN by the mode switching signal S · NW output from the system controller 14, whereby the PLL held in the PLL target fixed value register 40 is held.
The target fixed value is supplied to the subtractor 46. The switch SW5 is connected to a mode switching signal S ·
By being controlled to be turned off by the NW, the PC
The operation of I circuit 50 is disabled.

At this point, for example, when the spindle motor is started, or when the PLL circuit is unlocked for a predetermined time or more due to dropout due to a servo drop or dust or scratches on the disk 1, the PLL circuit is locked. The mode shifts to the CLV scan mode for performing the reproducing operation. At this stage, since the PLL circuit is not locked, the switches SW1 and SW3 controlled by the lock signal S • LOCK are connected to the terminal To.
ut is controlled to be connected to the terminal T.UL. Therefore, a value of '0' is input as the signal CLV-P to the adder 36 in the CLV servo circuit system 25A, and the PLL circuit system 25B automatically adjusts the VCO center frequency on the FCO counter 45 side. Is valid.

Since the switching state of each switch is controlled as described above, in the initial state in the CLV scan mode, the VC circuit is not connected to the PLL circuit system 25A.
The automatic adjustment mode is set so that O44 becomes the center frequency. That is, since the switch SW4 is turned off, the error control signal SE obtained based on the detection output of the analog PCO circuit 41 is not supplied to the adder 43. Since the terminal T.UL is connected to the terminal Tout in the switch SW3, the output of the automatic adjustment circuit system including the FCO counter 45 is supplied to the VCO 44 via the adder 43. .

At this time, the operation of the PLL circuit system 25B is as follows.
Frequency signal PL obtained based on the oscillation frequency of O44
The frequency value of CK / 36 is measured, and the measurement result is compared with the PLL target fixed value (output of the PLL target fixed value register 40) in the subtractor 46. Then, the output of the subtractor 46 is changed from the amplifier 47 to the switch SW.
3 → integration circuit 48 → supplied as frequency error signal S · FC to adder 43 via D / A converter 49. At this time, if the training mode is set for the sake of simplicity, the output of the analog PCO circuit 41 is not supplied to the adder 43.
CO44 is a frequency error signal S on the FCO counter 45 side.
Only by the loop in which the FC is fed back, the frequency signal PLCK / 36 is controlled so as to approach the PLL target fixed value. As a result, control is performed so that the oscillation frequency of the VCO 44 converges and is fixed so as to be the center frequency (PLCK = 4.3218 MHz) set corresponding to the normal mode. That is, in the CLV scan mode in the normal mode, P
It can be seen that the LL circuit system 25B has the VCO 44 fixed at the center frequency.

On the other hand, the CLV servo circuit system 25A
Then, when the subtractor 34 compares the speed information signal output from the CLV speed counter 33 with the CLV target value output from the CLV target setting circuit 35, the CLV target setting circuit 35 uses the CLV target. The value is made to be variable. That is, as the CLV target setting circuit 35, the CLV described in FIG.
Until the V target variable setting circuit 35A functions and the state in which the PLL circuit is locked (lock signal S · LOCK = H) is obtained, the operation described with reference to FIG.
Set the CLV target value from the maximum value (900K) to the minimum value (7
50K) to be varied. Therefore, the spindle motor 2 sets the frequency of the EFM signal to PL based on the speed error information obtained from the difference between the current CLV speed information (the output of the CLV speed counter 33) and the variable CLV target value.
The rotation speed of the L circuit is controlled so as to come within the pull-in range. At this time, since the switch SW1 is connected to the terminal T.UL, the unnecessary phase error signal CLV-P as a control component is not supplied to the adder 36 in the CLV scan mode.
'0' is supplied as a value.

Here, since the rotation speed of the spindle motor 2 has reached a level corresponding to the pull-in range of the PLL circuit, the frame sync of the EFM signal can be detected. If the LOCK is output, the operation shifts to the "normal operation mode" in which the state in which the PLL circuit is locked is maintained. If the operation shifts to the normal operation mode, the CLV target setting circuit The CLV target value that has been changed in the 35 counter unit 60 is fixed at this time, and is set as a CLV target value used for CLV control in the subsequent normal operation mode. By such an operation, the CLV servo circuit system according to the present embodiment can always obtain one transfer characteristic. When the lock signal S · LOCK is set to the H level, the CLV
In the servo circuit system 25A, the switch SW1 is connected to the terminal TL
To the adder 36, the current phase error signal CLV-P is input to the adder 36, and the current speed error information CL
VS is added. Then, the spindle motor 2 is CLV controlled by a motor drive signal obtained based on the output of the adder 36.

Further, by setting the operation mode to the “normal operation mode”, the lock signal S · L
The switch SW3 is connected to the terminal T.
The terminal is switched from UL to terminal TU. In the normal mode, the switch SW5 is turned off, so that the output of the PCI circuit 50 is turned off, and the input of the integrating circuit 48 is opened. . For this reason, in the normal operation mode, the integrated value (final value in the scan mode) held in the integrating circuit 48 at the time when the PLL circuit is locked is held, and is added to the adder 43 as the frequency error signal S · FC. Is entered.
At this time, except that the training mode is set, the switch SW4 is turned on, so that the analog P
An error control signal SE obtained based on the phase comparison output of the CO circuit 41 is also input to the adder 43. Thus, in the PLL circuit system 25B in the normal operation mode, the oscillation frequency of the VCO 44 is controlled by a voltage value obtained by adding the frequency error signal S · FC to the error control signal S · E. The locked state is maintained.

As described above, in the present embodiment, the CLV speed is set to PL in the CLV scan mode in the normal mode.
As an operation for pulling up to a speed corresponding to the capture range of the L circuit, EFM is performed at a frequency of about 115 Hz (≒ 9 ms) longer than that of the conventional CLV servo circuit system.
The CLV speed is measured by counting the number of edges (number of inversions) of the signal, and the measured value is compared with the CLV target value that is varied between a maximum value and a minimum value set based on the frequency of the EFM signal. The CLV control is executed based on the error. Thus, in the present embodiment, it is possible to shift from CLV pull-in servo to normal CLV control with a very simple circuit scale without separately providing a rough servo circuit system as in the related art. Further, it is not necessary to switch the circuit system between the rough servo control, the access control, and the CLV control at the time of the normal reproduction as in the related art. Control is also realized.

For example, the measuring cycle of the CLV speed is about 136 μs in the related art, whereas it is 9 ms as described above in the present embodiment, and in this case, about 64 μs in this case.
Since the cycle is twice as long, the disturbance of the signal when one sample is lost can be reduced to 1/64. Also,
Transition from the state where the CLV target value is variable,
Since a CLV target value suitable for the normal operation mode is set, the CLV target value can be finally determined to be one while being variable. Therefore, for example, even when the configuration is such that the variable speed reproduction is performed, the PLL / CLV servo circuit of the present embodiment can easily cope with the case.

Further, in the present embodiment, since the measured value of the CLV speed is based on the number of edges of the EFM signal, the system controller 14 monitors this measured value, so that runaway or reversal of the disk may occur. Can be configured to detect these signs at a stage before the occurrence of the error, and control is performed so as to prevent an error state due to runaway or reverse rotation of the disk, which has been difficult in the past, beforehand. It is possible to do. For example, the error of the CLV speed value measured by the CLV speed counter 33 with respect to the CLV target value is within a predetermined range (for example, ± 50%).
Is exceeded, kick control of the spindle motor is executed at a preset kick level, and the CL is controlled.
The control waits until the error of the V speed value with respect to the CLV target value falls within a certain range (for example, within ± 30%). To be.

(2-e. CLV target variable setting operation by software) By the way, C in the normal mode
The configuration for changing the CLV target value in the LV scan mode is realized by software under the control of the system controller 14 instead of the CLV target variable setting circuit 35A as hardware as shown in FIG. Is also possible. In this case, for example, the CLV target variable setting circuit 35
A may be omitted so that the CLV target value generated by the system controller 14 is input to the subtractor 34.

Therefore, as an operation in the CLV scan mode in the normal mode, a configuration in which the CLV target value is varied by software will be described with reference to the flowcharts of FIGS. The processing operations shown in these figures are performed by the system controller 14. In the following processing operation, a case where the spindle motor 2 is started to rotate will be described as an example of a state for shifting to the CLV scan mode.

For example, when the system controller 14 detects that an operation for reproducing a disc has been performed on the operation unit 15 from the stopped state, the system controller 14 proceeds to step S100 shown in FIG. TIM
After resetting E to 0, control is performed in a subsequent step S101 to apply a kick voltage of a predetermined level for forcibly rotating the spindle motor 2 for a predetermined time. That is, an operation called a so-called spindle kick is performed, whereby the spindle motor 2 starts rotating. After the execution of the spindle kick for a predetermined time is completed, for example, the spindle motor 2 is in a state of performing inertial rotation during a standby period until the CLV control is performed.

After the processing in step S101 is completed,
In step S102, a command for turning on the focus servo is output. As a result, the focus servo circuit system including the optical system servo circuit 12 (see FIG. 1) executes the focusing control from the transition from the focus search control to the focus servo loop control. Under this state, the system controller 14 determines whether or not the focus servo control has been properly performed in step S103, and the state in which the servo control by the closed focus servo loop is performed is performed. When it is determined that has become, the process proceeds to step S104. Step S1
In step 04, a command for turning on the tracking servo is output. Accordingly, the tracking servo control is started in the tracking servo circuit system in the optical system servo circuit 12. As a result, a state where signals recorded on the disk 1 can be read by the optical head 3 is obtained.

In step S105, the lock signal S · L
It is determined whether or not the OCK is output at the H level, that is, whether or not the PLL circuit is locked (a state where the frame sync can be properly detected from the EFM signal). Note that, in the processing steps so far, P
If the LL circuit is not locked (lock signal S
If LOCK = L), as described in FIG.
The L circuit system 25B is in a state where its circuit configuration is formed so as to perform an automatic adjustment operation of the VCO center frequency using the circuit system of the FCO counter 45.

In step S105, the rotational speed of the spindle motor 2 rotated by the spindle kick process (S101) is within an appropriate range corresponding to the capture range of the PLL circuit, and the PLL circuit is already locked. If it is determined that the lock signal S · LOCK = H, the process proceeds to step S111, where the time measurement value TIME is reset to “0”, and the process proceeds to step S1.
Proceed to 12. In step S112, a control process for a reproducing operation in accordance with the normal operation mode in a state where the PLL circuit is locked is executed, and the process returns to step S105 every predetermined time to change the state of the PLL circuit. Be monitored. Note that the lock state determination processing of the PLL circuit in step S105 and step S202 described later generates the lock signal S • LOCK according to the signal GFS as described above, and thus is input from, for example, the synchronization detection circuit 26. It is also possible by detecting the state of the signal GFS. Therefore, as long as the PLL circuit is locked, steps S111 → S112 → S1
By the loop processing of 05, the normal operation mode corresponding to these reproduction modes is continued regardless of whether the current mode is the normal mode or the wide mode. If an error condition such as a servo drop or a long-term signal drop occurs due to some disturbance during reproduction or the like and the lock is released, the process proceeds from step S105 to S106.

If it is determined in step S105 that the PLL circuit is not locked, step S1 is executed.
06 → S107 → S105, the PLL circuit returns to the locked state for a predetermined time in this state, and waits for the transition to the normal operation mode. If the rotation speed of the CD player is still inappropriate and the PLL circuit is not locked even after waiting for a predetermined time and it is impossible to shift to the normal operation mode, the process proceeds from step S107 to step S108. It is determined whether the reproduction mode is set to the normal mode or the wide mode. In this mode setting, it is assumed that one of the modes is already selected by the user operating the operation unit 15.

If it is determined in step S108 that the mode is the normal mode, the process proceeds to step S109, which is a CLV scan mode corresponding to the normal mode. The processing routine of step S109 is as described below with reference to FIG. When it is determined that the mode is the wide mode,
The process proceeds to the process for the CLV scan mode in the wide mode in step S110.
Will be described later.

In the routine shown in FIG.
The operation in place of the CLV target variable setting circuit 35A shown in FIG. Here, for the system controller 14, at least the maximum value (900K) and the minimum value (7
50K) is set.

As the processing shown in FIG.
At 201, for example, CL to be input to the subtractor 34
V target value (shown as CLVTG in the figure)
Is set to the maximum value, and in step S202, P
It is determined whether or not the LL circuit is locked.

If it is determined in step S202 that the PLL circuit is locked, step S21
0, if the CLV target value has been variably controlled so far, the counting operation for this is stopped, and after the last CLV target value is held, the process proceeds to step S105 shown in FIG. You. This gives P
As long as the LL circuit is locked, step S11
The normal operation mode is set by the loop processing of 1 → S112 → S105. On the other hand, if it is determined in step S202 that the PLL circuit is not locked, the flow advances to step S203 to determine whether the count mode of the CLV target value is currently the up-count mode. . Step S20
When the process proceeds to step S203 through the processing of 1 → S202, it is assumed that the down-count mode has been set. If it is determined in step S203 that the mode is the up-count mode, the process proceeds to step S20.
The process proceeds to step S4, where the CLV target value is incremented by one step, and then proceeds to step S206. If it is determined that the mode is the down-count mode, the process proceeds to step S206 after decrementing by one step in step S205.

In step S206, the current CL
It is determined whether the V target value is the maximum value. If the CLV target value is the maximum value, the process proceeds to step S207, switches the count mode to the down-count mode, and returns to step S202. To be. On the other hand, if it is determined that the CLV target value has not reached the maximum value, the process proceeds to step S208, and it is determined whether the CLV target value has reached the minimum value. If it is determined that the CLV target value has reached the minimum value, the process proceeds to step S209 to switch to the up-count mode, and thereafter returns to step S202. If a negative result is obtained in step S208, the process returns to step S202 while maintaining the previous count mode. By performing the operation described so far, the C described with reference to FIG.
An operation equivalent to the LV target variable setting circuit 35A is executed as a process of the system controller 14.

In the above-described processing operation, switching between the up-count mode and the down-count mode is performed according to the hardware configuration described with reference to FIG.
The measurement can be performed based on the measurement result of the EFM pit length.

(2-f. Operation in Wide Mode) Next, the operation of the PLL servo circuit 25 in the vibration control mode (at the time of the wide mode) will be described. In the anti-vibration mode, the reading of signals from the disk, the signal processing in the signal processing circuit 7, and the writing of data to the RAM 9 are performed on the RAM 9 at a specific data transfer rate that is basically higher than 1 × speed. Accumulate data,
The reading of data from the RAM 9 is performed at a normal rate corresponding to 1 × speed so that reproduced data is output so as not to be interrupted, thereby obtaining a vibration damping function.
In the present embodiment, in order to further enhance the anti-vibration function, the capture range and the lock range of the PLL circuit are expanded as described below as the operation of the PLL servo circuit 25. The operation is performed as a “wide mode”.

In this case, the read frame clock signal R
For FCK, n times speed (n> 1) with CLV speed
Accordingly, a frequency signal represented by RFCK = n × RFCK is obtained. Also, correspondingly, V
The oscillating frequency of the CO 44 is also n times as high as that in the normal mode. Therefore, the frequency of the signal PLCK in the wide mode is also represented by PLCK = n × PLCK.

The switching state of each switch in the wide mode is such that the switch SW2 is switched to the terminal T • by the mode switching signal S • NW corresponding to the wide mode.
It is switched to W side. Thereby, the PLL circuit system 25
The output of the PLL target variable circuit 39 is input to the B subtractor 46. That is, in the circuit for automatically adjusting the center frequency of the VCO 44 in the PLL circuit system 25B, information on the EFM signal frequency measured by the CLV speed counter 33 is supplied to the subtractor 46 as the PLL target value.

The switch SW5 is controlled to be turned on by a mode switching signal S / NW corresponding to the wide mode, and the output of the PCI circuit 50 is switched to the switch S5.
The terminal T / L of W3 can be supplied. The switching state of the switches SW1 and SW4 controlled by the lock signal S • LOCK is the same as in the normal mode.

In the wide mode, the CLV target setting circuit 3 is provided in the CLV servo circuit system 25A.
From 5, the CLV target value based on the predetermined fixed value is output to the subtractor 34. That is, even during a CLV scan operation described later, the CLV target value is not variably controlled as in the normal mode. Thus, in the wide mode, the CLV servo circuit system 25
In A, the CLV output from the CLV speed counter 33
In order to obtain a convergence state in which the speed information coincides with the CLV target value as the fixed value, the spindle motor 2
Will be controlled. In the state where the PLL circuit is not locked in the wide mode, the position error signal CLV-P having a fixed value of “0” is input to the adder 36.

Assuming that the circuit configuration as described above is formed in the PLL / CLV servo circuit 25, the CL of the CLV servo circuit system 25A in the wide mode is set.
The V scan operation (operation for locking the PLL circuit) will be described.

Here, for example, assuming that the rotation speed of the disk has not reached the fixed value set by the CLV target setting circuit 35 in a state where the PLL circuit is not locked, in the PLL circuit system 25B, , FC
An automatic adjustment operation of the center frequency for controlling the VCO 44 to converge on the center frequency is performed only by the loop in which the frequency error signal S · FC of the O counter 45 is fed back.

However, in the wide mode, as described above, the PLL target value to be compared with the output of the FCO counter 45 in the subtractor 46 is the PLL target variable circuit 3
9 is output. At this time, the PLL target variable circuit 39 receives the frequency value of the EFM signal of the CLV speed counter 33, and sets the output of the FCO counter 45 according to the ratio between the predetermined target value and the CLV target value.
For example, the variable is performed at a cycle of RFCK / 64. The operation of changing the PLL target value will be described later.

As described above, the target PLL target value for the frequency measurement value of the FCO counter 45 is set to the frequency value based on the current EFM signal frequency value.
By controlling the oscillation frequency of the VCO 44 by the frequency error signal S · FC generated based on the LL target value, the VCO 44 can lock the current EFM signal frequency value to the VCO frequency or the D / A converter 49.
And converge so as to be fixed at the lowest frequency determined by the characteristics of the adder 43 and the VCO 44. on the other hand,
As described above, the CLV servo circuit system 25A operates to control the rotational speed of the spindle motor 2 with the CLV target value as a fixed value as a target. At this time, the PLL circuit system 25B performs the automatic adjustment operation of the center frequency of the VCO, and rotates the spindle motor 2 until the PLL circuit is locked (that is, the current EFM signal frequency matches the PLCK cycle). Waiting for speed increase.

The operating state at the time of unlocking can be regarded as, for example, a state in which the oscillation frequency of the VCO 44 is controlled so as to approach the current disk rotational speed. Therefore, for example, the oscillation frequency of the VCO 44 is set to 1
Assuming that the frequency variable range of the frequency signal PLCK obtained by dividing by ２ is 2 MHz to 30 MHz, in this embodiment, the signal PLCK has the lowest frequency 2
When the MHz is obtained, the PLL circuit is locked and the signal can be read. That is, it is possible to follow the PLL circuit from the pull-in stage of the CLV servo. For example,
Conventionally, assuming that the reproduction operation is performed at 2 × speed, the signal PLCK is set to PLL218 at 4.3218 MHz × 2.
Since the circuit is locked for the first time, for example, it takes about 4 seconds before the signal can be read after the rotation of the spindle motor 2 is started. On the other hand, in the present embodiment, a signal can be read in about one second. Further, even when the PLL circuit is re-locked, for example, at the time of a track jump, the above-described CLV scanning operation is performed, so that the disk speed can be converged so as to follow the disk speed at a speed of about 100 times the conventional speed. It becomes possible. This is because in the present embodiment, only the rotation speed of the spindle motor 2 is a variable control element because the PLL target value is fixed.
The operation of the circuit for automatically adjusting the center frequency of the circuit
4 is controlled so as to follow the current speed of the spindle motor 2 corresponding to the EFM signal frequency.

From the state where the PLL circuit is not locked as described above, the state where the EFM signal frequency coincides with the PLCK cycle and the frame sync is properly detected by the synchronization detecting circuit 26 and the PLL circuit is locked. , The lock signal S · LOCK output from the system controller 14 is output at the H level.

As a result, the switch SW3 is connected to the terminals TU
Switching from L to the terminal TL is performed. Further, the switch SW4 is turned on. In addition,
The switch SW1 is connected to the terminal T • UL in the wide mode.
(Fixed value '0' side). For this reason, regarding the CLV control of the spindle motor 2 in the CLV servo circuit system, the speed error signal CL
This is performed based on VS.

In the PLL circuit system 25B, the signal output to the integration circuit 48 via the switch SW3 is switched from the FCO counter 45 side to the PCI circuit 50 side wide lock circuit system. Further, an error control signal SE obtained based on the detection output of the analog PCO circuit 41 is supplied to the adder 43 via the switch SW4.
Will be supplied to When the PLL circuit is locked, the phase error signal S · PC obtained by integrating the detection output of the low frequency component of the phase error of the PCI circuit 50 by the integration circuit 48 corresponds to the frequency error information of the EFM signal with respect to the frequency signal PLCK. I do. Therefore, the switch SW
3 is switched from the FCO counter 45 side to the PCI circuit 50 side system, the final value of the frequency error signal S · FC, which has been supplied from the FCO counter 45 side, and the phase error signal S · PC A state in which the operation is performed in such a manner as to take over is obtained.

After the PLL circuit is locked by the above operation, the phase error signal S.PC obtained via the D / A converter 49 based on the output of the wide lock circuit system on the PCI circuit 50 side, and the analog PCO The oscillation frequency of the VCO 44 is controlled by the voltage value obtained by combining the error control signal SE, which is the detection output of the circuit 41, by the adder 43. At this time, the phase error signal S · PC (D / A converter 49) obtained based on the output of the PCI circuit 50
Output) is V so as to follow the EFM signal frequency.
The detection output (phase comparison result) of the analog PCO circuit 41, which is a source of the error control signal S · E, is a phase high frequency component. Therefore, at this time, the PLL circuit system 25B
In the above, the factors that determine the lock range and the capture range are only the characteristics of the D / A converter 49 and the adder 43 and the frequency variable range of the VCO 44, and consequently the lock range and the capture range are limited by the above-mentioned determination factors. It is possible to expand to within the range.

Here, FIG. 9 shows the PLL described so far.
The operation in the wide mode of the / CLV servo circuit 25 is represented by C
LV control signal (drive output supplied from CLV servo circuit system 25A to motor driver), frequency error signal S
FC / phase error signal S · PC and lock signal S · LO
This is shown in relation to CK. For example, it is assumed that an operation for rotating and starting the spindle motor 2 is started at a time point t0. At this time, since the PLL circuit is not locked, the lock signal S.LOCK is at the L level as shown in FIG. 9C. In this state, the PLL circuit system 2
In 5A, by operating the system on the FCO counter 45 side, the VCO oscillation frequency is controlled by, for example, the frequency error signal S.FC shown in FIG. 9B. Also,
In this initial stage, since the rotation speed of the spindle motor 2 is considerably apart from the CLV target value, a relatively large level CLV control signal is supplied as shown in FIG. Speed up to high speed. After the time point t0, the operation in the CLV scan mode described above is performed, and when the PLL circuit is in a locked state, the lock signal S · LO shown in FIG.
CK changes to H level. As a result, as described above, the PLL circuit system 25A operates so that the system on the FCO counter 45 side is switched from the valid state to the system on the PCI circuit 50 side. And at this time, FIG.
As shown in (b), the signal input to the adder 43 is switched to the phase error signal S · PC so as to take over the final value of the frequency error signal S · FC. Thereafter, as can be seen from the level transition of the CLV control signal in FIG. 9A and the phase error signal S.PC in FIG. 9B, the CLV control is performed so as to match the CLV target value of the CLV servo circuit system 25A. Is performed, and the PLL circuit system 25B
In this case, the oscillation frequency of the VCO 44 is controlled so as to be the center frequency in the steady state while maintaining the locked state.

For example, the PLL circuit system 25B without the wide lock system by the PCI circuit 50 of the present embodiment.
Considering the operation in the wide mode, the pull-in control operation is performed based on the frequency error signal S · FC obtained by the system on the FCO counter 45 side. Is achieved. However, the output (SE) of the analog PCO circuit 41 and the detection output (SE) of the FCO counter 45 side
Since the phase is different from that of the PLL circuit, the PLL circuit is locked when the PCI circuit 50 is not provided.
The final value of the frequency error signal S · FC, which is the detection output of the FCO counter 45, at the time when the PLL circuit is locked is held, and the frequency error signal S · F as the held value is held.
The only available method is to add C as an offset component to the error control signal S · E of the analog PCO circuit 41. At this time, the frequency error signal S · FC has a fixed value and does not change following the EFM signal frequency, so that it was difficult to expand the lock range. On the other hand, in the present embodiment, as described above, the output of the analog PCO circuit 41 is
By adding the output obtained by the operation of
The center frequency of the VCO 44 can be variably controlled so as to follow the EFM signal frequency.

Subsequently, as the processing operation of the system controller 14 in the above-mentioned wide mode, mainly the PL
A variable control process of the PLL target value for the L target variable circuit 39 will be described with reference to FIGS. Even in the wide mode, for example, after the start of rotation of the spindle motor 2 or immediately after the PLL circuit is unlocked due to a servo drop or a signal dropout, the processing operation shown in FIG. The processing up to S108 is executed. Since the processing operation shown in FIG. 6 has already been described as the operation in the normal mode, the description is omitted here. However, in the wide mode, since the CLV target value is fixed, the CLV servo circuit system is in a state where the CLV control is performed so as to converge on the CLV target value.

At step S108 in FIG.
If it is determined that the current mode is the wide mode, the process proceeds to step S110, and processing as the CLV scan mode in the wide mode is executed. The CLV scan processing as step S110 is as shown in the processing routine of FIG. In this processing routine, the system controller 14 outputs the control signal SC2 to control the PLL target variable circuit 39,
As described below, the PLL target variable circuit 3
9, the PLL target value to be output is varied.

As the processing in the CLV scan mode shown in FIG. 8, first, in step S301, the PLL target value (shown as PLLTG in the figure) output from the PLL target variable circuit 39 is set to the maximum value. The maximum value of the PLL target value is, for example, PL
Assuming that the output value of the CLV speed counter 33 input to the L target variable circuit 39 is SDT, this is set by setting a maximum value for a coefficient k for multiplying this value SDT. Further, as the maximum value of the PLL target value, a value corresponding to 900k which is the maximum value of the variable range of the CLV target value described above is set.
Similarly, the minimum value of the PLL target value is set to 750k, which is the minimum value of the variable range of the CLV target value.

Thereafter, in step S302, the system controller 14 determines whether or not the PLL circuit is locked. If it is determined in step S302 that the PLL circuit is locked, the process proceeds to step S105 in FIG. This gives P
As long as the LL circuit is locked, step S11
The normal operation mode is executed by the loop processing of 1 → S112 → S105. In this case, since the mode is the wide mode, when the process proceeds to step S105,
As described above, in the PLL circuit system 25B, switching from the system on the side of the FCO counter 45 to the wide-lock circuit of the PCI circuit 50 is performed.

If it is determined in step S302 that the PLL circuit is not locked, the flow advances to step S303 to determine whether the PLL target value count mode is currently set to the up-count mode. . However, steps S301 → S30
It is assumed that the down-count mode has been set in the initial stage in which the process proceeds to step S303 after the process of step S2. If it is determined in step S303 that the mode is the up-count mode, the process proceeds to step S304 to perform an up-count operation. In this up-count operation, for example, as shown in the figure, first, the coefficient k used for the variable PLL target value calculation is incremented by one predetermined step in step S304. Then, in the next step S306, the output value SDT of the CLV speed counter 33 is multiplied using the coefficient k obtained in step S305. That is, an up-count is performed by executing a process of updating the PLL target value according to PLLTG = SDT × k. Note that the counting operation at this time is such that the PLL target value is equal to C described above.
750K to 900K, which is the variable range of the LV target value
It is sufficient that the value is increased or decreased for each appropriate step value between the maximum value and the minimum value set corresponding to
304 → S306, or step S described next
It is not limited to the processing operation of 305 → S306. For example, it is conceivable that a weighting operation is performed each time the count processing is performed using each coefficient for up-counting and down-counting that is appropriately set with respect to the current PLL target value.

If it is determined in step S303 that the current mode is the down-count mode, in step S305, the coefficient k is decremented by one step by a predetermined value, and the flow advances to step S306.
The output value SD of the CLV speed counter 33 is calculated by the coefficient k.
By multiplying by T, the PLL target value is down-counted.

In step S307, the current PL
It is determined whether or not the L target value is the maximum value. If the PLL target value is the maximum value, the process proceeds to step S307 to switch the count mode to the down-count mode, and returns to step S302. . On the other hand, if it is determined that the PLL target value has not reached the maximum value, the process proceeds to step S308, and it is determined whether the PLL target value has reached the minimum value. Here, when it is determined that the PLL target value has reached the minimum value, the process proceeds to step S309 to switch to the up-count mode, and the process returns to step S302. Step S3
If a negative result is obtained in step 08, the process returns to step S302 while maintaining the count mode. In this manner, in the CLV scan mode in the wide mode, the CLV target value is fixed, whereas the scan is performed by changing the PLL target value. It is possible to make a quick transition to the output value SDT by a lockable state.

In this case as well, the switching between the up-count mode and the down-count mode for the coefficient k is performed based on the measurement result of the EFM pit length as in the case of the sweep of the CLV target value described above. Can be configured.

As described above, since the lock range and the capture range of the PLL circuit in the wide mode are expanded, the vibration resistance against the rotational disturbance is ± 4 frames in the conventional system. On the other hand, the CD player according to the present embodiment uses a 4 Mbyte DRAM
When used as the AM9, the frame becomes ± 35000 EFM frames in the wide mode, and has 9000 times the strength of the conventional one unless the PLL circuit is unlocked. The lock range of the PLL circuit is limited to a lock range of about ± 1 MHz, whereas a lock range of about ± 7 MHz is obtained in the present embodiment. It is possible to cope with seven times the disturbance intensity. Further, in the present embodiment, the processing in the signal processing circuit 7 is a signal PLC obtained by dividing the oscillation frequency of the VCO 44 by half.
A frequency signal based on K is used as a clock. From this, not only the EFM decoding circuit 22 but also the error correction /
The deinterleave processing circuit 23 also operates by the signal PLCK. The time axis correction of the data is performed by controlling the writing and reading of the RAM 9 of the memory controller 8. Therefore, a frame jitter margin at the time of error correction becomes unnecessary. As a result, it is possible to design a PLL / CLV servo circuit without considering the frame jitter margin while using the minimum system configuration using the RAM 24 having a capacity of, for example, about 16 Kbits. That is, about 2
The required CLV servo band of about 0 Hz is 1 Hz
It is possible to set up to about CLV
Power consumption in the servo circuit system can be reduced.

(2-g. Variable Speed Reproduction Operation) In the above description, the CLV target value output from the CLV target setting circuit 35 in the wide mode is a fixed value corresponding to the required CLV speed. The description has been made on the assumption that
By changing the CLV target value output from the CLV target setting circuit 35 in a state where the LL circuit system 25B is operating in the above-described wide mode, it is possible to perform so-called variable speed reproduction. Becomes In other words, the PLL circuit system 25B sets the CLV target value of the CLV target setting circuit 35 in a state where the lock range is expanded (locked state) by the operation in the wide mode described above. The value is changed to a value corresponding to the required CLV speed.

As described above, the lock range obtained by the wide mode operation of the present embodiment is guaranteed within the range according to the characteristics of the D / A converter 49 and the adder 43 and the frequency variable range of the VCO 44. Therefore, if the PLL circuit system 25B is in a state of being wide locked by the operation in the wide mode, the CLV target setting circuit 3
Even if the CLV target value of 5 is changed and set, the CLV servo circuit system 25A converges to obtain the CLV speed corresponding to the changed target CLV target value, while the PLL circuit system 25B is locked. Is maintained, and a state in which a signal can be read can be obtained. That is, the reproduction speed can be varied without stopping the reading operation during the signal reading. However, CLV
If the variable step amount until the target value is brought to the target value is large, it exceeds the lock range of the analog PCO circuit 41, so that the PLL circuit system 25B is unlocked. For this reason, the variable step amount of the CLV target value needs to be set so as not to lose the lock. In the case of this embodiment, 25
You get a maximum step size of percent, but in practice,
The result obtained was that the concentration should be set to 2% or less per one step. The variable time interval of the step is C
The following speed of the disk rotation speed control in the LV servo circuit system 25A and the signal G input from the synchronization detection circuit 26
What is necessary is just to set in consideration of preventing FS from falling.

For example, in the case of a CD, an audio reproduction signal obtained by variable speed reproduction has a variable pitch (pitch) and reproduction speed by a variable ratio with respect to a reference speed. Therefore, for example, a reproduced signal obtained by variable speed reproduction can be used for a so-called key transpose function such as karaoke. However, when using the key transpose function of karaoke, the playback speed must be the playback speed corresponding to the reference speed playback, but the pitch is maintained after being obtained by variable speed playback. Various techniques for returning the speed to a speed corresponding to the reference speed have been previously proposed by the present applicant, for example, and an appropriate technology may be selected from these technologies and employed.

The configuration for realizing the operation in the wide mode described as the above embodiment can be applied to, for example, a reproducing apparatus in which the wide mode is not set, as long as it is compatible with double-speed reproduction. In the above embodiment, a CD player is taken as an example of a playback device. However, the present invention can be applied to, for example, a playback device corresponding to other disk media in which disk rotation control is performed by a CLV. The recording data is not limited to the EFM signal. Naturally, the present invention can be effectively applied even if it is a run-length limited code according to another method.

[0137]

As described above, according to the present invention, in order to expand the lock range of the PLL circuit, the phase error of the clock and the run-length limited code detected by the phase information detection circuit is reduced based on the low-frequency component. By performing control so that the center frequency of the VCO is determined so as to follow the EFM signal frequency corresponding to the disk rotation speed, for example, one system can be used without employing a two-stage PLL circuit configuration as in the related art. By using the PLL circuit, the lock range can be expanded. As a result, the circuit scale of the PLL circuit provided with at least the wide-lock function can be smaller than that of the conventional PLL circuit, and the circuit size and cost can be reduced accordingly. If the configuration of the phase information detection circuit according to the present invention is adopted, it is possible to form a circuit on a very small scale, which also promotes downsizing and cost reduction as a PLL circuit capable of wide locking. Will be done. Then, in the phase information detection circuit, at the timing when the detection phase of the clock has the opposite polarity, this phase information is not taken in as detection information, and an offset for canceling a deviation of the detection phase from the analog phase comparator is set. By providing the detection output, a stable operation can be obtained.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration example of a playback device according to an embodiment of the present invention.

FIG. 2 is a block diagram illustrating a configuration example of a PLL / CLV servo circuit system.

FIG. 3 is a block diagram illustrating a configuration example of a CLV target variable setting circuit.

FIG. 4 is a block diagram illustrating an example of an internal configuration of a PCI circuit.

FIG. 5 is a timing chart showing an operation of the PCI circuit shown in FIG.

FIG. 6 is a flowchart illustrating a processing operation of a system controller associated with CLV control.

FIG. 7 is a flowchart showing a processing operation in a normal mode as a processing operation of the system controller accompanying the CLV control.

FIG. 8 is a flowchart showing a processing operation in a wide mode as a processing operation of the system controller accompanying the CLV control.

FIG. 9 is an explanatory diagram showing transition of a CLV control operation in a wide mode.

FIG. 10 is an explanatory diagram showing a frame structure of an EFM signal.

FIG. 11 is an explanatory diagram showing an EFM word.

FIG. 12 is an explanatory diagram showing an EFM word.

FIG. 13 is an explanatory diagram showing an EFM word.

FIG. 14 is an explanatory diagram showing an EFM word.

FIG. 15 is a block diagram showing a configuration example of a CLV servo control circuit system as a conventional example.

FIG. 16 is a block diagram showing a configuration of a PLL circuit having a wide capture function as a conventional example.

[Explanation of symbols]

1 disc, 2 spindle motor, 3a objective lens, 3b detector, 3c laser diode, 3
d optical system, 3 optical head, 4 biaxial mechanism, 5
Thread mechanism, 6 RF amplifier, 7 signal processing circuit,
Reference Signs List 8 memory controller, 9 RAM (buffer memory), 10 D / A converter, 11 audio output terminal, 12 optical system servo circuit, 13 motor driver, 14 system controller, 15 operation unit, 20
Binarization circuit, 21 register, 22 EFM decoding circuit, 23 error correction / deinterleave processing circuit, 2
5 ACLV servo circuit system, 25B PLL circuit system, 25
PLL / CLV servo circuit, 26 synchronization detection circuit, 3
0 frequency divider, 31 crystal oscillator, 32 frequency divider, 33
CLV speed counter, 34 subtractor, 35A target variable setting circuit, 35 CLV target setting circuit, 3
6 adder, 37 low boost circuit, 38 D / A converter, 39 PLL target variable circuit, 40 target fixed value register, 41 analog PCO circuit, 4
2 filter, 43 adder, 44VCO, 45 FC
O counter, 46 subtractor, 47 amplifier, 48 integrator, 49 D / A converter, 50 PCI circuit, 5
1 amplifier, 60 counter section, 61 selector, 62
Minimum value register, 63 maximum value register, 64 set / reset unit, 65 maximum value detection unit, 66 minimum value detection unit, 67 edge detection circuit, 68 OR gate, 70,
72 flip-flop, 71 inverter, 73 switch, 74 exclusive OR gate, 75 edge detection circuit, 76 AND, 77 up / down counter, 78 PCI initial value register, 79 PCI register, 80 output terminal, SW1, SW2, SW3, SW
4, SW5 switch

Claims (7)

[Claims] 1. A phase-locked loop circuit for extracting a clock synchronized with a run-length limited code read from a rotationally driven disk-shaped recording medium, comprising: at least voltage-controlled oscillating means; Phase information detecting means for outputting a low-frequency component of a phase error with respect to a clock obtained based on the output of the voltage-controlled oscillation circuit with respect to the run-length limited code read from the disk, and the run read from the disk-shaped recording medium. A phase comparison is performed between the length limited code and a frequency signal obtained based on the clock, and a phase comparison unit that outputs a result of the phase comparison is based on a phase error low frequency component output from the phase information detection unit. The obtained control signal component is compared with the phase comparison result output from the phase comparison means. On the basis of the control signal component obtained based on the phase-locked loop circuit characterized by comprising a oscillation frequency control means for controlling the oscillation frequency of the voltage controlled oscillator. 2. A control signal component obtained based on a low-frequency component of a phase error between a run-length limited code read from a rotationally driven disk-shaped recording medium and a clock obtained based on an output of a voltage-controlled oscillation circuit. And a control signal component obtained by comparing a phase of a frequency signal obtained based on the clock with a run-length limited code read from the disk-shaped recording medium, and a voltage-controlled oscillation circuit. A phase-locked loop circuit operable to variably control the oscillation frequency of the phase-error information, and as a phase information detection device for detecting the low-frequency component of the phase error, a run-length limited read from the disk-shaped recording medium. Edge detecting means for detecting an edge of the code; A sampling means capable of sampling the clock at a timing at which an edge of the limited code is detected; a counting operation at a timing at which an edge of the run-length limited code is detected by the code edge detecting means; Means for setting whether the counting operation is up-counting or down-counting according to the level of the clock at the time of sampling by the means, and setting the count value of the counter means to the phase error. A phase information detecting device configured to output as a low frequency component. 3. A sampling operation control means for inhibiting a sampling operation by the sampling means during a period in which a phase of a clock to be sampled by the sampling means is inverted from a phase to be originally detected. The phase information detection device according to claim 2. 4. The counting means is configured to hold an offset value set in accordance with a phase error from a detection output of the phase comparator, and to provide the offset value to the count value. 3. The phase information detecting device according to claim 2, wherein 5. A control signal component obtained based on a low-frequency component of a phase error between a run-length limited code read from a rotationally driven disk-shaped recording medium and a clock obtained based on an output of a voltage-controlled oscillation circuit. And a control signal component obtained by comparing a phase of a frequency signal obtained based on the clock with a run-length limited code read from the disk-shaped recording medium, and a voltage-controlled oscillation circuit. In a phase locked loop circuit operable to variably control the oscillation frequency of the phase error detection method for detecting the low-frequency component of the phase error, a run-length limited code read from the disk-shaped recording medium is used. An edge detection process for detecting an edge; and the run length by the edge detection process. A sampling process capable of sampling the clock at a timing at which an edge of the limited code is detected; a counting operation at a timing at which an edge of the run-length limited code is detected by the code edge detection process; And a counter process in which whether the count operation is up-counting or down-counting is set in accordance with the level of the clock at the time of sampling. A phase information detecting method, wherein a value is output as a detection output of the phase error low frequency component. 6. The control process according to claim 5, wherein a control process for inhibiting the sampling process is executed during a period in which a phase of a clock to be sampled by the sampling process is inverted from an original phase. Phase information detection method. 7. The method according to claim 1, wherein at the time of the count processing, an offset value set corresponding to a phase error between the count value and a detection output of the phase comparator is provided. 6. The phase information detection method according to 5.