JPH11185396A - Pll and disk reproducing device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To more stabilize a phase pulling-in operation by reducing a possibility that a frequency comparator acts as a disturbunce at the time of phase pulling-in. SOLUTION: The maximum value MAX of edge intervals among >= one frame periods and a reference value C2 are compared in an S17. In the case of MAX > C2, when the number of times of the case is >= a previously set value C3, the output of frequency comparisons is made an L (S26a) and the frequency of a VOC is lowered. In the case of MAX < C2, when the number of times of the case is <= a previously set value C4, the output of frequency comparisons is made an H (S26c) and the frequency of the VOC is lowered. In the case other than both cases, the output of a frequency comparison is made a high impedance (S26b) and the frequency comparison is disabled.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a PLL applied to, for example, an optical disk reproducing apparatus and a disk reproducing apparatus.

[0002]

2. Description of the Related Art A CD (Compact) which is an example of an optical disk
Disc) reproducing apparatus reproduces a clock (channel bit clock) from a reproduced signal by a PLL circuit, separates a frame sync from the reproduced signal based on the clock, and uses the separated frame sync and clock to generate a reproduced signal. Is performed. The phase comparator of the PLL can lock the PLL when the CD has reached a substantially specified rotational speed.

In the case of a CD-ROM, a DVD-ROM, etc., there is a strong demand for shortening the access time, so that data can be read immediately at the start of rotation of the disk, immediately after a seek operation, and the like. And PLL
Is provided with a frequency comparator. In some cases, data is read by rotating an optical disk recorded by CLV, such as a CD, by CAV. In such a case,
A frequency comparator is provided in the PLL. By providing the frequency comparator, frequency pull-in is performed so that the frequency of the clock generated by the PLL substantially matches the frequency of the reproduced signal, and after the pull-in is completed, the VCO is controlled by the comparison output of the phase comparator. It is made to do.

[0004] However, once the frequency comparator pulls in the frequency, the rate of comparison is lower than that of the phase comparator. Therefore, if the disk is damaged, there is a high possibility that a large disturbance to the PLL will occur. . In order to avoid this problem, the frequency comparison operation is disabled when the PLL is locked by the GFS signal indicating that the PLL is locked. For example, in the case of a CD, since 588 clocks exist in one frame period, a window pulse corresponding to the frame sync is generated by the PLL clock, and when the frame sync is detected within the width of the window pulse, the GFS The signal is set to H (high level), for example, while the GFS signal is set to L (low level) when the frame sync is lost.

[0005]

However, since the role of the frequency comparator ends when the frequency is pulled in, locking the PLL, that is, performing the process of pulling in the phase and then disabling it, is a condition. Is too harsh. As a result, there is a problem that the frequency comparator acts as a disturbance from the end of the frequency pull-in to the end of the phase pull-in, making it difficult to pull in the PLL. Further, there is a problem that a circuit for determining whether or not the PLL is locked from the RF signal is separately required.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to reduce the possibility that a frequency comparator acts as a disturbance during phase pull-in, and to further stabilize phase pull-in.
Another object of the present invention is to provide a disk reproducing apparatus capable of performing a quick and stable reproducing operation.

[0007]

In order to solve the above problems, the invention of claim 1 compares a VCO whose oscillation frequency is controlled by a control signal with a frequency of an input signal and a frequency of a VCO output. Frequency comparison means, and phase comparison means for comparing the phase of the input signal with the phase of the VCO output, and by supplying the comparison output of the frequency comparison means to the VCO, the frequency of the input signal and the frequency of the VCO output Is substantially equalized, the VCO is controlled by the comparison output of the phase comparison means. When the frequency of the input signal is determined to be substantially equal to the frequency of the VCO output, the frequency comparison means Generates an output that does not change the output frequency of the input signal.
When it is determined that the frequency of the CO output is different, when the same comparison output continues for a preset number of times,
A PLL for generating an output for changing an output frequency of a VCO corresponding to a comparison output.

According to a second aspect of the present invention, a VCO whose oscillation frequency is controlled by a control signal, a frequency of an input signal and a VC
The frequency comparator includes frequency comparison means for comparing the frequency of the O output, and phase comparison means for comparing the phase of the input signal with the phase of the VCO output. The VCO is controlled by the comparison output of the phase comparison means with the frequency of the VCO output substantially equal to the frequency of the VCO output, and the difference between the frequency of the input signal and the frequency of the VCO output is determined in advance. When it is determined that the frequency is within the set margin, an output of a value that does not change the output frequency of the VCO is immediately generated, and it is determined that the frequency of the input signal and the frequency of the VCO output are different from each other beyond the range. When the same comparison output is repeated a preset number of times, an output for changing the output frequency of the VCO corresponding to the comparison output is generated. That is a PLL.

According to a third aspect of the present invention, there is provided a disk reproducing apparatus having a PLL for reading a reproduction signal from a disk-shaped recording medium and generating a clock synchronized with the reproduction signal.
LL is a VC whose oscillation frequency is controlled by a control signal.
O, frequency comparing means for comparing the frequency of the input signal with the frequency of the VCO output, and phase comparing means for comparing the phase of the input signal with the phase of the VCO output. The VCO is controlled by the comparison output of the phase comparison means in a state where the frequency of the input signal and the frequency of the VCO output are substantially equalized. When it is determined that the frequency of the output is substantially equal, an output of a value that does not change the output frequency of the VCO is immediately generated, and when it is determined that the frequency of the input signal is different from the frequency of the VCO output, the same is generated. When the comparison output of a predetermined number of times is continuous, the comparison output corresponds to
A disk reproducing apparatus for generating an output for changing an output frequency of a VCO.

According to a fourth aspect of the present invention, there is provided a disk reproducing apparatus having a PLL for reading a reproduction signal from a disk-shaped recording medium and generating a clock synchronized with the reproduction signal.
LL is a VC whose oscillation frequency is controlled by a control signal.
O, frequency comparing means for comparing the frequency of the input signal with the frequency of the VCO output, and phase comparing means for comparing the phase of the input signal with the phase of the VCO output. The VCO is controlled by the comparison output of the phase comparison means in a state where the frequency of the input signal and the frequency of the VCO output are substantially equalized. When it is determined that the difference between the output frequency and the output frequency is within the range of a preset margin, an output of a value that does not change the output frequency of the VCO is immediately generated, and the frequency of the input signal and the frequency of the VCO output are within the range. When the same comparison output continues for a preset number of times, the output frequency of the VCO corresponding to the comparison output is changed. Is a disk reproducing apparatus characterized by generating an output.

In the present invention, when the target frequency is reached and VC
In the case where the frequency of O is not changed, the output of the comparison unit is immediately changed to an output that does not affect the VCO. On the other hand, when the same frequency comparison output is continuously generated a predetermined number of times, the output that changes the frequency of the VCO for the first time. Is made to occur. When determining whether the target frequency has been reached, a range including a margin is set. When the number of times out of this range exceeds a predetermined number, an output for changing the frequency of the VCO is generated for the first time. Therefore, once the PLL is locked, the possibility that the frequency comparison operation becomes a disturbance to the PLL can be reduced. Also,
No circuit is required to detect whether the PLL is locked.

[0012]

An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows an overall configuration of an embodiment of the present invention. The disc reproducing apparatus shown in FIG. 1 is capable of reproducing discs of two different standards, CD and DVD, as optical discs. In FIG. 1, what is indicated by 1 is an optical disk (CD or DVD). Optical disk 1 is spindle motor 2
For example, it is driven to rotate at CLV. An optical pickup 3 is provided for reproducing data from the optical disc 1.

The optical pickup 3 is a biaxial device for changing an objective lens in two directions, a radial direction (tracking direction) of the disk and a direction away from the disk (focus direction), and reproduces data on each medium. And a semiconductor laser 5a for DVD, a semiconductor laser 5b for DVD, a photodetector 6, and optical elements such as a beam splitter. The photodetector 6 has, for example, a four-divided configuration.

The signal detected by the photodetector 6 is R
It is supplied to the F amplifier 7. The RF amplifier 7 calculates detection signals respectively generated from the four regions of the photodetector 6 to generate an RF signal, a tracking error signal TE, and a focus error signal FE. These signals are supplied to the read channel and the servo section 8. In the read channel and servo section 8, a bit clock is reproduced from the RF signal by the PLL, and a focus synchronization signal is separated. Also, the read channel and the servo unit 8
Based on the tracking error signal TE and the focus error signal FE, the biaxial device 4 of the optical pickup 3
Generate a signal that controls These control signals are supplied to the two-axis device 4 via the two-axis driver 9. Also,
The RF amplifier 7 receives a detection signal corresponding to the laser power generated by the semiconductor lasers 5a and 5b, and performs laser power control for controlling the laser power to an appropriate value.

The read channel and servo section 8 generates a control signal for a spindle driver 10 for driving the spindle motor 2. By the spindle motor 2,
The optical disk 1 is driven to rotate at CLV. Further, the read channel and the servo section 8 generate a control signal for the thread driver 12 that drives the thread motor 11. The optical pickup 3 is moved in the disk radial direction by the thread motor 11.

The read data from the read channel and the servo section 8 is supplied to a signal processing section 13 including an ECC (error correction), a buffer controller, and a host interface. The buffer memory 14 is connected to the signal processing unit 13. The reproduction data from the signal processing unit 13 is sent to the host processor via an interface connector (not shown). A system controller 15 including an MPU is provided to control the operation of the entire drive. A ROM 16 for storing programs is connected to the system controller 15.

Although simplified in FIG. 1, RF
The RF signal from the amplifier 7 is a P
Except for the LL processing system, there are two systems, an RF signal output when reproducing a DVD and an RF signal output when reproducing a CD. Then, the read channel and the servo unit 8
Each of the signal processing units 13 includes two processing units corresponding to each medium. That is, one of the read channel and the servo unit included in the read channel and the servo unit 8 and supplied with the RF signal when the DVD is reproduced is
Detection of frame sync, 8-16 demodulation, CL for DVD
Perform processing such as V-servo. The other read channel to which the RF signal when the CD is reproduced and the servo unit perform processing such as frame sync detection, 8-14 demodulation, and CLV servo for CD.

One of the signal processing units to which the reproduction data when reproducing the DVD in the signal processing unit 13 is supplied performs processing such as error correction and descrambling of the DVD. The other signal processing unit to which reproduction data when reproducing a CD in the signal processing unit 13 is supplied is a CD error correction, a CD-ROM, and the like.
And the like, such as decoding the reproduced data. Processing of the buffer memory 14, the interface with the host, etc.
It can be shared between D playback and CD playback.

In the disc reproducing apparatus shown in FIG.
When reproducing the DVD, the bias of the focus error signal FE is controlled to an appropriate value every time the DVD is mounted on the rotating unit. For this purpose, the absolute value of the phase error signal of the PLL in the read channel and the servo section 8 is supplied to the low-pass filter 17.
The A / D converter 18 converts the absolute value signal averaged by the digital signal into a digital signal. The output signal of the A / D converter 18 is supplied to the system controller 15.

The system controller 15 evaluates the quality of the reproducing system from the low-frequency component of the absolute value of the phase error signal, and generates a control signal for adjusting the bias of the focus error signal so as to improve the quality. Since the bias adjustment circuit is included in the RF amplifier 7, a control signal from the system controller 15 is supplied to the RF amplifier 7. The bias adjustment circuit for the focus error signal in the RF amplifier 7 changes the bias in response to a control signal from the system controller 15. Then, the system controller 15 again evaluates the quality of the reproduction system from the low-frequency component of the absolute value of the phase error, and performs bias control of the focus error signal. By repeatedly performing this evaluation and control, a bias that minimizes the absolute value of the phase error can be set.

FIG. 2 shows an example of a PLL provided in the read channel and the servo section 8 of the above-described disk reproducing apparatus and performing a bit clock reproducing process. In FIG. 2, components (optical pickup 3, RF amplifier 7, etc.) of FIG. 1 that are not related to the PLL are omitted. An RF signal formed by reproducing the optical disk 1 is supplied to the frequency comparator 21 and the phase comparator 22, respectively.

The PLL comprises a frequency comparator 21, a phase comparator 22, an adder 23, an LPF (low-pass filter) 24,
It comprises a VCO (voltage controlled oscillator) 25 and a 1 / N frequency divider 26. The PLL locks a frequency formed by the frequency comparator 21, the adder 23, the LPF 24, and the VCO 25, and a phase locked by the phase comparator 22, the adder 23, the LPF 24, and the VCO. And a loop. The frequency comparator 21 has V
From the CO 25, a clock (PLCK × N) having a frequency N times the clock frequency and a reproduction signal are supplied. The frequency comparator 21 performs frequency detection based on a clock (PLCK × N) and a frame synchronization signal included in the reproduction signal. The frame synchronization signal is a signal included for each data (frame) having a predetermined length determined by the format of each of the CD and the DVD, and has a bit pattern that cannot be present in normal data.
In addition, the frame synchronization signal includes a pattern having a maximum length that can be considered in terms of format. Therefore, in the frequency comparator 21, the pattern can be distinguished from other patterns, and the length of the pattern is measured by the clock (PLCK × N). Then, the output of the frequency comparator 21 is controlled based on the measurement result so that the output frequency of the VCO 25 approaches the frequency of the bit clock of the disk reproduction signal RF.

The frequency comparator 21 is supplied with a CD / DVD switching signal via a terminal 28. CD / DV
The D switching signal indicates whether the loaded optical disc 1 is a CD or a DV.
D is formed. This switching signal is generated based on a difference in the shape of a hole or the like provided in the disk jacket, a difference in the reflectance of the disk, and the like. As described later, a reference value or the like used in the processing of the frequency comparator 21 is set in accordance with the CD / DVD switching signal.

The clock (PLCK) from the 1 / N divider 26 and the reproduced signal are supplied to the phase comparator 22, and the phase comparator 22 compares the phases of these signals. The comparison output of the phase comparator 22 is supplied to the adder 23, and is added to the comparison output of the frequency comparator 21. This adder 23
Is supplied to the control terminal of the VCO 25 via the LPF 24. The oscillation frequency of the VCO 25 is changed according to the control voltage. For example, when the control voltage is set to the midpoint potential (for example, 2.5 V), the oscillation frequency is maintained, and when the control voltage is set to the high level (for example, 5 V), the oscillation frequency is increased. When the control voltage is set to a low level (for example, 0 V), the oscillation frequency is reduced. A clock (PLCK × N) formed according to the control voltage in the VCO 25 is supplied to the frequency comparator 21, and the phase comparator 22 via the 1 / N frequency divider 26.
Supplied to (PLCK × N) represents a frequency that is N times the clock frequency of the channel bit.

FIG. 3 shows an example of the configuration of the frequency comparator 21 described above. As shown in FIG. 3, the frequency comparator 21 includes an edge detection circuit 31, an edge interval measurement circuit 32, a maximum value storage circuit 33, a counter 34, and a comparison unit 35. Note that the edge detection circuit 31, the edge interval measurement circuit 32, the maximum value storage circuit 33, the counter 34, and the comparison unit 3
Each of the circuits 5 has, for example, a positive edge trigger type circuit configuration and operates at the timing of the rising edge of the clock supplied to the clock input terminal 37.
Note that the input terminal 37
Is supplied with a clock PLCK.

A terminal 36 is derived from the edge detection circuit 31, and the above-mentioned reproduction signal is supplied to this terminal 36. Further, an edge detection circuit 31, an edge interval measurement circuit 32, a maximum value storage circuit 33, a counter 34, a comparison unit 3
A terminal 37 is derived from a common connection point of the respective clock input terminals 5 and a clock PLCK is supplied to the terminal 37. Further, the control terminals of the counter 34 and the comparison unit 35 are connected to each other, a terminal 28 is derived from this connection point, and a CD / DVD switching signal is supplied to this terminal 28.

The edge detection circuit 31 detects, for example, a rising edge of the reproduction signal, and a detection output is supplied to the edge interval measurement circuit 32 and the counter 34. In the edge interval measuring circuit 32, the edge interval is measured based on the clock PLCK. That is, the interval between rising edges is measured by counting the interval between edges by the clock PLCK. The edge interval is supplied to the maximum value storage circuit 33.

Further, the counter 34 counts the number of edges, and outputs a pulse signal every time the counter 34 counts the number of sections corresponding to one or more frames. The counter 34 is supplied with a CD / DVD switching signal, and sets the number of edges corresponding to one frame corresponding to each of a CD and a DVD. The output of the counter 34 is supplied to the maximum value storage circuit 33 and the comparison block 35 as a reset signal.

The maximum value storage circuit 33 stores the count value of the edge interval from the edge interval measurement circuit 32 as a clock PLC.
At each timing of K, the count value is compared with the value already stored. If the current count value is larger, the count value is replaced with the previous stored value and stored. Otherwise, the stored value is changed. Hold. The maximum value stored in the maximum value storage circuit 33 is reset by a reset signal from the counter 34. The output of the maximum value storage circuit 33 is
5 is supplied.

The comparator 35 compares the maximum value of the edge interval from the maximum value storage circuit 33 with a reference value. Comparison unit 35
In, an output signal is formed based on the result of the determination process, and the output of this comparison unit is taken out via a terminal 38,
The VCO 2 via the adder 23 and the LPF 24 described above
5 is supplied as a control voltage. For example, the comparison unit 35
(Maximum value> reference value) outputs L (low level), (maximum value <reference value) outputs H (high level), and (maximum value = reference value) sets the output impedance to high impedance (midpoint potential). I do. At this time, the comparison unit 35 includes a CD / D
A VD switching signal is supplied, and different reference values are set for a CD and a DVD.

Regarding the above-described embodiment of the present invention,
This will be described in more detail with reference to FIGS. 4, 5 and 6. FIG. 4 shows a conventional frequency comparison process. Before describing the frequency comparison processing according to the present invention, the conventional processing will be described first. In step S1, an initialization process is performed. That is, although not shown, the counter 34 is cleared and the contents stored in the maximum value storage circuit 33 are cleared. Then, the detection operation is started in the edge detection circuit 31 (step S2). The detection pulse from the edge detection circuit 31 is supplied to the edge interval measurement circuit 32, and the edge interval is counted as the number of clocks PLCK (step S).
3). Then, the maximum value of the edge interval measured by the edge interval measuring circuit 32 is stored in the maximum value storage circuit 33 (step S4).

At the same time, the counter 34 counts the number of detection pulses from the edge detection circuit 31 (step S5), and determines whether the edge count value is equal to or longer than one frame period and shorter than two reference periods. C1
Is determined (step S6). The reference value C1 is set to a different value for a CD and a DVD. In the case of CD, one frame is 588 channel bits long, and the average pattern length is:
Since it is at least 5 or more, in the case of a CD, (C1
= 588/5 (however, the decimal part is rounded up to an integer). In the case of DVD, one frame is 148
Since the length is 8 channel bits and the average value of the pattern length is at least 4 or more, in the case of DVD,
(C1 = 1488/4 (the decimal portion is rounded up to an integer)). The predetermined period is set in this way because the frame synchronization signal of the pattern having the maximum interval of the edge specified by the modulation method is always set to one in the predetermined period.
One is to be included.

If it is determined that the edge count value has not reached the reference value C1, the process returns to step S2, and the processes of steps S2 to S6 are repeated. Then, when the edge count value reaches the reference value C1 and it is determined that the period of one or more frames has ended, the processing shifts to the processing of step S7 in the comparing unit 35.

In the comparator 35, the maximum value storage circuit 33
, Ie, the count value MAX corresponding to the maximum pattern length during the period of one frame or more and the reference value C2. In addition, the reference value C2 used for this comparison processing
Is set to (C2 = 11) in the case of a CD and (C2 = 14) in the case of a DVD, corresponding to the fact that the modulation method is different between a CD and a DVD.

The output of the comparing section 35, that is, the output of the frequency comparator is determined based on the result of the determination in step S7 (steps S8a, S8b, S8).
c). Thereafter, the process returns to the first step S1, and the processes of steps S1 to S8 are repeatedly performed.
In the conventional frequency comparison process shown in FIG. 4, the result of the frequency comparison is immediately reflected in the output. If the count value MAX corresponding to the maximum pattern length is larger than the reference value C2, V
It is determined that the oscillation frequency of the CO 25 is higher than the frequency of the reproduction signal, and in step S8a, an output of L is generated, and the VCO is controlled in a direction to decrease the oscillation frequency.

If the count value MAX is smaller than the reference value C2, it is determined that the oscillation frequency of the VCO is lower than the frequency of the reproduction signal, and in step S8c,
An H output is generated to control the VCO in a direction to increase the oscillation frequency. Further, when the count value MAX is equal to the reference value C2, it is determined that the oscillation frequency of the VCO is equal to the frequency of the reproduction signal. In step S8b, the output state of the high impedance is set, and the frequency of the VCO is not changed. That is, the comparison operation of the frequency comparator is disabled. The voltage output in the high impedance state is
For example, the midpoint potential of H (+5 V) and L (0 V) (+2.5
V).

In the frequency comparison process described above, the VCO oscillation frequency is controlled to a frequency close to the frequency of the reproduction signal from a state where the oscillation frequency greatly deviates from the frequency of the reproduction signal, and the oscillation frequency of the VCO and the frequency of the reproduction signal are substantially changed. By making them equal, a state where the phase can be finally locked only by the phase comparator can be obtained. However, in this state, there is a possibility that the output of the frequency comparator acts as a disturbance. For example, in a phase locked state or a state where the frequency pull-in is completed, the frequency comparator responds to a sudden frequency deviation due to scratches or noise on the disk, and an incorrect output is output from the frequency comparator. As a result, an unnecessary signal is output from the VCO for one frame, and the frequency deviates.
You have to start over from pulling in the frequency.

The present invention solves such a problem. That is, when the target frequency is reached and the VCO 25
In the case where the frequency is not changed, the output of the comparison unit 35 is promptly changed to an output in a state where the VCO 25 is not affected. On the other hand, in the case where the oscillation frequency of the VCO 25 is changed, the output of the comparison unit 35 is set to an output in a state where the frequency of the VCO 25 is changed when the same frequency comparison result continues more than a predetermined number of times.

FIG. 5 shows a characteristic portion of the processing performed in one embodiment of the present invention. FIG. 5 shows only the processing after step S7 in FIG. Since the processing up to step S6 is the same, a description thereof will be omitted. Step 17
In the same manner as in step S7 (FIG. 4) described above, the output of the maximum value storage circuit 33, that is, a comparison process between the count value MAX corresponding to the maximum pattern length in one frame section and the reference value C2 is performed. In the case of (MAX> C2), it is determined that the oscillation frequency of the VCO 25 may be higher than the frequency of the reproduction signal, and the process proceeds to Step S18. In the case of (MAX <C2), it is determined that the oscillation frequency of the VCO 25 may be lower than the frequency of the reproduction signal, and the process proceeds to Step S20. Furthermore,
In the case of (MAX = C2), it is determined that the oscillation frequency of the VCO 25 is equal to the frequency of the reproduction signal, and step S1
The process moves to 9.

In step S18, first, (Ch = 0)
It is said. Ch is (MAX) in step S17.
This is a count value indicating the number of times determined as <C2), and is a count value used to set the frequency comparison output to H. Each time (MAX> C2) is determined in step 21, the count value Cl is incremented. C
l is a count value used to set the frequency comparison output to L.

In the next step 24, the count value C
1 is compared with a preset reference value C3. It is determined whether the oscillation frequency of VCO 25 needs to be changed based on the comparison result. The reference value C3 can be appropriately selected, but is, for example, a value between 10 and 15. (Cl
> C3), and when the count value Cl is equal to or more than the reference value C3, the frequency comparison output is set to L (step S26).
a). Thereby, the VCO 25 is controlled so as to lower the oscillation frequency of the VCO 25. As described above, when the frequency comparison output is set to L, it is necessary that the same comparison result continues more than the reference value indicated by C3. Otherwise, an output is generated that does not change the oscillation frequency immediately.

In the case where (Cl> C3) is not satisfied,
It is determined that there is no need to change the oscillation frequency, and the routine goes to Step S26b. Step S26b is a process of generating a high-impedance output that disables the frequency comparison operation.

In the case of (MAX <C2), step S
At 20, (Cl = 0) is set. Then, in step 23, the count value Ch is incremented, and (MAX)
The number of times determined as <C2) is counted. Next, in step 25, a comparison process between the count value Ch and a preset reference value C4 is performed. The reference value C4 may be equal to the reference value C3.

In the case of (Ch> C4), it is determined that the oscillation frequency of the VCO 25 is lower than the frequency of the reproduction signal, and in step S26c, the output of H is compared with that of the comparator 35.
Output. Thereby, the oscillation frequency of the VCO 25 is controlled so as to increase. If not (Ch> C4), the process moves to step S26b, where the oscillation frequency is not controlled. In the case of (MAX = C2), (Cl = 0) is set in step S19, and then (Ch = 0) is set (step S22). Then, control goes to a step S26b. Thus, when the frequency comparison output is set to H,
It is necessary that the same comparison result continues over the reference value indicated by C4. Otherwise, an output is generated that does not change the oscillation frequency immediately.

FIG. 6 shows a process according to another embodiment of the present invention. The other embodiments are suitable for application when the capture range can be secured to some extent only by the phase comparator.
That is, by disabling the frequency comparison operation when the frequencies match to some extent, the possibility that the frequency comparison operation acts as a disturbance can be reduced. In FIG. 6, the processing up to step S27 is the same as the processing in FIGS. 4 and 5 described above. However, step S
27, (MAX> C2 + Wl), (C2-Wh <M
AX <C2 + Wl) or (MAX <C2-Wh) is determined. Wl is a margin for setting the output to L, and Wh is a margin for setting the output to H.

In step 27, (MAX> C2 +
If it is determined to be Wl), the frequency comparison output is set to L (step S28a). Thereby, the VCO 25 is controlled so as to lower the oscillation frequency. (MAX <C
2-Wh), the frequency comparison output is set to H
(Step 28c). Thereby, the VCO 25 is controlled so as to increase the oscillation frequency. (C2-W
If h <MAX <C2 + Wl), the frequency comparison operation is disabled (step S28b). Thereby, the oscillation frequency is not changed. That is, it is detected that the oscillation frequency has almost reached the target frequency, and if it is within the range, it is possible to quickly generate an output that does not change the oscillation frequency.

In another embodiment of the present invention, since the capture range of the phase comparator can be secured to some extent, the reference values (C2 + Wl) and (C2-Wh) including the margin are provided.
Is set, the margin of deviation between the oscillation frequency of the VCO 25 and the frequency of the reproduction signal is secured.

In the embodiment of the present invention and the other embodiments, each is separately described.
Both may be used together. Further, in the above description, the frequency comparison processing is performed based on a clock having a frequency equal to the frequency of the channel bit clock of the reproduction signal. However, as shown in FIG.
The frequency comparison processing is preferably performed using a clock having a frequency N times the channel bit clock frequency. The reason is that the measurement of the edge interval can be performed with higher accuracy. Further, the above-described frequency comparison processing may be performed by software processing by a microcomputer.

[0049]

According to the present invention, when the target frequency is reached, the output of the comparison unit is immediately changed to an output in which the VCO is not affected.
When the same comparison result continues, an output that changes the oscillation frequency of the VCO is generated. Further, according to the present invention, in the processing in the comparison unit, the target frequency is almost reached, but when the target frequency is not completely reached, a window is provided and if the target frequency is within the range, a value that does not promptly change the oscillation frequency is set. Output.
Therefore, according to the present invention, the possibility that the frequency comparator acts as a disturbance at the time of phase pull-in is reduced, and the phase pull-in can be further stabilized. Further, the present invention has an advantage that a circuit for detecting that the PLL is locked from the RF signal is not required.

[Brief description of the drawings]

FIG. 1 is a block diagram of an embodiment of a disk reproducing apparatus according to the present invention.

FIG. 2 is a block diagram of a PLL to which the present invention can be applied.

FIG. 3 is a block diagram illustrating a configuration of a frequency comparator according to an embodiment of the present invention.

FIG. 4 is a flowchart for explaining the present invention.

FIG. 5 is a flowchart used to explain the operation of the embodiment of the present invention.

FIG. 6 is a flowchart used to describe the operation of another embodiment of the present invention.

[Explanation of symbols]

1 ... optical disk, 2 ... spindle motor, 3 ...
..Optical pickup, 8 read channel, servo section, 21 frequency comparator, 22 phase comparator, 23 adder, 25 VCO, 31
・ Edge detection circuit, 32 ・ ・ ・ Edge interval measurement circuit, 3
3 ... maximum value storage circuit, 34 ... counter, 35
..Comparison section

Claims (8)

[Claims] 1. A VCO whose oscillation frequency is controlled by a control signal, frequency comparing means for comparing a frequency of an input signal with a frequency of a VCO output, and comparing a phase of the input signal with a phase of the VCO output. A phase comparison means for supplying a comparison output of the frequency comparison means to the VCO, so that a frequency of the input signal and a frequency of the output of the VCO are substantially equal to each other. The VCO is controlled by the following. The frequency comparison means determines the frequency of the input signal and the V
When it is determined that the frequency of the CO output is approximately equal,
An output of a value that does not change the output frequency of the VCO is immediately generated, and when it is determined that the frequency of the input signal is different from the frequency of the VCO output, the same comparison output continues for a preset number of times. A PLL for generating an output for changing the output frequency of the VCO corresponding to the comparison output. 2. A VCO whose oscillation frequency is controlled by a control signal, frequency comparing means for comparing a frequency of an input signal with a frequency of a VCO output, and comparing a phase of the input signal with a phase of the VCO output. A phase comparison means for supplying a comparison output of the frequency comparison means to the VCO, so that a frequency of the input signal and a frequency of the output of the VCO are substantially equal to each other. The VCO is controlled by the following. The frequency comparison means determines the frequency of the input signal and the V
When it is determined that the difference from the frequency of the CO output is within the range of the preset margin, an output of a value that does not change the output frequency of the VCO is immediately generated, and the frequency of the input signal and the VCO output are not changed. When the frequency is determined to be different from the above range, when the same comparison output is repeated a predetermined number of times, an output for changing the output frequency of the VCO corresponding to the comparison output is generated. A PLL characterized by the above. 3. A PL for reading a reproduction signal from a disk-shaped recording medium and generating a clock synchronized with the reproduction signal.
The PLL comprises: a VCO whose oscillation frequency is controlled by a control signal; frequency comparison means for comparing a frequency of an input signal with a frequency of a VCO output; A phase comparing means for comparing the phase of the output with the output of the frequency comparing means. The comparison output of the frequency comparing means is supplied to the VCO so that the frequency of the input signal is substantially equal to the frequency of the VCO output. The VCO is controlled by a comparison output of the phase comparing means. The frequency comparing means controls the frequency of the input signal and the V
When it is determined that the frequency of the CO output is approximately equal,
An output of a value that does not change the output frequency of the VCO is immediately generated, and when it is determined that the frequency of the input signal is different from the frequency of the VCO output, the same comparison output continues for a preset number of times. A disc reproducing apparatus for generating an output for changing the output frequency of the VCO corresponding to the comparison output. 4. A PL for reading a reproduction signal from a disk-shaped recording medium and generating a clock synchronized with the reproduction signal.
The PLL comprises: a VCO whose oscillation frequency is controlled by a control signal; frequency comparison means for comparing a frequency of an input signal with a frequency of a VCO output; A phase comparing means for comparing the phase of the output with the output of the frequency comparing means. The comparison output of the frequency comparing means is supplied to the VCO so that the frequency of the input signal is substantially equal to the frequency of the VCO output. The VCO is controlled by a comparison output of the phase comparing means. The frequency comparing means controls the frequency of the input signal and the V
When it is determined that the difference from the frequency of the CO output is within the range of the preset margin, an output of a value that does not change the output frequency of the VCO is immediately generated, and the frequency of the input signal and the VCO output are not changed. When the frequency is determined to be different from the above range, when the same comparison output is repeated a predetermined number of times, an output for changing the output frequency of the VCO corresponding to the comparison output is generated. A disk reproducing device characterized by the above-mentioned. 5. An edge detecting means for detecting an edge of an input signal according to claim 1 or 2, wherein a detection signal is supplied from the edge detecting means, and an interval for measuring the interval between the edges based on an output of a VCO. Measuring means, a detecting signal supplied from the edge detecting means, a determining means for determining a predetermined period by counting the number of edges of the detecting signal, an output signal from the interval measuring means, and the determining means Means for detecting the maximum value of the interval between the edges of the predetermined period, and comparing the maximum value with a reference value to obtain a magnitude relationship between the frequency of the input signal and the output signal of the VCO. And a comparing means for determining the following. 6. The PLL according to claim 3, wherein the PLL is supplied with edge detection means for detecting an edge of a reproduction signal, and a detection signal from the edge detection means, and determines an interval between the edges based on an output of a VCO. An interval measuring means for measuring the distance, a detection signal is supplied from the edge detecting means, a determining means for determining a predetermined period by counting the number of edges of the detection signal, and an output signal from the interval measuring means. An output signal of the discriminating means is supplied, a means for detecting a maximum value of an interval between edges in the predetermined period, and a comparison between the maximum value and a reference value, whereby an input signal and an output signal of the VCO are compared. A disc reproducing apparatus comprising: comparing means for determining a magnitude relationship between frequencies. 7. The disk reproducing apparatus according to claim 6, wherein the comparing means switches the reference value according to a modulation method of a reproduction signal. 8. The method according to claim 6, wherein the predetermined period is one frame period or more and shorter than two frame periods, and based on an average value of the edge intervals of the reproduction signal, the one frame period or more is shorter than two frame periods. A disc reproducing apparatus for determining a period.