JPH11149467A - 規則検査のためのフレームワーク - Google Patents

規則検査のためのフレームワーク

Info

Publication number
JPH11149467A
JPH11149467A JP10244774A JP24477498A JPH11149467A JP H11149467 A JPH11149467 A JP H11149467A JP 10244774 A JP10244774 A JP 10244774A JP 24477498 A JP24477498 A JP 24477498A JP H11149467 A JPH11149467 A JP H11149467A
Authority
JP
Japan
Prior art keywords
node
elements
nodes
structures
block
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP10244774A
Other languages
English (en)
Japanese (ja)
Other versions
JPH11149467A5 (https=
Inventor
John G Mcbride
ジョン・ジー・マクブライド
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
HP Inc
Original Assignee
Hewlett Packard Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hewlett Packard Co filed Critical Hewlett Packard Co
Publication of JPH11149467A publication Critical patent/JPH11149467A/ja
Publication of JPH11149467A5 publication Critical patent/JPH11149467A5/ja
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/36—Circuit design at the analogue level
    • G06F30/367—Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Geometry (AREA)
  • Evolutionary Computation (AREA)
  • General Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Information Retrieval, Db Structures And Fs Structures Therefor (AREA)
  • Testing Electric Properties And Detecting Electric Faults (AREA)
  • Complex Calculations (AREA)
JP10244774A 1997-09-02 1998-08-31 規則検査のためのフレームワーク Withdrawn JPH11149467A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US922793 1997-09-02
US08/922,793 US5987237A (en) 1997-09-02 1997-09-02 Framework for rules checking

Publications (2)

Publication Number Publication Date
JPH11149467A true JPH11149467A (ja) 1999-06-02
JPH11149467A5 JPH11149467A5 (https=) 2005-10-27

Family

ID=25447583

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10244774A Withdrawn JPH11149467A (ja) 1997-09-02 1998-08-31 規則検査のためのフレームワーク

Country Status (3)

Country Link
US (1) US5987237A (https=)
EP (1) EP0901088A3 (https=)
JP (1) JPH11149467A (https=)

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6321365B1 (en) * 1999-01-26 2001-11-20 Hewlett-Packard Company System and method for detecting storage nodes that are susceptible to charge sharing
US6701290B1 (en) * 1999-02-18 2004-03-02 Hewlett-Packard Development Company, L.P. Method and apparatus for evaluating the design quality of network nodes
US7031889B1 (en) * 1999-03-22 2006-04-18 Hewlett-Packard Development Company, L.P. Method and apparatus for evaluating the design quality of network nodes
US6367055B1 (en) * 1999-04-27 2002-04-02 Hewlett-Packard Company Method and apparatus for determining certain characteristics of circuit elements
US6990643B1 (en) * 1999-05-13 2006-01-24 Hewlett-Packard Development Company, L.P. Method and apparatus for determining whether an element in an integrated circuit is a feedback element
US6523152B1 (en) 2000-03-08 2003-02-18 Hewlett-Packard Company Framework for rules checking utilizing resistor, nonresistor, node and small node data structures
US7082104B2 (en) 2001-05-18 2006-07-25 Intel Corporation Network device switch
US7093224B2 (en) 2001-08-28 2006-08-15 Intel Corporation Model-based logic design
US6859913B2 (en) 2001-08-29 2005-02-22 Intel Corporation Representing a simulation model using a hardware configuration database
US6983427B2 (en) 2001-08-29 2006-01-03 Intel Corporation Generating a logic design
US7107201B2 (en) 2001-08-29 2006-09-12 Intel Corporation Simulating a logic design
US7073156B2 (en) 2001-08-29 2006-07-04 Intel Corporation Gate estimation process and method
US7130784B2 (en) 2001-08-29 2006-10-31 Intel Corporation Logic simulation
US6640329B2 (en) * 2001-08-29 2003-10-28 Intel Corporation Real-time connection error checking method and process
US7197724B2 (en) 2002-01-17 2007-03-27 Intel Corporation Modeling a logic design
US6631506B1 (en) * 2002-04-02 2003-10-07 Hewlett-Packard Development Company, L.P. Method and apparatus for identifying switching race conditions in a circuit design
JP4312796B2 (ja) 2004-02-25 2009-08-12 パナソニック株式会社 プリント基板の電源分離チェック装置および方法
US7900178B2 (en) * 2008-02-28 2011-03-01 International Business Machines Corporation Integrated circuit (IC) design method, system and program product

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4858146A (en) * 1986-08-13 1989-08-15 The Babcock & Wilcox Company Automated design of structures using a finite element database
US5289567A (en) * 1991-04-01 1994-02-22 Digital Equipment Corporation Computer apparatus and method for finite element identification in interactive modeling
JP2788820B2 (ja) * 1991-08-30 1998-08-20 三菱電機株式会社 シミュレーション装置
US5394524A (en) * 1992-08-07 1995-02-28 International Business Machines Corporation Method and apparatus for processing two graphics data streams in parallel
DE69327389T2 (de) * 1992-10-29 2000-06-15 Altera Corp., San Jose Verfahren zum Prüfen von Entwürfen für programmierbare Logikschaltungen
US5522022A (en) * 1993-11-24 1996-05-28 Xerox Corporation Analyzing an image showing a node-link structure
US5787274A (en) * 1995-11-29 1998-07-28 International Business Machines Corporation Data mining method and system for generating a decision tree classifier for data records based on a minimum description length (MDL) and presorting of records
US5802508A (en) * 1996-08-21 1998-09-01 International Business Machines Corporation Reasoning with rules in a multiple inheritance semantic network with exceptions

Also Published As

Publication number Publication date
EP0901088A2 (en) 1999-03-10
EP0901088A3 (en) 2002-03-20
US5987237A (en) 1999-11-16

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