JPH1114702A - Ic test device and method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To evaluate an LSI of high operational frequency by using an IC tester of low speed. SOLUTION: By giving a fixed setting to a control circuit from an IC tester 1, a test pattern is transferred from the IC tester 1 to a test pattern storing memory 4, an LSI to be measured is measured, and the measured result is transferred from an output measurement storing memory 5 to the IC tester 1. At executing the measurement, the IC tester 1 is cut off by a relay 6 so as to reduce load capacity, data is input to the LSI to be measured while synchronizing with the high speed pulse of a signal generating circuit 3, and the output data from the LSI to be measured is stored.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an IC tester, and more particularly, to an LS operating at a higher speed than the operating frequency of the IC tester.
The present invention relates to an IC test apparatus that enables I to be tested.

[0002]

2. Description of the Related Art FIG. 7 is a block diagram showing an IC tester 1 and an LSI 7 to be measured when measuring or evaluating an LSI or IC as a prior art. Measurement of LSI under test,
When performing the evaluation, a test apparatus called an IC tester is used. An operating frequency of several tens of MHz when testing an LSI to be measured is generally used.
The test of I is performed as follows.

The IC tester 1 synchronizes a clock generated inside the apparatus with a test pattern prepared in the IC tester in advance, and inputs the test pattern to each terminal of the LSI 7 to be measured. Reference numeral 106 denotes an input signal. LSI to be measured
Performs a predetermined logical operation or the like sequentially according to this input,
The calculation result and the like are output for each LSI to be measured and for each test pattern. Reference numeral 107 denotes an output signal. IC
The tester compares the output result with the test pattern to determine the test. Based on these test patterns and the corresponding outputs, various measurements such as the operation timing and the error rate of the measured LSI are performed, and the evaluation of the measured LSI is performed to determine whether the operation as designed is achieved. .

On the other hand, as shown in FIG.
Japanese Patent Application Laid-Open No. 288805 discloses an IC having an IC tester 1, a signal generator 82, and a pulse extraction output circuit 81 in order to supply a high operating frequency to a clock signal.
A test device is disclosed.

[0005] This IC test apparatus converts a pulse signal 181 output from an IC tester and a pulse signal 182 which is a faster pulse signal than this pulse signal and is output from a signal generator 82 into a pulse extraction output circuit. 81, and through this circuit, one or more high-speed pulse signals 183 synchronized with the IC tester are input to the clock terminal of a synchronous digital IC.

[0006]

In recent years, the operating frequency of LSIs has been increasing, and some of them operate at several hundred MHz. However, many IC testers have a low clock signal of several tens of MHz, and the evaluation speed of the LSI is limited by the clock speed of the IC tester. Therefore, the evaluation of a high-speed LSI operating at several hundred MHz as described above cannot be performed by an IC tester having a low operating frequency. One way to evaluate a high-speed LSI is to use an IC tester that operates with a clock signal of 400 to 600 MHz. However, such an IC tester is not widely used because it is extremely expensive. Difficult to use.

The technique described in Japanese Patent Application Laid-Open No. 5-288805 is a method of inputting a high-speed pulse only to a limited input terminal such as a clock terminal. In this method, as shown in FIG. 9, a high-speed pulse is input to an input terminal serving as a clock of the LSI 7 to be measured, but a test pattern from an IC tester is input to an input terminal other than the clock that changes randomly. The measured L is measured only by a change synchronized with the maximum operating frequency of the IC tester.
Cannot input to SI. For example, the input signal 106-B that changes at random cannot change at the timing of the problem indication portion 91. Further, in the comparison of the output result of the output terminal, since the detection is performed at the timing limited to the maximum operating frequency in the low-speed IC tester in the related art, the output signal 107-D that changes at random indicates the problem point 92. , 93, cannot be measured, and when the change timing is close to the detection timing, as in the problem point 94, the measurement will be unstable with no margin.

Further, the load capacity of input / output signals of a low-speed IC tester is generally large, and is as large as 40 to 100 pF. The above-mentioned Japanese Patent Application Laid-Open No. 5-288805 does not particularly mention this, but it is indispensable to suppress the capacity when inputting at a high speed pulse. Also,
The reason why the timing at which the problem point 94 changes is unstable measurement is because the output load capacity of the IC tester is more than the ability of the LSI to be measured.

An object of the present invention is to evaluate an LSI having a high operating frequency by using a low-speed IC tester.

[0010]

According to the present invention, there is provided an IC tester comprising: an IC tester; a signal generating circuit for generating a pulse faster than the IC tester; a memory for storing a test pattern used in the IC tester; A memory for storing an output result of the LSI under test, a control circuit for controlling the signal generation circuit, a test pattern storage memory, and an output result storage memory by a signal input from the IC tester; And a relay that can be switched from the IC tester between the signals for connecting.

In the test circuit, the test circuit stores the expected value, which is obtained in synchronization with the basic clock from the signal generation circuit into the LSI to be measured in the test pattern storage memory, in the output result storage memory. A comparator for successively comparing the output value of the LSI with the output value and a flag for notifying the IC tester of the comparison result can be provided.

Further, the IC test method of the present invention provides an
In a series of processes for testing the SI, a command is input to the control circuit from the measurement signal of the IC tester to give the initial setting of the IC measuring device, the test pattern in the IC tester is transferred to the test pattern storage memory, A signal connecting the LSI and the LSI to be measured is not contacted, and the LSI to be measured is tested.

[0013]

FIG. 1 is a block diagram showing an embodiment of an IC test apparatus according to the present invention. This IC test equipment
Provided between the IC tester 1 and the LSI 7 to be measured,
It comprises a control circuit 2, a signal generation circuit 3, a test pattern storage memory 4, and an output result storage memory 5. Relays 6 are inserted into the signals 106 and 107 connecting the IC tester 1 and the LSI 7 to be measured, respectively.
The signal 102 for switching the switch is supplied from the IC tester 1.

The control circuit 2 receives the signal 10 of the IC tester 1
1, the setting is sent to the test pattern storage memory 4 and the output result storage memory 5 by a signal 103 in accordance with the command, and information for changing the frequency in accordance with the command is output by a signal 104 to the signal generation circuit 3. Send to

The signal generating circuit 3 is capable of outputting a pulse faster than the IC tester 1, and changes the output frequency according to the information received from the signal 104. The test pattern storage memory 4 and the output result storage memory 5 change the pattern length inside the memory according to the setting of the signal 103.

FIG. 2 is a block diagram showing the control circuit 2 of FIG. 1 more specifically. The control circuit 2 includes an IC tester 1
A command control unit 22 that receives a command sent by a signal 101 and controls each unit; a memory control unit 24 that sends a signal 103 to the test pattern storage memory 4 and controls the signal 103;
A signal 103 is sent to the output result storage memory 5, and a memory control unit 25 for controlling the signal 103 is sent to the signal generation circuit 3.
And a frequency control unit 23 for controlling this.

The control circuit 2 further stores the expected value input from the test pattern storage memory 4 to the LSI 7 to be measured in the output result storage memory 5 in synchronization with the basic clock 105 from the signal generation circuit 3 during the test. LSI to be measured
And a flag signal 110 for notifying the IC tester 1 of the determination of the comparison result.
And The expected value is controlled by the control circuit 2 by the signal 108.
The output value is sent to the control circuit 2 by a signal 109.

The operation of the IC test apparatus according to the present invention will be described with reference to the timing chart of FIG. 3 and the flowchart of FIG. When a test at a high operating frequency is performed using this IC test apparatus, the test is divided into three modes: pattern transfer [A], measurement execution [B], and test result judgment [C]. Through to set any mode by command and give initial setting at the same time.

First, the command [A] is obtained from the signal 101.
To set the IC test apparatus in the pattern transfer mode. As the initial setting at this time, the test pattern storage memory 4 is set to the input state and the pattern length to be transferred is given.
When the IC tester 1 starts running the test pattern,
The test patterns are stored in the test pattern storage memory 4 line by line in synchronization with the operating frequency of the IC tester 1. Synchronization timing is given by the basic clock 105.

Next, a command [B] is input from the signal 101 to set the mode to the measurement execution mode. In the initial setting, the test pattern storage memory 4 is set to the output state, the test result storage memory 5 is set to the input state, and the frequency to be operated by the LSI 7 to be measured is set. Further, at the start of the measurement execution [B], the signal 102 of the IC tester 1 is fixed at “H”, and the relay 6 is turned off. This allows signal 106,
107 can be cut off from the IC tester 1 and drastically reduce a high load capacity which becomes a problem in a test at a high operating frequency. As described above, the load capacity of the IC tester 1 is 40 to
Compared to 100 pF, the capacitance between the contacts of the relay 6 after being disconnected from the IC tester 1 is about 2 pF, which is a value that does not pose a problem as a load capacitance during high-speed operation.

Next, a command [C] is input from the signal 101 to set a test result determination mode. In the initial setting, the test result storage memory 5 is set to the output state. IC tester 1
After turning on the relay 6 from the signal 102, the test pattern starts to run, and the data in the output result storage memory 5 is output line by line in synchronization with the operating frequency of the IC tester 1 in the same manner as described above. , IC tester 1.

The flow of the embodiment of the IC test apparatus according to the present invention has been described above. This is an explanation of the operation at the evaluation stage before the LSI 7 to be measured is mass-produced and shipped, and is a flow that enables debugging for specifying a test pattern portion even when a failure occurs.

Next, a method for reducing the test time at the time of mass production shipment will be described with reference to the timing chart of FIG. 4 and the flowchart of FIG.

In consideration of the reduction of the test time, it can be realized by setting the measurement execution mode of the command [B] in the above-mentioned flow and simultaneously judging the measurement result. in this case,
The test pattern transfer mode of the command [A] is omitted. Specifically, at the time of setting a program load or the like on the IC tester 1 before the selection process starts, the command [A]
And the data is held in the test pattern storage memory 4 or the test pattern is written in advance in a UVEPROM or an EEPROM, etc.
It can be realized by mounting it in the test pattern storage memory 4. Either method is technically easy.

Further, the measurement execution mode of the command [B] is set, and the result is judged by the comparator 21 at the same time when the measurement is executed. This makes it possible to omit the measurement result determination using the command [C]. In the control circuit of FIG.
The data output from the test pattern storage memory 4 is input from the signal 106 to the LSI 7 to be measured,
08 to the comparator 21 in the control circuit. The data output from the LSI 7 to be measured is stored in the output result storage memory 5 and is also input from the signal 109 to the comparator 21 in the control circuit. When the comparison result between the two does not match, the comparator 21 changes the flag signal 110 to the “H” level, so that the result can be transmitted to the IC tester 1.

At present, when semiconductor technology is remarkably progressing, it is difficult to develop a device for performing measurement and evaluation without the latest device. However, it is necessary to replace only a signal generator and a memory or the like to replace the latest device. You will be able to develop semiconductor technology.

[0027]

According to the IC test apparatus and the test method of the present invention, even a low-speed IC tester can perform a test at a high operating frequency according to the measured object.

The reason is that the test pattern is input to the LSI under test in synchronization with the clock of the high-speed signal generation circuit of the IC test apparatus, the output data of the LSI under test is stored in the memory, and the IC tester This is because input plays a role of controlling the state.

Further, according to the present invention, there are problems in the conventional method of making a limited terminal such as a clock terminal a high-speed pulse, that is, the timing of other input terminals is limited, and output data cannot be measured. Or solved the instability.

The reason is that the entire test pattern is stored in the test pattern storage memory, and all the input / output terminals of the LSI under test can be tested at a high operating frequency.

Further, according to the present invention, when a low-speed IC tester is used at a high operating frequency, the problem that the load capacity of input / output signals of the IC tester is large and obstructs high-speed measurement can be solved.

The reason for this is that when testing at a high operating frequency with the IC test apparatus of the present invention, a relay is used to disconnect the input / output signal of the LSI to be measured from the IC tester, and the load capacity is reduced to 20%. It depends on about 1 /

As described above, it is possible to measure an existing highest-speed LSI product by using a low-speed IC tester that can measure an LSI to be measured only at an operating frequency of several tens of MHz. Also, no matter how much semiconductor technology advances in the future, the IC test apparatus of the present invention can obtain the same effect simply by replacing the signal generation circuit, the memory, and the like with the fastest parts in accordance with the progress of the technology. be able to.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of an embodiment of an IC test apparatus of the present invention.

FIG. 2 is a configuration diagram of a control circuit in the embodiment of FIG.

FIG. 3 is an explanatory diagram showing timing of each signal in the embodiment of FIG. 1;

FIG. 4 is an explanatory diagram showing the timing of each signal in FIGS. 1 and 2 when the test time is reduced.

FIG. 5 is an explanatory diagram showing an operation flow in the embodiment of FIG. 1;

FIG. 6 is an explanatory diagram showing an operation flow for shortening the test time.

FIG. 7 is a configuration diagram showing a relationship between an IC tester and an LSI to be measured.

FIG. 8 is a configuration diagram of a conventional technique disclosed in Japanese Patent Application Laid-Open No. 5-288805.

FIG. 9 is an explanatory diagram showing the timing of each signal of the prior art disclosed in Japanese Patent Application Laid-Open No. 5-288805 and an example of a problem at that time.

[Explanation of symbols]

 Reference Signs List 1 IC tester 2 Control circuit 3 Signal generation circuit 4 Test pattern storage memory 5 Output result storage memory 6 Relay 7 LSI under test 21 Comparator 22 Command control 23 Frequency control 24 Memory control 25 Memory control 81 Pulse extraction output circuit 82 Signal generator 91, 92, 93, 94 Problems pointed out 101, 102, 103, 104 signal 105 basic clock 106, 107, 108, 109 signal 110 flag 181, 182, 183 signal

Claims (6)

[Claims] 1. An IC tester for testing various characteristics of an LSI to be measured, comprising: an IC tester; a signal generation circuit capable of generating a clock having a frequency higher than a frequency of a basic clock of the IC tester; A test pattern storage memory for storing a test pattern for testing the same; an output result storage memory for storing an output result of a test of the LSI under test; a plurality of signals from the IC tester; A control circuit for controlling a test pattern storage memory and the output result storage memory; and an input to the LSI under test between a plurality of signals from the IC tester and a plurality of signals from the test pattern storage memory. And the supply of the output from the LSI under test is switched between the output result storage memory and the IC tester. IC test apparatus characterized by comprising: a switching circuit for switching between the. 2. The test pattern storage memory according to claim 1, wherein:
Read and write the test pattern in the C tester,
The LS to be measured is determined by the written test pattern.
2. The IC test apparatus according to claim 1, wherein whether to perform a test for operating I is controlled by a control signal output from the control circuit. 3. The output result storage memory writes an output result obtained by operating the LSI under test according to the test pattern, reads the written output result, and compares the output result with an expected value pattern in the IC tester. To
3. The IC test apparatus according to claim 1, wherein the control is performed by a control signal output from the control circuit. 4. The control circuit according to claim 1, wherein the control circuit controls a plurality of commands from the IC tester, an expected value pattern output from the test pattern storage memory, and a test output from the output result storage memory. A comparator for comparing a pattern with the IC tester and transmitting a comparison result to the IC tester; a plurality of memory control circuits for controlling the test pattern storage memory and the output result storage memory; and a frequency control unit for controlling the signal generation circuit. The command control unit controls the plurality of memory control units, the comparator, and the frequency control unit based on a plurality of commands from the IC tester, and stores the test pattern storage memory and the output result storage memory. Read or write of the test pattern storage memory and the Control whether or not to operate the force result storage memory with a high frequency clock, and control whether or not to compare and verify the test pattern from the test pattern storage memory with the expected value pattern in the IC test apparatus; 2. The frequency control of the signal generating circuit is performed.
4. The IC test apparatus according to any one of claims 1 to 3, 5. The memory according to claim 1, wherein said test pattern storage memory and said output result storage memory are operable at a frequency equal to or higher than an output frequency of said signal generation circuit. An IC test apparatus according to any one of the above. 6. An IC test method using an IC test apparatus according to claim 1, wherein a command is input to the control circuit from a measurement signal of the IC tester in a series of processes for testing the LSI under test. Providing an initial setting of a measuring device; transferring the test pattern in the IC tester to the control circuit; disconnecting a signal connecting the IC tester and the LSI to be measured in a non-contact manner; Testing an LSI to be measured.