JPH11146227A - Feedback type video signal processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a feedback type video signal processor which can use an ordinary general-purpose memory. SOLUTION: An external input video signal and a processing video signal stored in a storage means 5 are outputted through arithmetic processing at an arithmetic means 2 and stored in the storage means 5, while a control means 7 performs control so that the pressing video signal stored at an address generated from an address generating means 10 can be read out of the storage means 5 and the video signal processed by the arithmetic means 2 can be written at the same address. On the other hand, an address stream is generated from the address generating means 10 while sequentially updating addresses for each pixel, and the phase of the address stream is shifted just by the number of pixels corresponding to delay time related to feedback arithmetic processing at least for every lapse of one horizontal or vertical scanning period. Thus, read-out of video signals is skipped just by the number of pixels corresponding to the delay time related to that arithmetic processing, and the delay time of entire feedback loop is adjusted to 1H or one field period.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a feedback type video signal processing apparatus.

[0002]

2. Description of the Related Art A feedback type video signal processing apparatus uses a correlation between pixels adjacent to each other in a vertical direction or a time axis direction of a video signal, and calculates a video signal of peripheral pixels to improve image quality. Done. In such a video signal processing device, generally, an input video signal is delayed by one horizontal scanning period (1H period) or one field, and arithmetic processing is performed on the input signal and the delayed signal. Further, in applications such as a noise reducer for removing noise from a video signal, a feedback process for delaying the arithmetic processing result by 1H period or one field and feeding it back to the arithmetic processing to perform arithmetic processing with the input signal is performed. Will be

[0003] As an example of such a feedback type video signal processing device, a chroma noise reducer described in Japanese Patent Application Laid-Open No. 2-272891 is known. According to this, a video signal of one field is stored and delayed by a field memory, and a calculation is performed on the video signal of the next field and a video signal of the next field, thereby reducing a noise component of a color signal. According to this, an ideal state is assumed in which the delay time of the memory is 1 field and the delay time of the arithmetic processing is 0.

[0004]

In this feedback processing, the delay time of the entire feedback loop including the delay time of the delay means and the delay time of the arithmetic processing is generally set to exactly 1H period or 1 field period. There is a need. Therefore, it is necessary to make the delay time by the delay means shorter than the 1H period or one field period by an amount corresponding to the delay time of the arithmetic processing.

When a video signal whose period of 1H or one field changes, such as a reproduction signal of a VTR, is input, a write operation and a read operation to the delay means are performed with reference to the timing of horizontal synchronization or vertical synchronization. , It is necessary to control the delay time.

In such a case, in order to make the delay time by the delay means shorter than the 1H period or one field period by an amount corresponding to the delay time of the arithmetic processing,
The read operation from the delay means needs to precede the write operation. Therefore, when the delay means is constituted by a memory, a serial access memory called a FIFO (First In First Out) capable of performing a write operation and a read operation independently, and a write address and a read address are independent. It is common to use a dual-port memory that can be set as desired.

However, these FIFO and dual-port type memory elements have a problem in that they are more expensive than memory elements of a type that performs a write operation and a read operation from a single port.

In view of the above-mentioned conventional problems, an object of the present invention is to realize a feedback-type video signal processing device that can use a general-purpose memory.

[0009]

In order to solve the above-mentioned problems, an arithmetic means for inputting two video signals and performing predetermined arithmetic processing for each pixel, and a storage for storing the video signals processed by the arithmetic means Means, a control means for controlling a write operation and a read operation of the storage means, and an address generation means for generating an address of the storage means, wherein the arithmetic means has one input of a video signal inputted from outside. The feedback type video signal processing device that performs feedback operation processing on the other input as a video signal read from the storage means has the following configuration.

That is, the control means causes the video signal stored at the address generated by the address generation means to be read from the storage means, and then writes the video signal processed by the arithmetic means at the same address. The address generating means generates an address sequence by sequentially updating the address for each pixel of the video signal, and at least delay time related to the feedback calculation processing every one horizontal scanning period. The phase of the address sequence is shifted by a corresponding number of pixels.

By doing so, the video signal read from the storage means can be read in the next horizontal scanning period.
The address is shifted first by the number of pixels of the delay time related to the period calculation processing, the video signal is skipped by that amount, and the previous video signal is read earlier. As a result, the delay time of the entire feedback loop can be set to the 1H period.

The video signals corresponding to a plurality of pixels at the beginning of the horizontal scanning period are skipped by an amount corresponding to the shift of the address every one horizontal scanning period. Since the ten pixels are usually not displayed on the screen, there is no problem. In addition, for each horizontal scanning period, the address is shifted first,
Although the storage area corresponding to one horizontal scanning period is shifted, the required storage area is sufficient for the number of pixels of one horizontal scanning line by using the address of the circulation system.

On the other hand, when the video signal is delayed by one field cycle and the feedback operation is performed, the address is first shifted every one horizontal scanning period, and at least the feedback operation is performed every one vertical scanning period. The address string may be shifted by the number of pixels corresponding to the delay time for processing.

[0014]

Embodiments of the present invention will be described below with reference to the drawings. (First Embodiment) FIG. 1 is a circuit block diagram showing a first embodiment of a video signal processing apparatus according to the present invention.
It performs the type of feedback operation processing. FIG. 2 is a block diagram showing a specific example of the arithmetic circuit of FIG. 1, and FIG. 3 is a timing chart for explaining the operation.

As shown in FIG. 1, a video signal IN input from an input terminal 1 is input to an arithmetic circuit 2, where it is subjected to a predetermined feedback calculation process, and the processed video signal (hereinafter referred to as a "process"). DW (referred to as a video signal) is output from the output terminal 3. The processed video signal DW is input to the input / output unit I / O of the memory 5 via the three-state buffer 4. The input / output unit I / O of the memory 5 is connected to the input of the arithmetic circuit 2 via the register 6. These three-state buffer 4, memory 5 and register 6 are controlled by a pulse generated from timing control pulse generation circuit 7. Three-state buffer 4
Operates according to a control pulse from the timing control pulse generation circuit 7 and outputs a processed video signal DW output from the arithmetic circuit 2 when writing to the memory 5.
When reading from, it is kept in a high impedance state. The memory 5 has a capacity capable of storing pixel video signals for one horizontal scanning line. The timing control pulse generation circuit 7 generates a timing pulse for controlling a write operation and a read operation of the memory 5. For example, it generates an address strobe signal for instructing a timing at which an address signal is taken into the memory 5, a write enable signal for switching between a write operation and a read operation, an output enable signal for switching input / output of an input / output unit, and the like. However, specifically, since the control method and the control timing are different depending on the type of the memory 5 used, the function of the timing control pulse generation circuit 7 is formed according to the type of the memory 5.

On the other hand, the video signal IN input from the input terminal 1 is input to a synchronization separation circuit 8, where the horizontal synchronization signal is separated and output to an edge detection circuit 9. The edge detection circuit 9 detects an edge of the horizontal synchronization signal,
The edge pulse H synchronized therewith is supplied to the address counter 10.
Is output to the register 11. The address counter 10
Using the edge pulse H as a timing signal, the register 11
Is loaded as the initial value of the address, and thereafter, the address is incremented by "1" in accordance with the input clock signal. The clock signal is a signal that is synchronized with each cycle of one cycle of one read operation and one write operation to the memory 5. Then, the count output of the address counter 10 is supplied to the memory 5 as an address signal.

The register 11 is a register for giving an initial value of the address counter 10, and updates the initial value by using the edge pulse H from the edge detection circuit 9 as a timing signal. That is, the adder 12 adds a predetermined constant addition value to the output of the register 11 and outputs the result to the register 11. The register 11 captures and holds the output value of the adder 12 every time the edge pulse H is input. Here, the addition value in the adder 12 of this example is set to “3” which is the number of pixels corresponding to the delay time excluding the memory 5 in the feedback loop. Therefore, register 1
The value of 1 increases by “3” each time the edge pulse H is input from the edge detection circuit 9.

The operation of the embodiment configured as described above will be described below. Here, the arithmetic circuit 2 of FIG.
In the following description, it is assumed that an arithmetic circuit of a noise reducer for reducing a noise component of a video signal is applied as shown in FIG. In FIG. 2, the input terminal 20 is the input terminal 1 of FIG.
, And a feedback video signal RTN is input to the input terminal 21 from the memory 5 guided through the register 6 in FIG. The video signal IN input from the input terminal 20 is guided to the adder 30 via the register 23 and the register 25. On the other hand, the feedback video signal RTN input from the input terminal 21 is supplied to the subtractor 2 via the register 24.
8, where the video signal IN stored in the register 23 is subtracted. The output of the subtracter 28 is multiplied by a constant set in advance by a multiplier 29 and stored in a register 26. The signal stored in the register 26 is added to the video signal stored in the register 25 by the adder 30 and output to the output terminal 22 via the register 27. This output terminal 22 is connected to the output terminal 3 and the three-state buffer 4 of FIG.

In the arithmetic circuit 2 configured as described above, the two video signals input are first converted into registers 23 and 24.
Aligns the phases. Subsequently, the difference between the two signals is calculated by the subtracter 28. After the multiplier 29 multiplies the difference by a certain coefficient, the adder 30 adds the difference to the input signal and outputs the result. When a difference occurs between the two video signals input to the arithmetic circuit 2 by such an operation, the difference is reduced and output. Here, the coefficient of the multiplication in the multiplier 29 is generally called a feedback coefficient, and is a numerical value equal to or less than “1”. By the way, in such arithmetic processing, if the timing of the two video signals is shifted, an arithmetic error occurs. Therefore, it is necessary to appropriately insert a register for aligning the timing in consideration of the delay time of each arithmetic processing. is there. In the present embodiment, registers 23, 24, 25, 26, 27 are inserted for that purpose. Therefore, the video signal has a delay of three pixels due to the three-stage register inserted in the path from the input to the output of the video signal in the arithmetic circuit 2. That is, the delay time of the feedback loop excluding the memory 5 is equivalent to three pixels.

Next, the overall operation will be described with reference to the timing chart for explaining the operation of the embodiment shown in FIGS. 1 and 2 shown in FIG. First, the memory 5 uses the address signal from the address counter 10 as a write and read address, and processes from the arithmetic circuit 2 output via the three-state buffer 4 according to the timing of the control pulse from the timing control pulse generation circuit 7. Write the video signal DW to the memory. Similarly, the written video signal is read out, and the arithmetic circuit 2
To the other input terminal. The register 6 holds the video signal read from the memory 5 according to the control signal from the timing control pulse generation circuit 7.

FIG. 3A shows the operation at the start timing of a certain scanning line, and FIG. 3B shows the operation at the start timing of the next scanning line. In the figure, the phases for each horizontal synchronization are shown aligned vertically in the drawing. In FIG. 3, the reference numeral attached to the left of each signal waveform matches the reference numeral attached to the signal in FIG. 1. The clock waveform shown in FIG. 3 has a period corresponding to a time corresponding to one pixel of the input video signal. In addition, in the signal waveform indicated by reference numeral WR in FIG. 3, R indicates a read cycle, and W indicates a write cycle. Each signal waveform indicates a phase with respect to the horizontal synchronization timing, and is given a number that increases with the passage of time.

In FIG. 3A, the input signal IN is delayed by three pixels as a result of the arithmetic processing and output as a processed video signal DW. The address value A of the memory 5 is an edge pulse H
Is initialized to a value of A0, and “A1, A2,
A3... ". The memory 5 is controlled by a pulse from the timing control pulse generating circuit 7, and transfers the processed video signal DW to the address A in the memory via the three-state buffer 11 at the timing W of the memory cycle WR in FIG. Write. In FIG. 3A, the signal D2 is written to the address A2, and the signal D3 is written to the address A3.

Then, after 1H, as shown in FIG. 3 (2), the address value A of the memory 5 is initialized to a value A3 obtained by adding "3" to 1H before, and thereafter "A4, A"
5, A6 ... ". The memory 5 is controlled by a pulse from the timing control pulse generation circuit 7, and reads the signal DR written 1H earlier at the timing R of the memory cycle WR in FIG. That is, the signal D3 is sent from the address A3.
The signal D4 is read from the address A4. The read signal DR is held in the register 6 and the feedback video signal RT
It returns to the arithmetic circuit 2 as N.

As shown in FIG. 3, the feedback video signal RTN to the arithmetic circuit 2 is equivalent to the delay time of the arithmetic circuit 2 by three pixels, compared to the timing of the processed video signal DW written in the memory 5 1H before. Read out earlier.

By the above operation, the first three pixels are skipped in the next horizontal scanning period in the video signal written in the memory 5 during a certain horizontal scanning period, and the phase is read out earlier by that amount. Therefore, the delay time in the memory 3 is “1H−3 pixels”, and the delay time of the entire feedback loop is exactly 1H.

Since some pixels at the beginning of the horizontal scanning period are skipped, there occurs a period in which correct arithmetic processing is not performed at the end of the horizontal scanning period, but this portion is a period during which the image is not displayed on the screen. So there is no problem.

The circuit configuration of FIG. 2 described above is an example of the configuration of the arithmetic circuit 2. If the circuit configuration is changed,
The present invention can be applied to other feedback-type arithmetic processing circuits.

Although the delay time of the arithmetic circuit 2 has been described as three pixels, the number of register insertion stages must be changed as appropriate according to the processing time of the arithmetic processing. In this case, the adder 12 may be configured to add the address value corresponding to the delay time corresponding to the number of stages to the register 11.

When serial / parallel converters are inserted before and after the memory 5 to reduce the frequency of writing and reading of the memory 5, the delay time of the arithmetic circuit 2 and the delay time of the serial / parallel converter are summed. The adder 12 may be configured to add the address value corresponding to the delay time to the register 11.

As described above, according to the first embodiment, a video signal processing circuit that performs 1H feedback type arithmetic processing using a general-purpose memory that performs writing and reading in a time-division manner can be configured. The cost can be significantly reduced as compared with a circuit configuration using a memory that performs reading independently.

(Second Embodiment) Next, a second embodiment of the present invention will be described with reference to FIG. FIG. 4 is a block diagram of a video signal processing device circuit that performs one-field type feedback operation processing. In the figure, the same components as those in FIG. 1 are denoted by the same reference numerals, and description thereof will be omitted. 1 in that the memory 13 has a capacity to store at least one field of a video signal,
Can separate the vertical sync signal in addition to the horizontal sync signal,
And edge detection circuit 15 and second address counter 1
6 is provided.

The synchronization separation circuit 14 separates a horizontal synchronization signal and a vertical synchronization signal from the input video signal IN,
The signals are output to the edge detection circuits 9 and 15, respectively. The edge detection circuits 9 and 15 detect edges of the horizontal synchronization signal and the vertical synchronization signal, respectively, and output edge pulses H and V, respectively.

The memory 13 writes and reads a video signal using the outputs of the address counters 10 and 16 as an address signal. The output of the address counter 10 is an address corresponding to a pixel position in the horizontal direction, as in the embodiment of FIG. On the other hand, the second address counter 16 initializes the address using the edge pulse V of the vertical synchronization signal from the edge detection circuit 15 as a timing signal, and thereafter, converts the edge pulse H of the horizontal synchronization signal from the edge detection circuit 9 into an address. The address is incremented by "1" as a timing signal. The address signal of the address counter 10 is supplied to the memory 13. That is, the second address counter 16 generates an address corresponding to a pixel position in the vertical direction.

By the way, in the embodiment of FIG. 1, a constant value is added to the value of the register 11 every 1H, but in this embodiment, a constant value is added to each field. This means that the timing at which the register 11 updates the value may be set for each field. This fixed value is an address value corresponding to canceling out the delay time required for processing excluding the delay time of the memory 13 in the feedback loop, as in the embodiment of FIG. As in the case of the embodiment, three pixels are used.

With such a configuration, according to the embodiment shown in FIG.
The first three pixels are skipped in each horizontal scanning period of the next field in the video signal written in the next field, and the phase is read out earlier by that amount. Therefore, the delay time in the memory 13 is “one field−3 pixels”, and the delay time of the entire feedback loop is exactly one field.

Since the first pixel of each horizontal scanning period is skipped, a period occurs in which correct arithmetic processing is not performed at the end of each horizontal scanning period. However, since this portion is a period during which the image is not displayed on the screen. No problem.

As described above, according to the second embodiment, a video signal processing circuit that performs one-field feedback type arithmetic processing using a general-purpose memory that performs writing and reading in a time-sharing manner can be configured. The cost can be significantly reduced as compared with a circuit configuration using a memory that performs writing and reading independently.

[0038]

According to the present invention, a video signal processing circuit for performing 1H or 1-field feedback type arithmetic processing using a general-purpose memory which performs writing and reading in a time-division manner can be constructed. The cost can be significantly reduced as compared with a circuit configuration using a memory performed by a conventional method.

[Brief description of the drawings]

FIG. 1 is a circuit block diagram showing a first embodiment of the present invention.

FIG. 2 is a circuit illustrating an example of an arithmetic circuit according to the first embodiment of the present invention.

FIG. 3 is a timing chart for explaining operation timing according to the first embodiment of the present invention.

FIG. 4 is a circuit block diagram showing a second embodiment of the present invention.

[Explanation of symbols]

 Reference Signs List 1 input terminal 2 arithmetic circuit 3 output terminal 4 three-state buffer 5, 13 memory 6 register 7 timing control pulse generation circuit 8, 14 synchronization separation circuit 9, 15 edge detection circuit 10 address counter 11 register 12 adder 16 second address counter

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Hideo Shikidani 1410 Inada, Hitachinaka-shi, Ibaraki Pref. Hitachi, Ltd. Visual Information Media Division

Claims (5)

[Claims] 1. An arithmetic unit for inputting two video signals and performing a predetermined arithmetic process for each pixel, a storage unit for storing the video signal processed by the arithmetic unit, and a writing operation and reading of the storage unit Control means for controlling the operation;
Address generation means for generating an address of the storage means, wherein the calculation means performs a feedback calculation process with one input as a video signal input from the outside and the other input as a video signal read from the storage means The control means reads the video signal stored at the address generated by the address generation means from the storage means, and then writes the video signal processed by the arithmetic means at the same address. The address generating means generates an address sequence by sequentially updating the address for each pixel of the video signal,
A feedback-type video signal processing apparatus, wherein the phase of the address sequence is shifted by at least the number of pixels corresponding to the delay time of the feedback operation processing every time one horizontal scanning period elapses. 2. The method according to claim 1, wherein the address generating means updates the address sequentially from a preset initial value, and updates the initial value each time a horizontal synchronization signal is input, thereby changing the phase of the address string. 2. The video signal processing device of the feedback type according to claim 1, wherein shifting is performed. 3. An arithmetic unit for inputting two video signals and performing a predetermined arithmetic process for each pixel, a storage unit for storing the video signal processed by the arithmetic unit, and a writing operation and reading of the storage unit. Control means for controlling the operation;
Address generation means for generating an address of the storage means, wherein the calculation means performs a feedback calculation process with one input as a video signal input from the outside and the other input as a video signal read from the storage means The control means reads the video signal stored at the address generated by the address generation means from the storage means, and then writes the video signal processed by the arithmetic means at the same address. The address generating means generates an address sequence by sequentially updating the address for each pixel of the video signal,
A feedback-type video signal processing apparatus, wherein the phase of the address string is shifted by at least the number of pixels corresponding to a delay time related to the feedback operation processing every time one vertical scanning period elapses. 4. An address generating means for initializing an address corresponding to a pixel position in a horizontal direction to an initial value in synchronization with a horizontal synchronization signal, and an address generation means for setting an address in a vertical pixel position in synchronization with a vertical synchronization signal. Means for initializing a corresponding address to an initial value, and each time one vertical scanning period elapses,
4. The method according to claim 3, wherein an initial value of an address corresponding to the pixel position in the horizontal direction is increased or decreased by the number of pixels.
2. The feedback type video signal processing device according to 1. 5. The address generating means includes means for increasing or decreasing a write and read address corresponding to the horizontal pixel position from the initial value for each write and read operation; Write and read addresses corresponding to the pixel positions of
Means for increasing or decreasing from the initial value for each writing and reading operation for one horizontal scanning period, and for each elapse of one vertical scanning period, the initial value of the address corresponding to the pixel position in the horizontal direction is 4. A feedback type video signal processing apparatus according to claim 3, further comprising: means for increasing or decreasing by an amount corresponding to the delay time of the arithmetic means.