JPH11145837A - A/d converter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a high-accuracy A/D converter which is not unaffected by the output timing of a quantizer by taking in the output of the quantizer into a latch circuit and using the output of the latch circuit as a feedback signal to a D/A converter. SOLUTION: This device is provided with an input circuit 11, selector circuit 12, integrator 13, quantizer 14, D/A converter 15 and latch circuit 17, the output of the quantizer 14 is latched arbitrarily by the latch circuit 17 and the latch output is fed back as the feedback signal, so that the D/A conversion and integration of the feedback signal can always be started as the same timing, without depending on the change of output timing from the quantizer 14 caused by the potential difference of an input signal.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an A / D (analog / digital) converter for converting an analog signal into a digital signal, and more particularly to a .DELTA..SIGMA.-type A having a circuit for feeding back an output from a quantizer to an input side. / D converter.

[0002]

2. Description of the Related Art As one of A / D converters, a ΔΣ type A
An A / D conversion device using a / D conversion circuit has been proposed. A conventionally proposed A / D converter of this type will be described with reference to FIG.

FIG. 4 is a block diagram showing a configuration of a conventional A / D converter. In FIG. 4, 41 is an input circuit,
42 is a selector circuit, 43 is an integrator, 44 is a quantizer,
45 is a D / A converter and 46 is a selection signal.

In the input circuit 41, sampling of an input signal is performed at each sampling cycle. The input sampling signal from the input circuit 41 is used as one input,
In the selector circuit 42 which receives the feedback signal from the D / A converter 45 as the other input, one of the signals is selectively output by the selection signal 46 of the same frequency clock as the sampling frequency of the input circuit 41. The integrator 43 receives the selected output from the selector circuit 42 as input, performs cumulative addition, and outputs the result to the quantizer 44. And the quantizer 44
, The output from the integrator 43 is converted into a 1-bit digital signal, output as a digital output signal, and fed back to the D / A converter 45. The D / A converter 45 converts the digital output signal fed back from the quantizer 44 into an analog signal, and then feeds it back to the other input of the selector circuit 42.

In the A / D converter having such a configuration, either the input sampling signal from the input circuit 41 or the feedback signal from the D / A converter 45 is selected by the selector circuit 42, and the selection is performed. The output thus obtained is integrated by the integrator 43. Therefore, in the integrator 43, the input sampling signal and the feedback signal can be time-divisionally processed within one sampling period, so that an analog adder for adding the input sampling signal and the feedback signal is unnecessary. ing.

FIG. 5 shows an operation timing chart of each component in the conventional A / D converter as described above. In FIG. 5, T _S10 , T _S11 , T _S12 , T _S13 , T
_S14 is the operation timing time, ΔT ₀ and ΔT ₁ are the time from the start of quantization to the output of the quantized signal, in other words, from the start of quantization to the start of D / A conversion and integration of the feedback signal. Indicates time.

The operation of the conventional A / D converter configured as described above will be described below with reference to FIGS.

[0008] Sampling at each sampling cycle in the input circuit 41 is defined as input sampling (0), (1),
In the case of (2), the operation timing of each component will be described using, for example, input sampling (1). 1) At the timing of T _S11 , the input sampling (1) sampled by the input circuit 41 is used as the selector circuit. It is selected by 42 and input to the integrator 43.

2) In the integrator 43, the integration of the input sampling (1) selected by the selector circuit 42 is performed for a predetermined time (T _S12 -T _S11 ).

3) At the timing of T _S12 , quantization of the output from the integrator 43 is started by the quantizer 44, and the quantization of the input (1) is performed for a predetermined time (T _S13 −T _S12 ).
Done. At the same time, the switching of the selector circuit 42 is performed at the timing of T _S12 , and the feedback signal (1) fed back via the D / A converter 45 is selected.

4) In the quantizer 44, Δ
T ₁ delayed digital output signal is outputted. The delay of this output is the time required to determine the “H” and “L” levels of the signal, and depends on the potential difference of the signal input to the quantizer 44. The delay is short if the potential difference is large and long if the potential difference is small. . In the D / A converter 45 having this output as an input, the D / A conversion of the feedback signal (1) is started with a delay of ΔT ₁ . Therefore, the integration of the feedback signal (1) in the integrator 43 is also started with a delay of ΔT ₁ .

5) At the timing of T _S13 , the selector circuit 42 is switched to select the input sampling signal (2) side, and the quantization of the input (1) by the quantizer 44 and the feedback by the D / A converter 45. The D / A conversion of the signal (1) and the integration of the feedback signal (1) by the integrator 43 are completed.

6) On the other hand, in the input circuit 41, sampling of the next input signal is started at the timing of T _S12 , and the input sampling (2) is performed for a predetermined time (T _S13 −T _S12 ).

As is apparent from the above, the integrator 43 has a period in which the feedback signal is integrated and a period in which the input sampling signal is integrated within one sampling period, and is processed by time division.

When the analog input signal of the A / D converter shown in FIG. 4 is X, the digital output signal is Y, and the quantization error generated by the quantizer 44 is Vq, the relationship between input and output is described by a Z function. It becomes like the following formula.

[0016] The Y = X + (1-z -1) Vq digital output signal in this manner, including but quantization errors Vq as the error in addition to the analog input signal components, the primary differential characteristic (1-z ^-1) , The noise due to Vq decreases as the frequency decreases, and a wide dynamic range can be obtained even with only 1-bit quantization.

In order to obtain a wider dynamic range, the sampling period is set shorter (the sampling frequency is higher) than the digital output signal to be obtained, and the A / D
The conversion may be performed, and digital processing may be performed by a digital filter in the subsequent stage so that only the low frequency region of the output is used. For this reason, the A / D conversion of this method is also called an oversampling method, and is an indispensable technique especially in the field of digital audio in recent years.

[0018]

However, in the above-described conventional configuration, the quantizer 44 has a characteristic that the determination time varies depending on the potential difference of the input signal. The time required for outputting a quantized digital signal from the input signal varies depending on the potential difference of the input signal. Therefore, the times ΔT ₀ and ΔT ₁ until the start of the D / A conversion of the D / A converter 45 that receives the quantization output from the quantizer 44 as input are changed by the potential difference of the signal input to the quantizer 44. In addition, the time for integrating the feedback signal in the integrator 43 also changes.

That is, as shown in FIG. 5, for example, the quantization period of the input (1) is a fixed time (T _S13 -T _S12 ), and the D / A conversion of the feedback signal (1) is performed at the timing of T _S13. And the integration ends. Therefore, if the output start time from the quantizer 44 changes, the time from the start of the D / A converter 45 to the end of the D / A conversion to the end thereof, and the integrator 43 starting the integration. From the end to the end (the amount of feedback) changes. If the amount of feedback changes, components not included in the original signal are mixed into noise, which causes a problem of deterioration of A / D conversion characteristics such as generation of harmonic distortion and deterioration of dynamic range. is there.

FIG. 6 shows an output waveform diagram of a quantizer and an integrator in a conventional A / D converter. In FIG. 6, T _A is a quantization start time, T ₀ is a time at which input sampling (0) starts to be quantized and output, T ₁ is a time at which input sampling (1) starts to be quantized and output, and T T _B is the end time of quantization, B is the feedback amount of input sampling (0), and C is the feedback amount of input sampling (1). The input signal in this case indicates a case where the potential difference is smaller in the input sampling (1) than in the input sampling (0). D / A converter fed-back feedback signal via a (0), integral (1), the input sampling is started in association with the time T _0, T _1, which starts to be output after being quantized, the T _B It ends at the timing. Note that the output waveform of the integrator includes ringing generated by the settling time of the operational amplifier which is a component of the integrator, load, parasitic resistance, and parasitic capacitance.

As apparent from FIG. 6, when the output start time from the quantizer changes from T ₀ to T ₁ due to the potential difference of the signal input to the quantizer, the feedback signals (0), ( 1) integration even start time is changed from T ₀ to T _1, the integrator output waveform changes the feedback amount of the integral end T _B because it contains ringing from B to C. This change in the amount of feedback affects the A / D conversion characteristics as described above and causes deterioration.

The present invention has been made to solve the above-mentioned conventional problems, and has the same timing as that of the feedback signal at the same timing regardless of the time until the signal is output from the quantizer.
It is an object of the present invention to provide a high-precision A / D converter capable of starting / A conversion and integration and having a constant feedback amount.

[0023]

An A / D converter according to the present invention includes an integrator for integrating an input signal and a feedback signal in a time-division manner, a quantizer for quantizing an output of the integrator, A latch circuit for latching an output of the quantizer with an arbitrarily set latch signal; and a D / A converter for D / A converting the output of the latch circuit, wherein the output of the D / A converter is fed back. The signal is fed back to the integrator as a signal.

According to this configuration, since the output of the quantizer is arbitrarily latched by the latch circuit and the latch output is fed back as a feedback signal, it does not depend on the output change from the quantizer due to the potential difference of the input signal. The D / A conversion and integration of the feedback signal can always be started at the same timing. Therefore, since the D / A conversion time of the feedback signal by the D / A converter and the integration time of the feedback signal by the integrator are always constant, noise components due to a change (error) in the feedback amount as in the related art are mixed. Is prevented, and generation of harmonic distortion and deterioration of the dynamic range can be suppressed.

The above A / D converter is provided with a selector circuit having an input signal as one input and a feedback signal from the D / A converter as the other input. Either one can be selected and output to the integrator.

[0026]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing a configuration of an A / D converter according to the present embodiment. In FIG. 1, 11
Is an input circuit, 12 is a selector circuit, 13 is an integrator, 14
Is a quantizer, 15 is a D / A converter, 16 is a selection signal, 1
7, a latch circuit; and 18, a latch signal.

In the input circuit 11, sampling of an input signal is performed for each sampling cycle. The input sampling signal from the input circuit 11 is used as one input,
In the selector circuit 12 which receives the feedback signal from the D / A converter 15 as the other input, one of the signals is selectively output by the selection signal 16 of the same frequency clock as the sampling frequency of the input circuit 11. The integrator 13 receives the selected output from the selector circuit 12 as an input, performs cumulative addition, and outputs the result to the quantizer 14. And the quantizer 14
, The output from the integrator 13 is converted into a 1-bit digital signal, and the digital output signal is output to the latch circuit 17. In the latch circuit 17, the output from the quantizer 14 is a latch signal (latch clock) 1 arbitrarily set.
8 and outputs the fetched data as a digital output signal.
Return to. The D / A converter 15 converts the digital output signal fed back from the latch circuit 17 into an analog signal and then feeds it back to the other input of the selector circuit 12.

FIG. 2 shows an operation timing chart of each component in the A / D converter of the present invention as described above. In FIG. 2, T _S0 , T _S1 , T _S2 , T _S3 , T _S4 are operation timing times, ΔT ₀ , ΔT ₁ are times from the start of quantization until a quantized signal is output, and ΔT is quantization. It indicates the time from the start until the latch circuit 17 latches the output from the quantizer 14 and outputs the latch data, in other words, the time from the start of quantization to the start of D / A conversion and integration of the feedback signal. .

The operation of the A / D converter of the present invention configured as described above will be described below with reference to FIGS.

The sampling at each sampling period in the input circuit 11 is defined as input sampling (0), (1),
In the case of (2), the operation timing of each component will be described using, for example, input sampling (1). 1) At the timing of T _S1 , the input sampling (1) sampled by the input circuit 11 is selected by the selector circuit. 1
2 and input to the integrator 13.

2) In the integrator 13, the integration of the input sampling (1) selected by the selector circuit 12 is performed for a predetermined time (T _S2 −T _S1 ).

3) At the timing of T _S2 , the quantizer 14 starts quantizing the output from the integrator 13,
The quantization of the input (1) is performed for a predetermined time (T _S3 −T _S2 ). At the same time, the selector circuit 12 is switched at the timing of T _S2 , and the feedback signal (1) fed back from the D / A converter 15 is selected.

4) In the quantizer 14, ΔΔ
T ₁ delayed digital output signal is outputted.

5) The latch circuit 17 latches the output data from the quantizer 14 at the edge of the latch signal 18 when a predetermined time ΔT has elapsed from the start of quantization, and outputs the latch data. Also in the D / A converter 15 having this output as an input, the D / A conversion of the feedback signal (1) is started with a delay of ΔT. The integration of the feedback signal (1) in the integrator 13 is also started with a delay of ΔT.

As described above, the integrator 13 has a period in which the feedback signal is integrated and a period in which the input sample signal is integrated within one sampling period, and is processed by time division.

6) At the timing of T _S3 , the selector circuit 1
2 is switched to select the input sampling (2) side, the quantization of the input (1) by the quantizer 14 and D
The D / A conversion of the feedback signal (1) by the / A converter 15 and the integration of the feedback signal (1) by the integrator 13 are completed.

7) On the other hand, the input circuit 11 starts sampling the next input signal at the timing of T _S2 , and the input sampling (2) is performed for a predetermined time (T _S3 −T _S2 ).

As is clear from the above, the latch circuit 17
Latches the output data of the quantizer 14 by the latch signal 18 after the elapse of ΔT from the start of the quantization of the quantizer 14 and outputs the latched data. This latch circuit 17
The D / A converter 15 starts the D / A conversion by the output signal from, and the time ΔT ₀ , ΔT ₁ until the digital output signal starts to be output from the quantizer 14 varies depending on the potential difference of the input signal. The start time of D / A conversion is always constant (after ΔT has elapsed from the start of quantization). Therefore, since the integrator 13 also starts integration after elapse of ΔT from the start of quantization, the integration time of the feedback signal is always constant.

FIG. 3 shows an output waveform diagram of a quantizer, a latch circuit, and an integrator in the A / D converter of the present invention. In FIG. 3, T _A is the quantization start time, T _B is the quantization end time, T ₀ is the time at which input sampling (0) starts to be quantized and output, and T ₁ is the input sampling (1) is at the quantization time. T ₂ is the time at which input sampling (2) begins to be quantized and output, and T _L is the clock input time of the latch signal, in other words, the start time of the latch output. This is the integration start time of the feedback signal.

In the quantizer 14, when the potential difference of the input signal is large, the time from the start of the quantization to the start of the output of the digital signal is short, for example, the output start time is T ₀ , and the voltage difference of the input signal is Becomes smaller, the time until the digital signal starts to be output becomes longer, and the output start time becomes T ₁ , T ₂ .

In the latch circuit 17, the latch signal 1
8, the output data from the quantizer 14 is latched (determined) at the rising edge of the clock signal 8. Therefore, the clock input time _TL of the latch signal 18 is set to the time when the latch circuit 17 starts outputting the latch data. Become. further,
After this latch output becomes a feedback signal and is D / A converted,
Since integration is performed by the integrator 13, the integration start time is also T _L.

According to the present embodiment as described above, even if the output start time of the digital signal from the quantizer 14 changes, for example, between T ₀ and T ₁ due to the potential difference of the input signal, the feedback Since the start time of the D / A conversion and integration of the signal is determined by the clock input time _TL of the latch signal of the latch circuit 17, it is necessary to always start the D / A conversion and integration of the feedback signal at a constant timing (T _L ). Can be.

When the output start time of the digital signal from the quantizer 14 becomes T ₂ , the start time is later than the clock input time T _L of the latch signal 18.
The latch circuit 17 latches the undetermined output data. When such undetermined data is latched, it is unclear which level of the latch output of the latch circuit 17 is 'H' or 'L', and a latch different from the output of the quantizer 14 is latched. there is a possibility. However, the reason why it takes a long time from the start of quantization to the output of the digital signal is that the potential difference of the signal input to the quantizer is very small, and the characteristics are not affected even if the level of the feedback signal is reversed. There is no significant effect. Therefore,
When the latch circuit 17 latches the undetermined data,
For example, an “L” level may be output.

The output waveform of the integrator 13 includes the settling time of the operational amplifier and ringing generated by the load, the parasitic resistance, and the parasitic capacitance. The integration start time of the integrator 13 is _TL and is always constant. Therefore, the feedback amount is always a constant amount A.

As described above, according to the present invention, the D / A conversion and integration of the feedback signal are performed irrespective of the time at which the digital signal from the quantizer starts to be output. Therefore, it can be started at a certain timing. As a result, the D / A conversion time of the feedback signal by the D / A converter and the integration time of the feedback signal by the integrator are always constant, and the feedback amount is constant. Since the feedback amount is constant, noise components due to a change (error) in the feedback amount as in the related art can be prevented, and generation of harmonic distortion and deterioration of the dynamic range can be suppressed. A / D conversion characteristics with high accuracy can be obtained.

[0047]

As described above, according to the present invention, since the feedback signal is controlled by the latch circuit, D / A conversion and integration of the feedback signal can always be started at the same timing. Therefore, it is possible to realize an A / D converter having a highly accurate conversion characteristic that does not depend on the potential difference of the input signal to the quantizer.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an A / D converter according to an embodiment of the present invention.

FIG. 2 is an operation timing chart of each component in the A / D converter of the present invention.

FIG. 3 is an output waveform diagram of a quantizer, a latch circuit, and an integrator in the A / D converter according to the present invention.

FIG. 4 is a block diagram showing a configuration of a conventional A / D converter.

FIG. 5 is an operation timing chart of each component in a conventional A / D converter.

FIG. 6 is an output waveform diagram of a quantizer and an integrator in a conventional A / D converter.

[Explanation of symbols]

 Reference Signs List 11 input circuit 12 selector circuit 13 integrator 14 quantizer 15 D / A converter 16 selection signal 17 latch circuit 18 latch signal

Claims (2)

[Claims] An integrator for integrating an input signal and a feedback signal in a time-sharing manner, a quantizer for quantizing an output of the integrator,
A latch circuit for latching the output of the quantizer with an arbitrarily set latch signal;
And a D / A converter for performing A / A conversion, wherein an output of the D / A converter is fed back to the integrator as a feedback signal. 2. A selector circuit having an input signal as one input and a feedback signal from a D / A converter as another input, wherein the selector circuit selects either the input signal or the feedback signal. 2. The A / D conversion device according to claim 1, wherein the A / D converter outputs the result to an integrator.