JPH11145328A - Flip-chip mounting substrate and flip-chip mounting inspection method - Google Patents

Abstract

(57) Abstract: The present invention relates to a flip-chip mounting board and a flip-chip mounting inspection method in which a mounted element in which projecting electrodes are arranged in a staggered manner is flip-chip mounted, and a high density of the mounted element. It is an object to improve the accuracy of mounting inspection while coping with miniaturization and miniaturization. A flip-chip mounting substrate in which a semiconductor chip having a plurality of bumps arranged in a staggered manner is flip-chip mounted on a plurality of wirings corresponding to the semiconductor chip, a pad portion is provided on the wiring. 1st and 2nd extension part 3
Form 8,40. The pad portions 36 are arranged in a zigzag pattern so as to correspond to the bumps 52, and are configured to have a sufficient area and shape to allow the bumps 52 to be flip-chip mounted. In addition, the first extension portion 38 has a shape narrower than the width of the pad portion 36 so as not to interfere between adjacent wirings. Further, the second extending portion 40 has a linear reference side edge 42 continuously extending from the outer peripheral edge of the pad portion 36 in the width direction.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a flip-chip mounting board and a flip-chip mounting inspection method, and more particularly, to a flip-chip mounting board on which elements to be mounted having projecting electrodes arranged in a staggered manner are flip-chip mounted. The present invention relates to a flip chip mounting inspection method. 2. Description of the Related Art In recent years, the density and size of semiconductor chips have been rapidly increasing, and accordingly, the number of connection terminals provided on a semiconductor chip has increased, and the pitch between terminals has tended to be narrower. For this reason, by arranging the connection terminals in a staggered manner, it has been practiced to cope with the increase in the number of pins while maintaining a relatively wide pitch between adjacent connection terminals.

Further, in order to reduce the size of an electronic device on which a semiconductor chip is mounted, it is necessary to reduce a mounting space when mounting the semiconductor chip on a mounting substrate. For this reason, bump electrodes (bumps) are used as connection terminals of the semiconductor chip, and the semiconductor chip is flip-chip mounted on a mounting substrate. Further, in the mounting substrate on which the semiconductor chip is mounted, it is necessary to reduce the pitch of the wiring to which the bumps are bonded, and in order to enable reliable flip-chip mounting, the bonding positions of the bumps must be reduced. It is necessary to secure a predetermined bonding area.

Further, after bonding the bump to the mounting substrate,
It is necessary to inspect whether or not the bumps are properly flip-chip mounted on the mounting substrate. However, in the case of flip-chip mounting, since the leads do not extend outside the semiconductor chip, X-rays are used. A fluoroscopic examination is being performed.
Therefore, in order to increase the reliability of flip-chip mounting, it is necessary to perform a fluoroscopic inspection using this X-ray with high accuracy.

[0004]

FIG. 4 shows a state in which a semiconductor chip 8 is flip-chip mounted on a conventional flip-chip mounting substrate 2. As shown in FIG. 5, the semiconductor chip 8 has a plurality of bumps 10 arranged on its mounting surface in a peripheral shape. The bump 10 is a stud bump and is formed using a wire bonding technique.

The flip-chip mounting substrate 2 has a wiring 6 formed in a predetermined pattern on a resin or ceramic substrate main body. A predetermined range including a portion of the wiring 6 to be joined to the bump 10 is a linear pattern. Therefore, the side edge is a straight side edge (hereinafter, this side edge is referred to as a reference side edge 14). As shown in FIG. 2, the semiconductor chip 8 is flip-chip mounted on the flip-chip mounting substrate 2. In this mounted state, the bumps 10 are fixed to the wiring 6 by a conductive adhesive 12. Thus, the semiconductor chip 8 is electrically and mechanically connected to the flip-chip mounting substrate 2.

By the way, in the related art where the density of the semiconductor chips 8 has not been increased in recent years, the number of bumps provided on the semiconductor chip 8 is small, and the pitch P1 between adjacent bumps can be widened. Therefore, the wiring 6 formed corresponding to the pitch P1 between the bumps also has a large pitch P1.
The width W1 of each wiring 6 can be set sufficiently large with respect to the diameter of the bump 10.

The reason why the width W1 of the wiring 6 is made wider than the diameter of the bump 10 is as follows. That is, when the semiconductor chip 8 is flip-chip mounted on the flip-chip mounting substrate 2, the mounting process is performed after positioning the semiconductor chip 8 and the flip-chip mounting substrate 2, but this positioning is necessarily performed. An error occurs.

Accordingly, the width W1 of the wiring 6 is
If the diameter is the same, the probability of mounting failure increases and the reliability of mounting decreases. Therefore, in order to absorb the above error, the width dimension W1 of the wiring 6 is set to be larger than the diameter dimension of the bump 10, so that the bump 10 and the wiring 6 can be securely joined in the error range. Further, conventionally, as described above, the pitch P1 between the bumps is used.
Therefore, even if the wiring 6 is formed with a width W1 sufficient to absorb the above error over the entire wiring, no interference occurs between adjacent wirings.

However, due to the influence of disturbance or the like, the semiconductor chip 8 may be rarely mounted on the flip-chip mounting substrate 2 beyond the error range due to the influence of disturbance or the like. For this reason, conventionally, it has been inspected whether the semiconductor chip 8 is mounted on the flip-chip mounting substrate 2 properly (that is, within the error range). Here, a conventional flip chip mounting inspection method will be described with reference to FIG.

In the flip chip mounting, the semiconductor chip 8
In this structure, the bumps 10 provided on the mounting surface are bonded to the flip-chip mounting substrate 2 and mounted, so that no leads or the like exist around the semiconductor chip 8 in the mounted state. For this reason, in the mounting inspection in flip-chip mounting, the bonding position between the wiring 6 and the bump 10 is perspectively imaged using X-rays, and the quality of the mounting is determined from the fluoroscopic image. In addition, the quality is determined by the inspector observing the fluoroscopic imaging.

FIGS. 7A to 7D show the wiring 6 and the bump 1.
0 shows various implementation modes. FIG. 7A shows a state in which the bump 10 is most appropriately mounted (joined) to the wiring 6. In the perspective image in this mounting state, the perspective image of the bump 10 (hereinafter, referred to as a bump image 10A) is located at the center of the perspective image of the wiring 6 (hereinafter, referred to as the wiring image 6A). 6 can be determined.

FIG. 7B shows that the bumps 10 are slightly displaced in the direction of arrow X in FIG.
3 shows a state in which they are joined. In this state, a part of the bump 10 protrudes from the wiring 6.
In general, the bonding state between the wiring 6 and the bump 10 is determined by the overlapping area of the bump image 10A and the wiring image 6A.
If the area of A is half or more, it is determined that the area is appropriate. Therefore, the inspector determines from the perspective image whether or not the overlapping area of the bump image 10A and the wiring image 6A is at least half the area of the bump image 10A.

Specifically, the inspector determines the reference side edge 1 of the wiring 6.
4 (hereinafter, referred to as a reference side image 14A), and the bump image 10
The quality is determined by observing how much A protrudes. Therefore, in the case shown in FIG. 7B, it can be determined that the bonding state between the wiring 6 and the bump 10 is appropriate.

FIG. 7C shows a state in which the bumps 10 are further displaced slightly in the direction of the arrow X in the figure and are joined to the wiring 6 as compared with the proper state in FIG. 7B. In this state, the bump 10 protrudes greatly from the wiring 6. In the example shown in FIG. 7C, the reference side edge image 14A
On the other hand, the bump image 10A protrudes more than half, so that the inspector can determine that the bonding state between the wiring 6 and the bump 10 is defective.

FIG. 7D shows a state in which the bumps 10 are slightly displaced in the direction of the arrow X in the figure, compared to the proper state in FIG. 7C. In this state, the bump 10 is completely separated from the wiring 6, so that the inspector can determine that the bonding state between the wiring 6 and the bump 10 is defective. As described above, in the flip chip mounting inspection, the inspector makes a pass / fail judgment based on the fluoroscopic image.
Since the reference side edge image 14A serving as a criterion for determination is present in the perspective image, the quality is good even in the state where the bump image 10A protrudes from the reference side edge image 14A, for example, in FIGS. 7B and 7C. Was able to be determined.

With the rapid increase in the density and miniaturization of semiconductor chips in recent years, the number of connection terminals provided on the semiconductor chip has increased, and the pitch between terminals has tended to be reduced. For this reason, in the structure in which the bumps 10 are arranged in a line as shown in FIG. 5, the pitch between the bumps is narrowed, and interference between adjacent bumps (for example, adjacent bumps bridge at the time of mounting). Began to occur. Therefore, as a structure for solving this, the semiconductor chip 16 shown in FIG. 8 has been proposed and put to practical use.

The semiconductor chip 16 shown in FIG.
It is said that 8 are arranged in a staggered manner. With this configuration, the pitch P2 between the bumps in the row direction of the bumps 18 can be narrower than the pitch P1 between the bumps of the semiconductor chip 8 shown in FIG. 5 (P2 <P1).
Therefore, the bumps 18 can be arranged at a high density, and the number of pins and the size of the semiconductor device 16 can be reduced. Further, the separation distance between the adjacent bumps is the distance indicated by the arrow P3 in the figure, and can be made wider than the pitch P2 between the bumps (P3 <P2). Therefore, bump 1
8 are arranged in a staggered manner, so that the pitch P1 between the bumps is obtained.
Can be narrowed, and the occurrence of interference between adjacent bumps can be prevented.

As described above, by forming the bumps 18 in a zigzag pattern, the flip-chip mounting substrate on which the semiconductor chip 16 is mounted needs to correspond to this. FIG.
Shows a flip chip mounting substrate 20 on which the semiconductor chips 16 in which the bumps 18 are arranged in a staggered manner are mounted. As shown in the figure, wirings 22 are formed on the substrate body 4 of the flip-chip mounting substrate 20 so as to correspond to the pitch P2 between the bumps 18. Also, since the pitch P2 between the bumps is smaller than the pitch P1 between the bumps of the semiconductor chip 8 shown in FIG. 5, (P2 <P
1) The width dimension W3 of the wiring 22 cannot be set as wide as the width dimension W1 of the wiring 6 provided on the flip-chip mounting board 2 shown in FIG. 6 and is a narrow pattern (W3 < W1).

However, as described above, in order to absorb an error that is inevitably generated when the semiconductor chip 16 is flip-chip mounted on the flip-chip mounting substrate 20, the wiring 22 is also required to have a size corresponding to the diameter of the bump 18. It is necessary to increase the width of the wiring 22. For this reason, a pad portion 24 having a width dimension W2 larger than the diameter dimension of the bump 18 is formed on the wiring 22, so that the above-described error can be absorbed. The pad portion 24 has a substantially elliptical shape in order to absorb the displacement of the bump 18 in various directions due to the error.

With this configuration, the distance between the adjacent wirings 22 can be made to correspond to the pitch P2 between the bumps, which is reduced in pitch, and the positioning error at the time of mounting can be absorbed. By forming the pad portion 24 as described above, the wiring 22 has a portion extending from one of the pad portions 24 (hereinafter, referred to as a first extending portion 26),
It has a portion extending from the other side of the pad portion 24 in a direction opposite to the extending direction of the first extending portion 26 (hereinafter, a second extending portion 28).

[0021]

Subsequently, the semiconductor chip 16 having the above-described structure is mounted on the flip-chip mounting substrate 20.
A flip-chip mounting inspection performed after mounting on a semiconductor device will be described. Also in this flip chip mounting inspection, the bonding position between the wiring 22 and the bump 18 is perspectively imaged using X-rays, and the quality of the mounting is determined from the fluoroscopic image. In addition, the quality is determined by the inspector observing the fluoroscopic imaging.

FIGS. 10A to 10D show various mounting modes of the wiring 22 and the bump 18. FIG. 10 (A)
Shows a state in which the bump 18 is most appropriately mounted (joined) to the wiring 22. In the perspective image in this mounting state, a perspective image of the bump 18 (hereinafter, bump image 18A)
Is a perspective image of the wiring 22 (hereinafter referred to as a wiring image 22A).
Therefore, it can be determined that the bump 18 is securely joined to the wiring 22.

FIG. 10D shows a state in which the bump 18 is largely displaced in the arrow X direction in the figure, and the bump 18 is completely separated from the wiring 22. Therefore, the inspector can determine from the perspective image that the bonding state between the wiring 22 and the bump 18 is defective. On the other hand, FIG. 10B shows a state in which the bump 18 is displaced in the direction of the arrow X in the figure and is bonded to the wiring 22 as compared with the optimum state in FIG. ) Is for FIG.
3 shows a state in which the bump 18 is further displaced in the direction of the arrow X in the figure and is further joined to the wiring 22.

In each of these states, a part of the bump 18 protrudes from a see-through image of the pad portion 24 (hereinafter, referred to as a pad portion image 24A). Therefore, the inspector observes each of the fluoroscopic images to obtain the bump image 1.
It is determined whether or not the overlapping area of the pad image 8A and the pad image 24A (wiring image 22A) is at least half the area of the bump image 18A.

However, in the configuration in which the pad portion 24 is formed on the wiring 22, the width dimension W3 of the first and second extension portions 26 and 28 is smaller than the width dimension W2 of the pad portion 24. In addition, the quality cannot be determined based on the perspective image of the side edge 29 of the second extending portions 26 and 28 (hereinafter, referred to as a side edge image 29A). That is, the pass / fail judgment needs to be performed based on a perspective image of the outer peripheral edge 25 of the pad portion 24 (hereinafter, referred to as a pad outer peripheral image 25A). However, the shape of the pad outer edge image 25A is substantially elliptical, and thus the pad outer edge image 25A having a curved shape is thus obtained.
It is difficult to determine the overlapping area of the bump image 18A and the wiring image 22A on the basis of the above, and there is a problem that the accuracy of the inspection is reduced.

The present invention has been made in view of the above-mentioned points, and has been made to cope with high density and miniaturization of mounted elements.
It is another object of the present invention to provide a flip-chip mounting substrate and a flip-chip mounting inspection method capable of improving the accuracy of the mounting inspection.

[0027]

Means for Solving the Problems In order to solve the above problems, the present invention is characterized by taking the following means. According to the first aspect of the present invention, a mounted element having a plurality of projecting electrodes arranged in a staggered manner is flip-chip mounted on a plurality of wirings formed so as to correspond to the projecting electrodes formed on the substrate body. In the flip-chip mounting substrate, the wiring is arranged in a staggered manner corresponding to the protruding electrodes, and a pad portion having a sufficient area and shape for the protruding electrodes to be flip-chip mounted, A first extending portion extending from one of the pad portions and having a shape narrower than a width dimension of the pad portion so as not to interfere between adjacent wirings; and a first extending portion extending from the other of the pad portions. And a second extension having a linear reference side edge extending continuously from the widthwise outer peripheral edge of the pad portion and facing the extension portion. .

According to a second aspect of the present invention, the mounting state of the bump electrode provided on the mounted element with respect to the pad formed on the flip-chip mounting substrate according to the first aspect is determined from a radiographic image. In the flip-chip mounting inspection method to inspect, based on the position of the reference side edge in the radiographic image, by determining the overlapping state of the image of the projecting electrode and the image of the wiring,
It is characterized in that the quality of the connection between the bump electrode and the pad portion is determined.

Each of the above means operates as follows. According to the first aspect of the present invention, the pad portion is formed on the wiring,
The pads are arranged in a zigzag pattern corresponding to the protruding electrodes, and the protruding electrodes have a sufficient area and shape to be flip-chip mounted. The positioning error that occurs when mounting on a board can be absorbed by the pad section. Therefore, it is possible to improve the throughput when the mounted element is mounted on the flip-chip mounting substrate.

Also, the first portion is opposed to the pad portion.
And forming a second extending portion, and making the first extending portion narrower than the width of the pad portion so as not to cause interference between adjacent wires, thereby shortening a separation distance between the wires. Accordingly, it is possible to cope with a mounted element having a high density and a high pin count. In addition, since the linear reference side edge continuously extending from the width direction outer peripheral edge of the pad portion is provided in the second extending portion, the width dimension of the second extending portion is the width size of the pad portion. Is the same as Therefore, when performing the flip chip mounting inspection, it is possible to determine the positional relationship of the protruding electrode with respect to the pad portion with reference to the reference side edge, and it is possible to easily determine the quality of the mounting.

That is, based on the position of the reference side edge in the radiographic image as a reference, the overlapping state between the image of the projecting electrode and the image of the wiring is determined.
It is possible to determine the quality of bonding between the protruding electrode and the pad portion, and it is possible to perform highly accurate determination processing.

[0032]

Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a partially enlarged view of a flip-chip mounting substrate 30 according to one embodiment of the present invention.
FIG. 2 shows a semiconductor chip 5 mounted on a flip-chip mounting substrate 30.
FIG. 7 is a side view showing a state in which 0 (device to be mounted) is flip-chip mounted.

The flip-chip mounting board 30 according to the present embodiment has a semiconductor chip with a high density and a high pin count by arranging the bumps 18 in a staggered manner on the board body 4 shown in FIG. 16 is flip-chip mounted. Since the semiconductor chip 16 has been described above, the description of the semiconductor chip 16 is omitted here.

As shown in FIG. 1, wirings 34 are formed on the substrate main body 32 of the flip-chip mounting substrate 30 so as to correspond to the inter-bump pitch P2 of the bumps 18. The wiring 34 is roughly composed of a pad portion 36, a first extension portion 38, a second extension portion 40, and the like. The pad portions 36 are arranged in a staggered manner corresponding to the bumps 18 formed on the semiconductor chip 16 and have a sufficient area and shape to allow the bumps 18 to be flip-chip mounted. Specifically, the width dimension W4 of the pad portion 36 is larger than the diameter dimension of the bump 18 by the semiconductor chip 1.
6 is configured to be wider by an error dimension generated when positioning and mounting the circuit board 6 on the flip-chip mounting board 30, and its shape is substantially semicircular.

As will be described later, the pad portion 36 is
And the second extended portion 40, there is no clear boundary between the pad portion 36 and the second extended portion 40. As described above, by setting the configuration of the pad portion 36 to have a sufficient area and shape for the bump 18 to be flip-chip mounted, a positioning error generated when the semiconductor chip 50 is mounted on the flip-chip mounting substrate 30 can be reduced. It can be absorbed by the pad portion 36. Therefore, the semiconductor chip 50 is mounted on the flip-chip mounting substrate 30.
Can be improved when mounted on a computer.

The first extending portion 38 extends from one of the pad portions 36 and has a width W5 smaller than the width W4 of the pad portion 36 so as not to interfere between adjacent wirings. Further, the second extending portion 40 is provided with the pad portion 3.
6 extend so as to face the first extending portion 38. That is, the second extending portion 40 is formed to extend in the direction opposite to the extending direction of the first extending portion 38 with the pad portion 36 interposed therebetween.

Here, the pad portion 36 and the second extension portion 40
Paying attention to the boundary portion between the two, the second extending portion 40 has a linear reference side edge 42 continuously extending from the widthwise outer peripheral edge of the pad portion 36. That is, the second extending portion 40 has the same size as the width W4 of the pad portion 36. With this configuration, the second extension 4
The width dimension of 0 is wider than the conventional configuration shown in FIG.
However, as shown in FIG. 1, the extending directions of the first extending portion 38 and the second extending portion 40 are alternately different in the adjacent wirings 34, so that the adjacent wirings 34 interfere with each other. There is nothing to do. Further, with this configuration, the distance between the adjacent wirings can be reduced, and thus the semiconductor chip 1 having the bumps 18 with a reduced pitch can be obtained.
Even if it is 6, flip-chip mounting can be ensured.

Further, as described above, in the present embodiment, the linear reference side edge 40 continuously extending from the widthwise outer peripheral edge of the pad portion 36 is formed in the second extending portion 40, Therefore, the width of the second extension 40 is the same as the width W4 of the pad. With this configuration, in the flip chip mounting inspection performed after mounting the semiconductor chip 16 on the flip chip mounting substrate 30, the positional relationship of the bump 52 with respect to the pad portion 36 is determined with reference to the reference side edge 40. It becomes possible.

In FIG. 2, reference numeral 54 denotes a conductive adhesive, and the bump 52 is electrically and mechanically connected to the pad 36 of the wiring 34 by the adhesive 54. . Next, a flip-chip mounting inspection performed after mounting the semiconductor chip 18 on the flip-chip mounting substrate 30 having the above configuration will be described below with reference to FIG.

In the flip-chip mounting inspection according to the present embodiment, a method is adopted in which the bonding position between the wiring 34 and the bump 36 is perspectively imaged using X-rays, and the quality of the mounting is determined from the perspective image. . In addition, the determination of the quality is performed by the inspector observing the fluoroscopic imaging. FIG.
(A) to (D) are perspective images showing various mounting modes of the wiring 34 and the bump 52. FIG. 3A shows the state of the bump 52.
Indicates a state where it is most appropriately mounted (joined) to the wiring 34. In the perspective image in this mounting state, bump 5
2 is located at the center of the perspective image of the wiring 34 (hereinafter referred to as the wiring image 34A), and thus it is determined that the bump 52 is securely joined to the wiring 34. it can.

FIG. 3D shows a state in which the bump 52 is largely displaced in the direction of arrow X in FIG.
2 is completely separated from the wiring 34. Accordingly, the inspector can easily determine from the perspective image that the bonding state between the wiring 34 and the bump 52 is defective. On the other hand, FIG. 3B shows a state in which the bump 52 is displaced in the direction of the arrow X in the figure and is joined to the wiring 34 as compared with the optimum state in FIG. 3) shows a state in which the bumps 52 are slightly displaced in the direction of the arrow X in the figure and are joined to the wiring 34 as compared with the state of FIG.

In each of these states, a part of the bump 52 protrudes from a perspective image of the pad section 36 (hereinafter referred to as a pad section image 36A). Therefore, the inspector observes each of the fluoroscopic images to obtain the bump image 5.
It is determined whether or not the overlapping area of the 2A and the pad image 36A (the wiring image 34A) is at least half the area of the bump image 52A.

In this case, in the present embodiment, since the linear reference side edge 40 continuously extending from the outer peripheral edge in the width direction of the pad portion 36 is formed in the second extension portion 40, the reference side Bump image 52A and pad portion image 36 with reference to edge 40
It is possible to determine the positional relationship with A (overlapping area). Therefore, as compared with the conventional configuration in which the overlapping area of the bump image 18A and the wiring image 22A is determined based on the curved pad outer edge image 25A described with reference to FIG. Since the positional relationship (superimposed area) between the video 52A and the pad portion video 36A can be determined, the quality can be easily determined.

Accordingly, in the case shown in FIG. 3B, the inspector can determine that the bonding state between the pad portion 36 and the bump 52 is proper. Similarly, in the case shown in FIG. 3C, the inspector can easily determine that the bonding state between the pad portion 36 and the bump 52 is defective. As described above, according to the present embodiment, the pad portion 36 and the bump 52
Since it is possible to easily determine the bonding state with the above, it is possible to perform highly accurate determination processing.

[0045]

As described above, according to the present invention, the first and second extending portions are formed so as to face each other with the pad portion interposed therebetween, and interference occurs between the first extending portion and the adjacent wiring. By making the shape narrower than the width of the pad portion so as not to cause the gap, the separation distance between the wirings can be shortened, so that it is possible to cope with a mounted element having a high density and a multi-pin structure.

Further, since the linear reference side edge continuously extending from the outer peripheral edge in the width direction of the pad portion is provided in the second extension portion, this reference side edge is used when performing flip-chip mounting inspection. It is possible to determine the positional relationship of the protruding electrode with respect to the pad portion with reference to. For this reason, it is possible to easily determine the quality of the mounting, and it is possible to perform highly accurate determination processing.

[Brief description of the drawings]

FIG. 1 is a partially enlarged view of a flip-chip mounting substrate according to an embodiment of the present invention.

FIG. 2 is a side view showing a state in which a semiconductor chip is mounted on a flip-chip mounting substrate according to one embodiment of the present invention.

FIG. 3 is a diagram for explaining a flip chip mounting method according to one embodiment of the present invention.

FIG. 4 is a side view showing a state in which a semiconductor chip is mounted on a flip-chip mounting substrate, which is an example of the related art.

FIG. 5 is a diagram for explaining a conventional semiconductor chip.

FIG. 6 is a partially enlarged view of a flip-chip mounting substrate as an example of the related art.

7 is a diagram for explaining a flip chip mounting inspection performed when the semiconductor chip shown in FIG. 5 is mounted on the flip chip mounting substrate shown in FIG. 6;

FIG. 8 is a diagram for explaining a semiconductor chip having a configuration in which bumps are arranged in a staggered manner in order to increase the density and increase the number of pins.

FIG. 9 is a partial enlarged view of a conventional flip-chip mounting substrate on which bumps are arranged in a staggered manner and a semiconductor chip is mounted.

10 is a diagram for explaining a flip chip mounting inspection performed when the semiconductor chip shown in FIG. 8 is mounted on the flip chip mounting substrate shown in FIG. 9;

[Explanation of symbols]

 Reference Signs List 30 Flip chip mounting substrate 32 Substrate body 34 Wiring 34A Wiring image 36 Pad portion 36A Pad portion image 38 First extension portion 38A First extension portion image 40 Second extension portion 40 40A Second extension Part image 42 Reference side edge 42A Reference side edge image 50 Semiconductor chip 52 Bump 52A Bump image 54 Adhesive

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Yoshinobu Maeno 4-1-1, Uedanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Prefecture Inside Fujitsu Limited (72) Inventor Hidehiko Kira 4-1-1, Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa No. 1 Fujitsu Co., Ltd. (72) Inventor Shunji Baba 4-1-1, Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Prefecture No. 1 Fujitsu Co., Ltd. No. 1 Inside Fujitsu Limited

Claims (2)

[Claims] 1. A flip chip in which an element to be mounted having a plurality of projecting electrodes arranged in a staggered manner is flip-chip mounted on a plurality of wirings formed corresponding to the projecting electrodes formed on a substrate body. In the mounting substrate, the wiring is arranged in a staggered manner corresponding to the protruding electrodes, and a pad portion having an area and a shape sufficient to mount the protruding electrodes on a flip chip; A first extension portion extending from one of the first and second portions and having a shape narrower than a width dimension of the pad portion so as not to interfere between adjacent wirings; and a first extension portion from the other of the pad portions. A second extending portion having a linear reference side edge extending so as to be opposed to the pad portion and continuously extending from the outer peripheral edge in the width direction of the pad portion. 2. A flip-chip mounting inspection method for inspecting a mounting state of a bump electrode provided on an element to be mounted on a pad portion formed on a flip-chip mounting substrate according to claim 1 from a radiographic image. By using the position of the reference side edge in the radiographic image as a reference, by judging the state of overlap between the image of the projecting electrode and the image of the wiring, it is possible to determine the quality of bonding between the projecting electrode and the pad portion. A flip-chip mounting inspection method.