JPH11145061A - Vapor growth method for group iii-v compound semiconductor, and light emitting element - Google Patents

Vapor growth method for group iii-v compound semiconductor, and light emitting element

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Publication number
JPH11145061A
JPH11145061A JP30548397A JP30548397A JPH11145061A JP H11145061 A JPH11145061 A JP H11145061A JP 30548397 A JP30548397 A JP 30548397A JP 30548397 A JP30548397 A JP 30548397A JP H11145061 A JPH11145061 A JP H11145061A
Authority
JP
Japan
Prior art keywords
crystal
compound semiconductor
substrate
group
iii
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP30548397A
Other languages
Japanese (ja)
Inventor
Nobuhiro Okubo
伸洋 大久保
Fumihiro Atsunushi
文弘 厚主
Shinya Ishida
真也 石田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
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Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Priority to JP30548397A priority Critical patent/JPH11145061A/en
Publication of JPH11145061A publication Critical patent/JPH11145061A/en
Pending legal-status Critical Current

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  • Crystals, And After-Treatments Of Crystals (AREA)
  • Physical Deposition Of Substances That Are Components Of Semiconductor Devices (AREA)
  • Led Devices (AREA)

Abstract

PROBLEM TO BE SOLVED: To lessen point defects, etc., caused by oxygen atoms, by supplying group V material, Si material, and group Ill material onto a crystal substrate so as to execute the crystal growth of a group III-V compound semiconductor crystal layer, after supplying Si material and group III material onto the crystal substrate. SOLUTION: In the course before start of crystal growth, the first process of supplying material compounds including group V onto a crystal substrate, and the second process of supplying group V material onto the crystal substrate are interrupted. Then, after supply of Si material and group III material onto the crystal substrate, group V material and group III material are supplied onto the crystal substrate, thus the crystal growth of a group III-V compound semiconductor crystal layer is executed. As a result, a Si-doped group III-V compound semiconductor crystal can be grown on the crystal substrate where the group III-V compound semiconductor crystal layer is made on the surface. To be concrete, crystal growth is executed after performing the switching of gas in sequence on the Si-doped GaAs substrate.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、半導体レーザ,L
ED,HEMT等のIII−V族化合物半導体の気相成
長方法及び発光素子に関する。
[0001] The present invention relates to a semiconductor laser, L
The present invention relates to a vapor phase growth method of a III-V compound semiconductor such as ED and HEMT, and a light emitting device.

【0002】[0002]

【従来の技術】III−V族化合物半導体の結晶成長法
としては有機金属気相成長法(MOCVD)や分子線エ
ピタキシャル法(MBE)などが量産性に優れ、しかも
超薄膜結晶の成長が可能であることからもっとも将来期
待されている。それらの典型的なn型III−V族化合
物半導体結晶成長方法は、III−V族化合物半導体結
晶層が表面に形成されている結晶基板の昇降温中に、V
族元素であるヒ素が結晶表面から熱脱離するのを防ぐた
めにV族元素を前記結晶表面上に供給し、その後、II
I族元素とV族元素とSiを同時に結晶表面上に供給し
て、Si添加されたn型III−V族化合物半導体の結
晶成長を行っている。
2. Description of the Related Art Metalorganic vapor phase epitaxy (MOCVD), molecular beam epitaxy (MBE), etc., are excellent in mass productivity and can grow ultra-thin film crystals. It is the most promising in the future. These typical n-type group III-V compound semiconductor crystal growth methods employ a method in which the temperature of a crystal substrate having a group III-V compound semiconductor crystal layer formed thereon is raised and lowered.
A group V element is supplied onto the crystal surface to prevent arsenic, which is a group element, from thermally desorbing from the crystal surface.
A group I element, a group V element, and Si are simultaneously supplied on the crystal surface to perform crystal growth of a Si-added n-type III-V compound semiconductor.

【0003】具体的には、MOCVD法におけるIII
−V族化合物半導体の気相成長方法の例として、以下に
示す。
[0003] Specifically, III in the MOCVD method
An example of a method for vapor-phase growth of a -V compound semiconductor will be described below.

【0004】Si添加GaAs基板上に、Si添加Ga
As結晶層を成長させる場合には、III族原料である
トリエチルガリウム(TEGa)又はトリメチルガリウ
ム(TMGa)とV族原料であるアルシン(AsH3
とSi原料であるシラン(SiH4)又はジシラン(S
26)などを用い、昇降温中はAs抜けを抑制する目
的でアルシンを供給し、その後TEGa又はTMGa、
AsH3、SiH4又はSi26などを供給して、Si添
加GaAs結晶層の結晶成長を行う。
On a Si-doped GaAs substrate, a Si-doped Ga
When growing an As crystal layer, triethyl gallium (TEGa) or trimethyl gallium (TMGa) as a group III material and arsine (AsH 3 ) as a group V material are used.
And silane (SiH 4 ) or disilane (S
i 2 H 6) using a, in heating and cooling supplies arsine purpose of suppressing escape As, then TEGa or TMGa,
By supplying AsH 3 , SiH 4, Si 2 H 6 or the like, the crystal growth of the Si-doped GaAs crystal layer is performed.

【0005】前記III−V族化合物半導体結晶層の表
面には、酸化膜が形成されており、結晶成長前にその酸
化膜を除去しなければ、基板上部に成長した結晶に悪影
響を及ぼすため、様々な方策が取られてきている。特開
平1−301584号公報では、高真空中で活性な水素
を基板表面に照射し、表面酸化膜の除去を行って成長し
ている。特開平3−227531号公報では、反応性ガ
スによる基板表面のエッチングを行い、表面酸化膜の除
去を行って成長している。特開平7−94411号公報
では、表面酸化物をサーマルクリーニングによって除去
し、III族安定化面を出し、結晶成長を行っている。
An oxide film is formed on the surface of the III-V compound semiconductor crystal layer. If the oxide film is not removed before the crystal growth, the crystal grown on the substrate has a bad influence. Various measures have been taken. In JP-A-1-301584, active hydrogen is irradiated on a substrate surface in a high vacuum to remove a surface oxide film and grow the substrate. In JP-A-3-227531, the substrate is grown by etching the substrate surface with a reactive gas to remove the surface oxide film. In JP-A-7-94411, a surface oxide is removed by thermal cleaning to provide a group III stabilized surface, and crystal growth is performed.

【0006】[0006]

【発明が解決しようとする課題】上記の従来方法では、
前記III−V族化合物半導体結晶層が表面に形成され
ている結晶基板の最表面層にSiまたはAlが含まれて
いる場合、特開平7−94411号公報の様にサーマル
クリーニングによって最表面の酸化膜の除去を行うと、
基板表面のダメージは無いが、最表面のSiと酸素の結
合(Si−O)及びAlと酸素の結合(Al−O)が取
れにくいため、基板最表面の酸化膜が完全に除去出来な
い。
In the above conventional method,
In the case where Si or Al is contained in the outermost surface layer of the crystal substrate having the III-V compound semiconductor crystal layer formed on the surface, the outermost surface is oxidized by thermal cleaning as disclosed in JP-A-7-94411. After removing the film,
Although there is no damage on the substrate surface, it is difficult to remove the bond between Si and oxygen (Si-O) and the bond between Al and oxygen (Al-O) on the outermost surface, so that the oxide film on the uppermost surface of the substrate cannot be completely removed.

【0007】そのため、図7(b)のように基板表面に
SiまたはAlと結合した酸素原子が表面に曝されてい
る状態で、V族元素であるAsとSiと前記III族元
素であるGaを同時に結晶基板上に供給して、III−
V族化合物半導体結晶層の結晶成長を行う場合、As及
びGaは酸素と結合しにくく、また、酸素と結合したと
しても結合エネルギーが小さいため、すぐに解離してし
まう。Siは酸素と結合しやすいが、V族元素であるA
sとSiと前記III族元素であるGaを同時に結晶基
板上に供給しているために、Siと酸素が結合する確率
が低くなる。そのため、酸素原子近傍には、Gaの原子
位置にAsが入ったり、Gaの原子位置の原子がない状
態ができ、酸素原子に起因した点欠陥が出来やすい状態
となる。この状態で、結晶成長を行えば、図7(c)の
ように点欠陥を起因とした転位欠陥が自ずと生じる。
Therefore, as shown in FIG. 7 (b), when the substrate surface is exposed to oxygen atoms bonded to Si or Al, the As group Si elements and As group Si elements and the above group III element Ga atoms are exposed. At the same time on a crystal substrate, and III-
When performing crystal growth of the group V compound semiconductor crystal layer, As and Ga are hardly bonded to oxygen, and even if bonded to oxygen, the bonding energy is small, so that they are immediately dissociated. Si is easily bonded to oxygen, but the group V element A
Since s, Si, and Ga, which is the group III element, are simultaneously supplied onto the crystal substrate, the probability of bonding between Si and oxygen is reduced. Therefore, in the vicinity of the oxygen atom, As enters the atomic position of Ga, or there is no atom at the atomic position of Ga, and a point defect due to the oxygen atom easily occurs. If crystal growth is performed in this state, dislocation defects due to point defects naturally occur as shown in FIG.

【0008】また、前記III−V族化合物半導体結晶
層の最表面層にSiまたはAlが含まれている場合にお
いて、特開平1−301584号公報、特開平3−22
7531号公報の様に活性水素や反応性ガスを用いて最
表面の酸化膜の除去を行うと、最表面の酸化膜の除去は
完全に出来ても、基板表面のダメージと基板表面のキャ
リアの欠乏という結果を伴う。
In the case where Si or Al is contained in the outermost layer of the III-V compound semiconductor crystal layer, Japanese Patent Application Laid-Open Nos. 1-301584 and 3-22
When the outermost oxide film is removed using active hydrogen or a reactive gas as disclosed in Japanese Patent No. 7531, even if the oxide film on the outermost surface can be completely removed, damage to the substrate surface and carrier carriers on the substrate surface may occur. With the consequence of deficiency.

【0009】その結果、基板と結晶層の界面での基板表
面のダメージと酸素に起因した転位欠陥が発生する。こ
の転位欠陥があると、前記III−V族化合物半導体結
晶層が表面に形成されている結晶基板上に形成されたI
II−V族化合物半導体結晶層全体に、転位欠陥が発生
する。その結果、亜鉛、ベリリウム、マグネシウム、セ
レン等の拡散係数の大きい不純物が添加されたIII−
V族化合物半導体結晶層内の添加不純物が転位欠陥を起
因として、拡散が起こる。この転位欠陥と添加不純物の
拡散に伴い、III−V族化合物半導体発光素子では、
通電中の素子劣化等の問題を引き起こし、さらには歩留
まりの低下を招く。
As a result, dislocation defects are caused by damage to the substrate surface and oxygen at the interface between the substrate and the crystal layer. When the dislocation defect is present, the I-crystal formed on the crystal substrate on which the III-V compound semiconductor crystal layer is formed is formed.
Dislocation defects occur throughout the II-V compound semiconductor crystal layer. As a result, an impurity having a large diffusion coefficient such as zinc, beryllium, magnesium, and selenium is added.
Diffusion occurs due to dislocation defects in the added impurities in the group V compound semiconductor crystal layer. Along with the dislocation defect and the diffusion of the additional impurity, the III-V compound semiconductor light emitting device
This causes a problem such as element deterioration during energization, and further lowers the yield.

【0010】本発明は、上記の問題について検討した結
果、基板と結晶層の界面での基板表面のダメージと酸素
に起因した転位欠陥を低減した高品質な結晶成長膜を形
成しうるIII−V族化合物半導体の気相成長方法を発
明したものである。
According to the present invention, as a result of studying the above problems, it has been found that a high quality crystal growth film capable of forming a high quality crystal growth film with reduced dislocation defects caused by damage to the substrate surface and oxygen at the interface between the substrate and the crystal layer can be formed. Invented is a method for vapor-phase growth of a group III compound semiconductor.

【0011】[0011]

【課題を解決するための手段】本発明は、III−V族
化合物半導体結晶層が表面に形成されている結晶基板の
上にSiを添加したIII−V族化合物半導体結晶を結
晶成長する気相成長法において、結晶成長開始前の過程
で、第一の工程;V族原料を前記結晶基板上に供給する
第二の工程;V族原料を前記結晶基板上に供給するのを
中断し、Si原料とIII族原料を前記結晶基板上に供
給するを行った後、V族原料とSi原料とIII族原料
を前記結晶基板上に供給し、III−V族化合物半導体
結晶層の結晶成長を行うことを特徴とするIII−V族
化合物半導体の気相成長方法を提供するものである。
According to the present invention, there is provided a vapor phase for growing a group III-V compound semiconductor crystal doped with Si on a crystal substrate having a group III-V compound semiconductor crystal layer formed thereon. In the growth method, before the start of crystal growth, a first step; a second step of supplying a group V source material onto the crystal substrate; interrupting the supply of the group V source material onto the crystal substrate; After the raw material and the group III raw material are supplied on the crystal substrate, the group V raw material, the Si raw material, and the group III raw material are supplied on the crystal substrate, and the crystal growth of the III-V compound semiconductor crystal layer is performed. It is another object of the present invention to provide a method for vapor-phase growing a group III-V compound semiconductor.

【0012】また、本発明は、III−V族化合物半導
体結晶層が表面に形成されている結晶基板の上にSiを
添加したIII−V族化合物半導体結晶を結晶成長する
気相成長法において、結晶成長開始前の過程で、第一の
工程;V族原料を前記結晶基板上に供給する第二の工
程;V族原料を前記結晶基板上に供給するのを中断し、
Si原料とIII族原料を前記結晶基板上に供給する第
三の工程;Si原料とIII族原料を前記結晶基板上に
供給するのを中断し、V族原料を前記結晶基板上に供給
するを行った後、V族原料とSi原料とIII族原料を
前記結晶基板上に供給し、III−V族化合物半導体結
晶層の結晶成長を行うことを特徴とするIII−V族化
合物半導体の気相成長方法を提供するものである。
Further, the present invention provides a vapor phase growth method for growing a group III-V compound semiconductor crystal to which Si is added on a crystal substrate having a group III-V compound semiconductor crystal layer formed thereon. In the process before the start of crystal growth, a first step; a second step of supplying a group V source onto the crystal substrate; interrupting the supply of a group V source onto the crystal substrate;
A third step of supplying a Si raw material and a Group III raw material onto the crystal substrate; stopping supplying the Si raw material and the Group III raw material onto the crystal substrate, and supplying a Group V raw material onto the crystal substrate. After that, a group V material, a Si material and a group III material are supplied onto the crystal substrate, and a crystal growth of a group III-V compound semiconductor crystal layer is performed. It provides a growth method.

【0013】具体的には、Si添加GaAs基板上に図
1、図2の様なシーケンスでガスの切り替えを行った
後、結晶成長を行う。
More specifically, after gas is switched on a Si-doped GaAs substrate in the sequence shown in FIGS. 1 and 2, crystal growth is performed.

【0014】さらに、本発明は、n型添加不純物にSi
を用いるIII−V族化合物半導体発光素子において、
前記III−V族化合物半導体の気相成長方法を用いて
作製されたことを特徴とするIII−V族化合物半導体
発光素子を提供するものである。
Further, according to the present invention, the n-type impurity
In a III-V compound semiconductor light emitting device using
An object of the present invention is to provide a III-V compound semiconductor light emitting device manufactured using the method of vapor-phase growing a III-V compound semiconductor.

【0015】[0015]

【発明の実施の形態】本発明では、Si添加III−V
族化合物半導体結晶の結晶成長に先立ち、まず第一の工
程において、基板昇温中に砒素等のV族元素を供給しな
がら、Asと結合した酸素、Gaと結合した酸素を分解
及び乖離し、図6(b)のように基板表面をほぼAs原
子で被覆した形となるが、Siと酸素の結合またはAl
と酸素の結合はこの時点ではほとんど分解しないため、
基板表面にSiまたはAlと結合した酸素原子が表面に
曝されている。
DETAILED DESCRIPTION OF THE INVENTION In the present invention, a Si-added III-V
Prior to the crystal growth of the group III compound semiconductor crystal, in the first step, oxygen combined with As and oxygen combined with Ga are decomposed and separated while supplying a group V element such as arsenic during the temperature rise of the substrate, As shown in FIG. 6B, the surface of the substrate is almost covered with As atoms.
Since the bond between oxygen and oxygen hardly breaks down at this point,
Oxygen atoms bonded to Si or Al are exposed to the surface of the substrate.

【0016】次の第二の工程において、V族原料を前記
結晶基板上に供給するのを中断し、Si原料とIII族
原料を前記結晶基板上に供給することにより、図6
(c)のようにGaはAsと結合する。Siは酸素と結
合し、Gaの原子位置に入る。この結果、基板表面には
GaとSiだけになる。
In the next second step, the supply of the group V raw material onto the crystal substrate is interrupted, and the Si raw material and the group III raw material are supplied onto the crystal substrate.
Ga couples with As as shown in FIG. Si combines with oxygen and enters the atomic position of Ga. As a result, only Ga and Si remain on the substrate surface.

【0017】基板表面にGaとSiだけ曝されている状
態では、基板界面の点欠陥を低減しているため、V族原
料とSi原料とIII族原料を同時に前記結晶基板上に
供給しても、図6(d)のように転位欠陥を低減した高
品質なIII−V族化合物半導体結晶の成長が可能とな
る。また、エッチング等の基板表面処理を行っていない
ため、基板表面にダメージを与えないので、基板表面の
ダメージに起因した転位欠陥をなくした高品質なIII
−V族化合物半導体結晶の成長が可能となる。
In the state where only Ga and Si are exposed to the substrate surface, the point defects at the substrate interface are reduced, so that the group V raw material, the Si raw material and the group III raw material are simultaneously supplied onto the crystal substrate. As shown in FIG. 6D, a high-quality group III-V compound semiconductor crystal with reduced dislocation defects can be grown. Further, since the substrate surface treatment such as etching is not performed, no damage is given to the substrate surface, so that a high-quality III that eliminates dislocation defects caused by damage to the substrate surface is obtained.
-Group V compound semiconductor crystal can be grown.

【0018】以下に本発明の実施例を詳細に説明する。 (実施例1)本実施例では、Si添加GaAs基板上へ
のSi添加GaAs結晶膜成長方法について説明する。
Hereinafter, embodiments of the present invention will be described in detail. (Embodiment 1) In this embodiment, a method of growing a Si-doped GaAs crystal film on a Si-doped GaAs substrate will be described.

【0019】Si添加GaAs基板上にSi添加GaA
s薄膜を成長するのにトリメチルガリウム(TMGa)
と水素(H2)で10%に希釈したアルシン(AsH3
とH2で100ppmに希釈したジシラン(Si26
を原料として使用した。使用した装置は、減圧横型高周
波加熱炉の気相成長装置で、炉内圧力は76Torrで
行った。結晶成長は、図1のシーケンスの様に行った。
Si-doped GaAs on a Si-doped GaAs substrate
Trimethyl gallium (TMGa) for growing thin film
And arsine (AsH 3 ) diluted to 10% with hydrogen (H 2 )
And disilane (Si 2 H 6 ) diluted to 100 ppm with H 2
Was used as a raw material. The apparatus used was a vapor phase growth apparatus of a reduced-pressure horizontal high-frequency heating furnace, and the furnace pressure was set to 76 Torr. The crystal growth was performed according to the sequence shown in FIG.

【0020】Si添加n型GaAs基板の昇温開始後、
AsH3をSi添加n型GaAs基板上に供給開始し、
基板温度が750℃まで上昇した後、前記基板温度を5
70℃まで降温する。その後、AsH3の基板への供給
を一時停止し、TMGa、Si26をSi添加n型Ga
As基板上に供給する。その後、III族元素を含む原
料化合物の供給量(TMGa)とV族元素を含む原料化
合物の供給量(AsH3)の比を120とし、AsH3
TMGa、Si26をSi添加n型GaAs基板上に供
給すると同時に前記基板温度を750℃まで昇温して、
Si添加GaAs薄膜の結晶成長を行った。成長時間は
90minで2μmの厚さを有するSi添加n型GaA
s薄膜が得られた。
After starting the temperature increase of the Si-doped n-type GaAs substrate,
Start supplying AsH 3 onto the Si-doped n-type GaAs substrate,
After the substrate temperature rises to 750 ° C.,
Cool down to 70 ° C. Thereafter, the supply of AsH 3 to the substrate is temporarily stopped, and TMGa and Si 2 H 6 are added to the Si-added n-type Ga.
It is supplied on an As substrate. Thereafter, the ratio of the supply amount of the raw material compound containing the group III element (TMGa) to the supply amount of the raw material compound containing the group V element (AsH 3 ) is set to 120, and AsH 3 ,
At the same time, TMGa and Si 2 H 6 are supplied onto the Si-doped n-type GaAs substrate, and the substrate temperature is raised to 750 ° C.
Crystal growth of a Si-doped GaAs thin film was performed. The growth time is 90 min and the Si-added n-type GaAs having a thickness of 2 μm
An s thin film was obtained.

【0021】又、比較のため、図3のシーケンスのよう
に、AsH3をSi添加n型GaAs基板上に供給開始
し、基板温度が750℃に安定後、AsH3、TMG
a、Si26をSi添加n型GaAs基板上に供給し、
Si添加GaAs薄膜の結晶成長を行う従来方法で、2
μmの厚さを有するSi添加GaAs薄膜も作製した。
For comparison, as shown in the sequence of FIG. 3, supply of AsH 3 onto a Si-added n-type GaAs substrate is started, and after the substrate temperature is stabilized at 750 ° C., AsH 3 and TMG
a, supplying Si 2 H 6 onto a Si-doped n-type GaAs substrate;
A conventional method for crystal growth of a Si-doped GaAs thin film is used.
A Si-doped GaAs thin film having a thickness of μm was also prepared.

【0022】得られた2つの成長層の結晶成長後の転位
欠陥密度を測定したが、従来方法では1000/cm2
であるが、本発明の結晶成長方法を用いることにより、
300/cm2と飛躍的に低減可能となっている。
[0022] Although the dislocation defect density after the crystal growth of the resulting two growth layers were measured, in the conventional method 1000 / cm 2
However, by using the crystal growth method of the present invention,
It can be dramatically reduced to 300 / cm 2 .

【0023】また、得られた2つの成長層の不純物分析
を2次イオン質量分析(SIMS)装置で測定した結
果、Si添加n型GaAs基板とSi添加GaAs薄膜
の界面での酸素濃度が、従来方法に比べて、本発明の結
晶成長方法を用いることにより、低減されていた。以上
より、本発明の結晶成長方法を用いることにより、高品
質なSi添加GaAs薄膜を作製することが可能である
ことがわかる。
Further, as a result of impurity analysis of the two grown layers obtained by using a secondary ion mass spectrometer (SIMS), the oxygen concentration at the interface between the Si-doped n-type GaAs substrate and the Si-doped GaAs thin film was reduced. Compared with the method, the reduction was achieved by using the crystal growth method of the present invention. From the above, it is understood that a high-quality Si-doped GaAs thin film can be manufactured by using the crystal growth method of the present invention.

【0024】本実施例では、Si添加GaAs基板上へ
のSi添加GaAs結晶膜成長方法を示しているが、他
のSi添加III−V族化合物半導体基板、例えば、I
nP等でも同様の結果が得られるし、あるいは、他のS
i添加III−V族化合物半導体結晶膜、例えば、Al
GaAs、InGaAs、AlGaInP、InGa
P、InGaAsP等においても、同様の結果が得られ
る。
In this embodiment, a method of growing a Si-doped GaAs crystal film on a Si-doped GaAs substrate is described.
Similar results can be obtained with nP or the like, or other S
i-added III-V compound semiconductor crystal film, for example, Al
GaAs, InGaAs, AlGaInP, InGa
Similar results are obtained with P, InGaAsP, and the like.

【0025】(実施例2)本実施例では、Si添加Al
GaAs結晶層上へのSi添加AlGaAs結晶膜成長
方法について説明する。
(Embodiment 2) In this embodiment, Si-added Al
A method for growing a Si-added AlGaAs crystal film on a GaAs crystal layer will be described.

【0026】Si添加GaAs基板上に1μmの厚さを
有するSi添加AlGaAs薄膜を長し、それをいった
ん大気に曝した後、ウェットエッチングで表面酸化膜を
除去後、その上に1μmの厚さを有するSi添加AlG
aAs薄膜を成長した。用いた原料は、トリメチルガリ
ウム(TMGa)とトリメチルアルミニウム(TMA
l)と水素(H2)で10%に希釈したアルシン(As
3)とH2で100ppmに希釈したシラン(Si
4)で、使用した装置は、減圧横型高周波加熱炉の気
相成長装置で、炉内圧力は76Torrで行った。
On a Si-doped GaAs substrate, a Si-doped AlGaAs thin film having a thickness of 1 μm is lengthened, and once exposed to the atmosphere, a surface oxide film is removed by wet etching, and a 1 μm thick film is formed thereon. AlG with Si
An aAs thin film was grown. The raw materials used were trimethylgallium (TMGa) and trimethylaluminum (TMA).
l) and arsine (As) diluted to 10% with hydrogen (H 2 )
Silane (Si) diluted to 100 ppm with H 3 ) and H 2
H 4 ), the apparatus used was a vapor phase growth apparatus for a reduced-pressure horizontal high-frequency heating furnace, and the furnace pressure was set to 76 Torr.

【0027】上記Si添加AlGaAs結晶薄膜層上へ
のSi添加AlGaAs結晶薄膜成長は、図2のシーケ
ンスの様に行った。図2のシーケンスでは、工程3に示
すように、Si原料とIII族原料を結晶基板上に供給
するのを中断し、V族原料を前記結晶基板上に供給する
工程を行った後、V族原料とSi原料とIII族原料を
前記結晶基板上に供給し、III−V族化合物半導体結
晶層の結晶成長を行うため、Si添加AlGaAs結晶
薄膜層の再成長界面の酸素濃度をより低減することが可
能となる。具体的には以下のように行った。
The growth of the Si-doped AlGaAs crystal thin film on the Si-doped AlGaAs crystal thin film layer was performed according to the sequence shown in FIG. In the sequence of FIG. 2, as shown in Step 3, the supply of the Si source and the Group III source onto the crystal substrate is interrupted, and the step of supplying the Group V source onto the crystal substrate is performed. Supplying a raw material, a Si raw material, and a group III raw material onto the crystal substrate, and performing crystal growth of the III-V compound semiconductor crystal layer, thereby further reducing the oxygen concentration at the regrowth interface of the Si-added AlGaAs crystal thin film layer. Becomes possible. Specifically, the procedure was performed as follows.

【0028】Si添加AlGaAs薄膜が表面に形成さ
れたSi添加GaAs基板の昇温開始後、AsH3をS
i添加AlGaAs薄膜上に供給開始し、前記基板温度
が750℃まで上昇した後、前記基板温度を620℃ま
で降温する。その後、AsH3のSi添加AlGaAs
薄膜上への供給を一時停止し、TMGa、TMAl、S
iH4をSi添加AlGaAs薄膜上に供給する。その
後、TMGa、TMAl、SiH4のSi添加AlGa
As薄膜上への供給を一時停止し、再びAsH3をSi
添加AlGaAs薄膜上に供給すると同時に前記基板温
度を750℃まで昇温する。その後、III族元素を含む
原料化合物の供給量(TMGa)とV族元素を含む原料
化合物の供給量(AsH3)の比を120とし、As
3、TMGa、TMAl、SiH4をSi添加n型Al
GaAs薄膜上に供給し、Si添加AlGaAs薄膜上
に1μmの厚さを有するSi添加AlGaAs薄膜の結
晶成長を行った。
After starting the temperature rise of the Si-doped GaAs substrate having the Si-doped AlGaAs thin film formed on the surface, AsH 3 is added to S
The supply is started on the i-doped AlGaAs thin film, and after the substrate temperature rises to 750 ° C., the substrate temperature is lowered to 620 ° C. Then, AsH 3 Si-added AlGaAs
Suspending the supply on the thin film, TMGa, TMAl, S
iH 4 is supplied on the Si-doped AlGaAs thin film. Thereafter, Si-added AlGa of TMGa, TMAl, SiH 4
The supply on the As thin film is temporarily stopped, and AsH 3 is again
The temperature of the substrate is raised to 750 ° C. at the same time when the substrate is supplied onto the added AlGaAs thin film. Then, the ratio between the supply amount of the raw material compound containing the group III element (TMGa) and the supply amount of the raw material compound containing the group V element (AsH 3 ) is set to 120, and As is obtained.
N-type Al doped with H 3 , TMGa, TMAl and SiH 4
The Si-added AlGaAs thin film having a thickness of 1 μm was supplied on the GaAs thin film and grown on the Si-added AlGaAs thin film.

【0029】以上の本発明方法によって得られたSi添
加AlGaAs薄膜の不純物分析を2次イオン質量分析
(SIMS)装置で測定し、得られた結果を図8に示
す。
Impurity analysis of the Si-doped AlGaAs thin film obtained by the above method of the present invention was measured by a secondary ion mass spectrometer (SIMS), and the obtained result is shown in FIG.

【0030】又、比較のため、2種類の従来方法を用い
て、Si添加AlGaAs薄膜上に1μmの厚さを有す
るSi添加AlGaAs薄膜も作製した。
For comparison, a Si-added AlGaAs thin film having a thickness of 1 μm was formed on the Si-added AlGaAs thin film by using two kinds of conventional methods.

【0031】第一の方法は、Si添加AlGaAs薄膜
表面の酸化膜を高真空中で活性な水素を基板表面に照射
し、表面酸化膜の除去を行ってから、図3のシーケンス
のように、AsH3をSi添加AlGaAs薄膜上に供
給開始し、基板温度が750℃に安定後、AsH3、T
MGa、TMAl、SiH4をSi添加AlGaAs薄
膜上に供給し、Si添加AlGaAs薄膜の結晶成長を
行う従来方法で、第二の方法は、Si添加AlGaAs
薄膜表面の酸化膜をウェットエッチングで表面酸化膜の
除去を行ってから、図3のシーケンスのように、AsH
3をSi添加AlGaAs薄膜上に供給開始し、基板温
度が750℃に安定後、AsH3、TMGa、TMA
l、SiH4をSi添加AlGaAs薄膜上に供給し、
Si添加AlGaAs薄膜の結晶成長を行う従来方法で
ある。
A first method is to irradiate an active hydrogen in a high vacuum on the oxide film on the surface of the Si-doped AlGaAs thin film to remove the surface oxide film and then remove the surface oxide film as shown in the sequence of FIG. AsH 3 is started to be supplied onto the Si-doped AlGaAs thin film, and after the substrate temperature is stabilized at 750 ° C., AsH 3 and T
A conventional method of supplying Mga, TMAl, and SiH 4 onto a Si-doped AlGaAs thin film to grow a crystal of the Si-doped AlGaAs thin film. The second method is a Si-doped AlGaAs thin film.
After removing the surface oxide film by wet etching of the oxide film on the thin film surface, as shown in the sequence of FIG.
3 is started to be supplied on the Si-doped AlGaAs thin film, and after the substrate temperature is stabilized at 750 ° C., AsH 3 , TMGa, TMA
1, SiH 4 is supplied on the Si-doped AlGaAs thin film,
This is a conventional method for performing crystal growth of a Si-doped AlGaAs thin film.

【0032】上記従来方法によって得られたSi添加A
lGaAs薄膜の不純物分析を2次イオン質量分析(S
IMS)装置で測定し、得られた結果を図9、図10に
示す。図8、図9、図10において横軸は成長膜深さを
表し、縦軸は酸素(O)及びシリコン(Si)の不純物
濃度を表す。
The Si-added A obtained by the above conventional method
Impurity analysis of the lGaAs thin film was performed by secondary ion mass spectrometry (S
(IMS) apparatus, and the obtained results are shown in FIGS. 8, 9, and 10, the horizontal axis represents the depth of the grown film, and the vertical axis represents the impurity concentrations of oxygen (O) and silicon (Si).

【0033】図8、図9、図10のSi添加AlGaA
s再成長界面において、酸素濃度は、図9<図8<図1
0の順で多くなっており、表面酸化膜の除去と言う観点
では、高真空中で活性な水素を基板表面に照射し、表面
酸化膜の除去する方法が1番良い。しかし、再成長界面
のシリコン濃度は、図8、図10では変化はないのに対
して、図9では、減少しており、キャリアの欠乏が生じ
ている。
FIGS. 8, 9 and 10 show Si-doped AlGaAs.
At the s-regrowth interface, the oxygen concentration is as shown in FIG. 9 <FIG. 8 <FIG.
From the viewpoint of removing the surface oxide film, the best method is to irradiate the substrate surface with active hydrogen in a high vacuum to remove the surface oxide film. However, while the silicon concentration at the regrowth interface does not change in FIGS. 8 and 10, it decreases in FIG. 9 and carrier deficiency occurs.

【0034】また、得られた3つの成長層の結晶成長後
の転位欠陥密度を測定したが、第一の従来方法では5×
104/cm2、第二の従来方法では1×104/cm2
あるが、本発明の結晶成長方法を用いることにより、2
×103/cm2と低減されている。
Further, the dislocation defect density after crystal growth of the obtained three grown layers was measured.
Although it is 10 4 / cm 2 and 1 × 10 4 / cm 2 in the second conventional method, by using the crystal growth method of the present invention, it is 2 × 10 4 / cm 2.
× 10 3 / cm 2 .

【0035】以上より、本発明の結晶成長方法を用いる
ことにより、結晶界面でのキャリアの欠乏が無く、表面
酸化膜を除去し、転位欠陥を低減した高品質なSi添加
AlGaAs薄膜を作製することが可能であることがわ
かる。
As described above, by using the crystal growth method of the present invention, there is no lack of carriers at the crystal interface, the surface oxide film is removed, and a high-quality Si-doped AlGaAs thin film with reduced dislocation defects is produced. It can be seen that is possible.

【0036】本実施例では、Si添加AlGaAs結晶
層上へのSi添加AlGaAs結晶膜成長方法を示して
いるが、他のSi添加III−V族化合物半導体結晶
層、例えばGaAs、AlGaAs、InGaAs、I
nP、AlGaInP、InGaP、InGaAsP等
の結晶層上でも同様の結果が得られるし、あるいは、他
のSi添加III−V族化合物半導体結晶膜成長の場
合、例えばGaAs、AlGaAs、InGaAs、I
nP、AlGaInP、InGaP、InGaAsP等
においても、同様の結果が得られる。
In this embodiment, a method of growing a Si-doped AlGaAs crystal film on a Si-doped AlGaAs crystal layer is shown. However, other Si-doped III-V compound semiconductor crystal layers, such as GaAs, AlGaAs, InGaAs, and IGaAs
Similar results can be obtained on a crystal layer of nP, AlGaInP, InGaP, InGaAsP, or the like. Alternatively, in the case of growing another Si-added III-V compound semiconductor crystal film, for example, GaAs, AlGaAs, InGaAs, IGaAs
Similar results are obtained for nP, AlGaInP, InGaP, InGaAsP, and the like.

【0037】(実施例3)本実施例では、本発明のSi
添加AlGaAs結晶膜の成長温度の最適化について説
明する。
(Embodiment 3) In this embodiment, the Si
The optimization of the growth temperature of the added AlGaAs crystal film will be described.

【0038】Si添加GaAs基板上に1μmの厚さを
有するSi添加AlGaAs薄膜を成長し、それをいっ
たん大気に曝した後、ウェットエッチングで表面酸化膜
を除去後、その上に1μmの厚さを有するSi添加Al
GaAs薄膜を成長した。用いた原料は、トリメチルガ
リウム(TMGa)とトリメチルアルミニウム(TMA
l)と水素(H2)で10%に希釈したアルシン(As
3)とH2で100ppmに希釈したシラン(Si
4)で、使用した装置は、減圧横型高周波加熱炉の気
相成長装置で、炉内圧力は76Torrで行った。
After growing a Si-added AlGaAs thin film having a thickness of 1 μm on a Si-doped GaAs substrate, once exposing it to the atmosphere, removing the surface oxide film by wet etching, and then forming a 1 μm-thick film thereon. Si-added Al having
A GaAs thin film was grown. The raw materials used were trimethylgallium (TMGa) and trimethylaluminum (TMA).
l) and arsine (As) diluted to 10% with hydrogen (H 2 )
Silane (Si) diluted to 100 ppm with H 3 ) and H 2
H 4 ), the apparatus used was a vapor phase growth apparatus for a reduced-pressure horizontal high-frequency heating furnace, and the furnace pressure was set to 76 Torr.

【0039】結晶成長は、図2のシーケンスの第一の工
程の基板温度T1(℃)及び第二の工程の基板温度T2
(℃)温度を変化させて行った。
In the crystal growth, the substrate temperature T1 (° C.) in the first step and the substrate temperature T2 in the second step in the sequence of FIG.
(° C.) at different temperatures.

【0040】Si添加AlGaAs薄膜が表面に形成さ
れたSi添加GaAs基板の昇温開始後、AsH3をS
i添加AlGaAs薄膜上に供給開始し、基板温度をT
1までまで上昇させ、しばらくした後、前記基板温度を
T2まで変化させる。その後、AsH3のSi添加Al
GaAs薄膜への供給を一時停止しTMGa、TMA
l、SiH4をSi添加AlGaAs薄膜上に供給す
る。その後、TMGa、TMAl、SiH4のSi添加
AlGaAs薄膜への供給を一時停止し、再びAsH3
をSi添加AlGaAs薄膜上に供給すると同時に前記
基板温度を750℃まで変化させる。その後、III族
元素を含む原料化合物の供給量(TMGa)とV族元素
を含む原料化合物の供給量(AsH3)の比を120と
し、AsH3、TMGa、TMAl、SiH4をSi添加
n型AlGaAs薄膜上に供給し、Si添加AlGaA
s薄膜上に1μmの厚さを有するSi添加AlGaAs
薄膜の結晶成長を行った。
After starting the temperature rise of the Si-doped GaAs substrate having the Si-doped AlGaAs thin film formed on the surface, AsH 3 was changed to S
The supply is started on the i-doped AlGaAs thin film, and the substrate temperature is set to T
Then, after a while, the substrate temperature is changed to T2. After that, Si-added Al of AsH 3
The supply to the GaAs thin film is temporarily stopped, and TMGa and TMA are stopped.
1, SiH 4 is supplied on the Si-doped AlGaAs thin film. Thereafter, the supply of TMGa, TMAl, and SiH 4 to the Si-added AlGaAs thin film is temporarily stopped, and the supply of AsH 3 is stopped again.
Is supplied onto the Si-doped AlGaAs thin film, and at the same time, the substrate temperature is changed to 750 ° C. Then, the ratio of the supply amount of the raw material compound containing the group III element (TMGa) to the supply amount of the raw material compound containing the group V element (AsH 3 ) was set to 120, and AsH 3 , TMGa, TMAl, and SiH 4 were added to the Si-added n-type. Si-doped AlGaAs supplied on AlGaAs thin film
Si-doped AlGaAs having a thickness of 1 μm on an s thin film
Crystal growth of the thin film was performed.

【0041】第一の工程の基板温度T1及び第二の工程
の基板温度T2は、一般的な減圧横形高周波加熱炉の通
常の温度範囲である550℃から850℃の間で行っ
た。
The substrate temperature T1 in the first step and the substrate temperature T2 in the second step were within a normal temperature range of a general reduced-pressure horizontal high-frequency heating furnace between 550 ° C. and 850 ° C.

【0042】以上の本発明方法によって得られたSi添
加AlGaAs薄膜の不純物分析を2次イオン質量分析
(SIMS)装置で測定を行った。その結果は、Si添
加AlGaAs再成長薄膜中の酸素濃度は、第二工程の
温度には無関係で、第一工程の温度に依存することが分
かった。第一工程の成長温度が600℃以下である場合
において、酸素濃度が急激に増加している。
The impurity analysis of the Si-doped AlGaAs thin film obtained by the above method of the present invention was measured by a secondary ion mass spectrometer (SIMS). As a result, it was found that the oxygen concentration in the Si-doped AlGaAs regrown thin film was independent of the temperature of the second step, but was dependent on the temperature of the first step. When the growth temperature in the first step is equal to or lower than 600 ° C., the oxygen concentration sharply increases.

【0043】また、得られた成長層の結晶成長後の転位
欠陥密度を測定した結果、第二工程の成長温度が650
℃以上であると、転位欠陥密度は、低減される効果は見
られない。
Further, as a result of measuring the dislocation defect density after crystal growth of the obtained growth layer, the growth temperature in the second step was 650.
When the temperature is higher than or equal to ° C., the effect of reducing the dislocation defect density is not seen.

【0044】また、第二・第三工程の原料ガスの切り替
えは、成長温度が一定にならない間に切り替えても、第
二工程の成長温度が650℃以下であれば、Si添加A
lGaAs薄膜の酸素濃度及び結晶成長後の転位欠陥密
度には関係ない。
Further, even if the source gas is switched in the second and third steps while the growth temperature is not constant, if the growth temperature in the second step is 650.degree.
It has nothing to do with the oxygen concentration of the lGaAs thin film or the dislocation defect density after crystal growth.

【0045】以上より、本発明の結晶成長方法におい
て、図5に示したように、第一工程の成長温度が600
℃以上で、第二工程の成長温度が650℃以下であれ
ば、さらに表面酸化膜を除去し、転位欠陥を低減した高
品質なSi添加AlGaAs薄膜を作製することが可能
であることがわかる。
As described above, in the crystal growth method of the present invention, as shown in FIG.
It can be seen that if the growth temperature in the second step is not less than 650C and the growth temperature in the second step is not more than 650C, it is possible to further remove the surface oxide film and produce a high-quality Si-doped AlGaAs thin film with reduced dislocation defects.

【0046】また、図5に示したように、第一工程の成
長温度が600℃以上650℃以下であれば、第二工程
の成長温度を第一工程の成長温度以下にしなくても、表
面酸化膜を除去し、転移欠陥を低減した高品質なSi添
加AlGaAs薄膜を作成することが可能であることが
わかる。
As shown in FIG. 5, if the growth temperature in the first step is not less than 600 ° C. and not more than 650 ° C., the growth temperature in the second step does not have to be lower than the growth temperature in the first step. It is understood that it is possible to remove the oxide film and produce a high-quality Si-doped AlGaAs thin film with reduced dislocation defects.

【0047】本実施例では、Si添加AlGaAs結晶
層上へのSi添加AlGaAs結晶膜成長方法を示して
いるが、他のSi添加III−V族化合物半導体結晶
層、例えばGaAs、AlGaAs、InGaAs、I
nP、AlGaInP、InGaP、InGaAsP等
の結晶層上でも同様の結果が得られるし、あるいは、他
のSi添加III−V族化合物半導体結晶膜成長の場
合、例えばGaAs、AlGaAs、InGaAs、I
nP、AlGaInP、InGaP、InGaAsP等
においても、同様の結果が得られる。
In this embodiment, a method of growing a Si-doped AlGaAs crystal film on a Si-doped AlGaAs crystal layer is described. However, other Si-doped III-V compound semiconductor crystal layers, such as GaAs, AlGaAs, InGaAs, and IGaAs
Similar results can be obtained on a crystal layer of nP, AlGaInP, InGaP, InGaAsP, or the like. Alternatively, in the case of growing another Si-added III-V compound semiconductor crystal film, for example, GaAs, AlGaAs, InGaAs, IGaAs
Similar results are obtained for nP, AlGaInP, InGaP, InGaAsP, and the like.

【0048】また、本実施例では、図2のシーケンスの
場合を説明したが、図1のシーケンスの第一工程及び第
二工程の最適温度範囲についても同様の結果が得られ
る。
In this embodiment, the case of the sequence shown in FIG. 2 has been described. However, similar results can be obtained for the optimum temperature ranges of the first step and the second step of the sequence shown in FIG.

【0049】(実施例4)本実施例では、本発明の結晶
成長方法を用いた半導体レーザについて説明する。図1
1は本実施例の半導体レーザ素子の断面図である。第一
の結晶成長で、Si添加n型GaAs基板1上にSi添
加n型GaAsバッファ層2、n型AlGaAsクラッ
ド層3、AlGaAs活性層4、p型AlGaAs第一
クラッド層5、p型GaAsエッチングストップ層6、
p型AlGaAs第二クラッド層7、p型GaAs保護
層8が順次積層される。p型GaAsエッチングストッ
プ層6の上部よりストライプ状のメサ構造をなす。メサ
ストライプの両側は、第二の結晶成長で、Si添加n型
AlGaAs電流ブロック層9、n型GaAs電流ブロ
ック層10、p型GaAs平坦化層11で埋め込まれ
る。p型GaAs保護層8とp型GaAs平坦化層11
の上には、p型GaAsコンタクト層12が形成されて
いる。p型GaAsコンタクト層12の上にはp側金属
電極13、Si添加n型GaAs基板1上にはn側金属
電極14が蒸着されている。
(Embodiment 4) In this embodiment, a semiconductor laser using the crystal growth method of the present invention will be described. FIG.
FIG. 1 is a sectional view of the semiconductor laser device of the present embodiment. In the first crystal growth, a Si-added n-type GaAs buffer layer 2, an n-type AlGaAs cladding layer 3, an AlGaAs active layer 4, a p-type AlGaAs first cladding layer 5, and a p-type GaAs etching are formed on a Si-added n-type GaAs substrate 1. Stop layer 6,
A p-type AlGaAs second cladding layer 7 and a p-type GaAs protection layer 8 are sequentially laminated. A stripe-shaped mesa structure is formed from above the p-type GaAs etching stop layer 6. Both sides of the mesa stripe are filled with a Si-doped n-type AlGaAs current block layer 9, an n-type GaAs current block layer 10, and a p-type GaAs planarization layer 11 in the second crystal growth. p-type GaAs protective layer 8 and p-type GaAs planarization layer 11
A p-type GaAs contact layer 12 is formed thereon. A p-side metal electrode 13 is deposited on the p-type GaAs contact layer 12, and an n-side metal electrode 14 is deposited on the Si-added n-type GaAs substrate 1.

【0050】上記半導体レーザ素子のSi添加n型Ga
Asバッファ層2〜p型GaAsコンタクト層12の各
層は、Ga原料としてトリメチルガリウム(TMG
a)、Al原料としてトリメチルアルミニウム(TMA
l)、As原料としてアルシン(AsH3)、n型不純
物であるSi原料としてシラン(SiH4)、p型不純
物あるZn原料としてジエチルジンク(DEZn)を用
い、使用した装置は、減圧横型高周波加熱炉の気相成長
装置で、炉内圧力は76Torrで行った。
In the above-mentioned semiconductor laser device, Si-doped n-type Ga
Each layer of the As buffer layer 2 to the p-type GaAs contact layer 12 is made of trimethylgallium (TMG) as a Ga material.
a), trimethyl aluminum (TMA)
1) Arsine (AsH 3 ) as an As material, silane (SiH 4 ) as a Si material as an n-type impurity, and diethyl zinc (DEZn) as a Zn material as a p-type impurity. The furnace pressure was set at 76 Torr in a furnace vapor phase growth apparatus.

【0051】まず、第一の結晶成長は、以下の方法で行
った。Si添加n型GaAs基板の昇温開始後、AsH
3をSi添加n型GaAs基板1上に供給開始し、基板
温度が750℃まで上昇した後、前記基板温度を620
℃まで降温する。その後、AsH3の基板への供給を一
時停止しTMGa、SiH4をSi添加n型GaAs基
板1上に供給する。その後、III族元素を含む原料化
合物の供給量(TMGa供給量または、TMGa供給量
とTMAl供給量の和)とV族元素を含む原料化合物の
供給量(AsH3)の比を120とし、AsH3、TMG
a、SiH4をSi添加n型GaAs基板1上に供給す
ると同時に前記基板温度を750℃まで昇温して、Si
添加n型GaAsバッファ層2の結晶成長を開始する。
First, the first crystal growth was performed by the following method. After starting the temperature increase of the Si-doped n-type GaAs substrate, AsH
3 is started to be supplied on the Si-doped n-type GaAs substrate 1 and the substrate temperature is raised to 750 ° C.
Cool down to ° C. Thereafter, the supply of AsH 3 to the substrate is temporarily stopped, and TMGa and SiH 4 are supplied onto the Si-doped n-type GaAs substrate 1. Thereafter, the ratio between the supply amount of the raw material compound containing the group III element (TMGa supply amount or the sum of the TMGa supply amount and the TMAl supply amount) and the supply amount of the raw material compound containing the group V element (AsH 3 ) is set to 120, and AsH 3 , TMG
a, SiH 4 is supplied onto the Si-doped n-type GaAs substrate 1 and at the same time the substrate temperature is raised to 750 ° C.
The crystal growth of the added n-type GaAs buffer layer 2 is started.

【0052】Si添加n型GaAsバッファ層2からp
型GaAs保護層8まで順次積層された後に、いったん
気相成長装置外に出して、p型GaAsエッチングスト
ップ層6の上部よりストライプ状のメサ構造をなすよう
にエッチングを行う。エッチング後、再び気相成長装置
内に基板を持ち込み、第二の結晶成長を行った。
From the Si-doped n-type GaAs buffer layer 2 to p
After the layers are sequentially stacked up to the p-type GaAs protective layer 8, the p-type GaAs etching stop layer 6 is once etched out of the vapor phase growth apparatus and etched to form a stripe-shaped mesa structure. After the etching, the substrate was again brought into the vapor phase growth apparatus, and second crystal growth was performed.

【0053】再成長基板の昇温開始後、AsH3、DE
Znを再成長基板上に供給開始し、基板温度が750℃
まで上昇した後、前記基板温度を640℃まで降温す
る。その後、AsH3、DEZnの基板への供給を一時
停止しTMGa、SiH4を再成長基板上に供給する。
その後、III族元素を含む原料化合物の供給量(TM
Ga供給量または、TMGa供給量とTMAl供給量の
和)とV族元素を含む原料化合物の供給量(AsH3
の比を120とし、AsH3、TMAl、TMGa、S
iH4を再成長基板上に供給すると同時に前記基板温度
を700℃まで昇温して、Si添加n型AlGaAs電
流ブロック層9の結晶成長を行った。
After the start of heating the regrown substrate, AsH 3 , DE
Starting supply of Zn onto the regrown substrate, and substrate temperature of 750 ° C.
Then, the substrate temperature is lowered to 640 ° C. Thereafter, supply of AsH 3 and DEZn to the substrate is temporarily stopped, and TMGa and SiH 4 are supplied onto the regrown substrate.
Then, the supply amount of the raw material compound containing the group III element (TM
Ga supply amount or the sum of TMGa supply amount and TMAl supply amount) and supply amount of raw material compound containing group V element (AsH 3 )
Of AsH 3 , TMAl, TMGa, S
At the same time as supplying iH 4 onto the regrowth substrate, the substrate temperature was raised to 700 ° C. to grow a crystal of the Si-added n-type AlGaAs current block layer 9.

【0054】以上の方法によって得られた本発明の半導
体レーザ素子の電流ブロック部の不純物分析を2次イオ
ン質量分析(SIMS)装置で測定し、得られた結果を
図12に示す。又、比較のため、AsH3をSi添加n
型GaAs基板上に供給開始し、基板温度が750℃に
安定後、AsH3、TMGa、SiH4をSi添加n型G
aAs基板上に供給し、Si添加n型GaAsバッファ
層の結晶成長を開始する従来方法で得られた半導体レー
ザ素子の電流ブロック部の不純物分析を2次イオン質量
分析(SIMS)装置で測定し、得られた結果を図13
に示す。図12、図13において横軸は成長膜深さを表
し、縦軸は亜鉛(Zn)及びシリコン(Si)の不純物
濃度を表す。
The impurity analysis of the current block portion of the semiconductor laser device of the present invention obtained by the above method was measured by a secondary ion mass spectrometer (SIMS), and the obtained result is shown in FIG. For comparison, AsH 3 was added with Si.
Is started on a GaAs substrate, and after the substrate temperature is stabilized at 750 ° C., AsH 3 , TMGa, and SiH 4 are doped with Si-added n-type G.
An impurity analysis of a current block portion of a semiconductor laser device obtained by a conventional method of supplying crystal onto an aAs substrate and starting crystal growth of a Si-doped n-type GaAs buffer layer is measured by a secondary ion mass spectrometer (SIMS). FIG. 13 shows the obtained results.
Shown in 12 and 13, the horizontal axis represents the depth of the grown film, and the vertical axis represents the impurity concentrations of zinc (Zn) and silicon (Si).

【0055】図12と図13において、p型AlGaA
s第一クラッド層内のZnの拡散が図12では起こって
いないが、図13ではn型クラッド層、n型電流ブロッ
ク層にZnが拡散しており、p型AlGaAs第一クラ
ッド層では所定の不純物添加量である8×1017/cm
3になっていない。このことから、本発明の結晶成長方
法を用いることにより、不純物添加物の制御が正確に行
うことができることがわかる。また、結晶成長後の転位
欠陥密度も、従来方法では1×105/cm2であるが、
本発明の結晶成長方法を用いることにより、5×103
/cm2と飛躍的に低減可能となっている。
Referring to FIGS. 12 and 13, p-type AlGaAs
Although the diffusion of Zn in the s first cladding layer does not occur in FIG. 12, Zn diffuses in the n-type cladding layer and the n-type current blocking layer in FIG. 8 × 10 17 / cm, the amount of impurity added
Not 3 This shows that the use of the crystal growth method of the present invention enables accurate control of impurity additives. Also, the dislocation defect density after crystal growth is 1 × 10 5 / cm 2 in the conventional method,
By using the crystal growth method of the present invention, 5 × 10 3
/ Cm 2 .

【0056】本発明の半導体レーザ素子は再現性も良
く、また従来方法による半導体レーザ素子と比較する
と、歩留まりが飛躍的に向上した。また、信頼性におい
ても、60℃、35mWの信頼性試験においても500
0時間以上安定に走行しており、このことから、高品質
で高信頼性である半導体レーザ素子が作成可能となるこ
とがわかる。
The semiconductor laser device of the present invention has a good reproducibility, and the yield is significantly improved as compared with the semiconductor laser device according to the conventional method. Also, in the reliability test at 60 ° C. and 35 mW, 500
The vehicle travels stably for 0 hour or more, which indicates that a high-quality and highly reliable semiconductor laser device can be manufactured.

【0057】(実施例5)本実施例では、本発明の結晶
成長方法を用いた発光ダイオードについて説明する。
Embodiment 5 In this embodiment, a light emitting diode using the crystal growth method of the present invention will be described.

【0058】図14は実施例5の発光ダイオード素子の
断面図である。Si添加n型GaAs基板15上に、S
i添加n型AlInPクラッド層16、AlGaInP
活性層17、p型AlInPクラッド層18、p型Ga
P電流拡散層19が順次積層される。p型GaP電流拡
散層19の上にはp側金属電極20、Si添加n型Ga
As基板15上にはn側金属電極21が蒸着されてい
る。
FIG. 14 is a sectional view of a light emitting diode element according to the fifth embodiment. On the Si-added n-type GaAs substrate 15, S
i-doped n-type AlInP cladding layer 16, AlGaInP
Active layer 17, p-type AlInP cladding layer 18, p-type Ga
P current diffusion layers 19 are sequentially stacked. On the p-type GaP current diffusion layer 19, a p-side metal electrode 20, a Si-added n-type Ga
An n-side metal electrode 21 is deposited on the As substrate 15.

【0059】上記発光ダイオード素子のSi添加n型A
lInPクラッド層16〜p型GaP電流拡散層19の
各層は、Ga原料としてトリメチルガリウム(TMG
a)、Al原料としてトリメチルアルミニウム(TMA
l)、ln原料としてトリメチルインジウム(TMI
n)と、As原料としてアルシン(AsH3)、P原料
としてホスフィン(PH3)、n型不純物であるSi原
料としてシラン(SiH4)、p型不純物あるZn原料
としてジエチルジンク(DEZn)を用い、使用した装
置は、減圧横型高周波加熱炉の気相成長装置で、炉内圧
力は76Torrで行った。
The Si-doped n-type A of the above light emitting diode element
Each layer of the lInP cladding layer 16 to the p-type GaP current spreading layer 19 is made of trimethyl gallium (TMG
a), trimethyl aluminum (TMA)
l), ln as raw material trimethylindium (TMI)
n), arsine (AsH 3 ) as an As material, phosphine (PH 3 ) as a P material, silane (SiH 4 ) as a Si material as an n-type impurity, and diethyl zinc (DEZn) as a Zn material as a p-type impurity. The apparatus used was a vapor-phase growth apparatus of a reduced-pressure horizontal high-frequency heating furnace, and the furnace pressure was set to 76 Torr.

【0060】Si添加n型GaAs基板15の昇温開始
後、AsH3をSi添加n型GaAs基板15上に供給
開始し、基板温度が770℃に安定後、AsH3の基板
への供給を停止しTMAl、TMIn、SiH4をSi
添加n型GaAs基板上に供給する。その後、TMA
l、TMIn、SiH4の基板への供給を一時停止し、
PH3をSi添加n型GaAs基板上に供給する。その
後、III族元素を含む原料化合物の供給量(TMGa
供給量とTMAl供給量とTMIn供給量の和)とV族
元素を含む原料化合物の供給量(PH3)の比を300
とし、PH3、TMAl、TMIn、SiH4をSi添加
n型GaAs基板15上に供給し、Si添加n型AlI
nPクラッド層16の結晶成長を開始し、順次成長を行
った。
After starting the temperature increase of the Si-added n-type GaAs substrate 15, supply of AsH 3 is started on the Si-added n-type GaAs substrate 15, and after the substrate temperature is stabilized at 770 ° C., the supply of AsH 3 to the substrate is stopped. TMAl, TMIn, SiH 4 to Si
It is supplied on an additive n-type GaAs substrate. Then TMA
1, the supply of TMIn, SiH 4 to the substrate is temporarily stopped,
PH 3 is supplied on a Si-doped n-type GaAs substrate. Thereafter, the supply amount of the raw material compound containing the group III element (TMGa
(The sum of the supply amount, the TMAl supply amount, and the TMIn supply amount) and the supply amount (PH 3 ) of the raw material compound containing the group V element are set to 300.
Then, PH 3 , TMAl, TMIn, and SiH 4 are supplied onto the Si-added n-type GaAs substrate 15 and the Si-added n-type AlI
Crystal growth of the nP cladding layer 16 was started, and growth was performed sequentially.

【0061】以上の方法によって得られた本発明の発光
ダイオードの転位欠陥密度は、従来に比べて、飛躍的に
低減された結果、AlGaInP活性層17及びSi添
加n型AlInPクラッド層16への亜鉛の拡散が低減
されていることにより、輝度が飛躍的に向上しており、
このことから、高品質で高輝度である発光ダイオードが
作成可能となることがわかる。
The dislocation defect density of the light emitting diode of the present invention obtained by the above-described method is remarkably reduced as compared with the prior art, and as a result, the zinc in the AlGaInP active layer 17 and the Si-added n-type AlInP cladding layer 16 is reduced. Is reduced, the brightness is dramatically improved,
This indicates that a light emitting diode with high quality and high luminance can be manufactured.

【0062】(実施例6)本実施例では、Si添加Ga
As基板上へのMBEによるSi添加GaAs結晶膜成
長方法について説明する。
(Embodiment 6) In this embodiment, Si-doped Ga
A method for growing a Si-doped GaAs crystal film on an As substrate by MBE will be described.

【0063】Si添加GaAs基板上にSi添加GaA
s薄膜を成長するのにMBE結晶成長法を用いて、結晶
成長を行った。結晶成長は、図4のシーケンスの様に行
った。Si添加n型GaAs基板をロードロックチャン
バーに導入、真空引き後、基板を250℃に加熱し、基
板表面の水分除去を行った後、成長チャンバーに基板を
搬送した。搬送後Asセルのシャッターを開けAsを基
板表面に供給し、基板温度を620℃まで上昇させ、そ
の後、前記基板温度を480℃まで降温する。その後、
Asの供給を一時停止し、Ga、Siセルのシャッター
を開け、Si添加n型GaAs基板上に供給する。その
後、Asセルのシャッターを再び開け、As、Ga、S
iをSi添加n型GaAs基板上に供給すると同時に前
記基板温度を620℃まで昇温して、Si添加GaAs
薄膜の結晶成長を行った。成長時間は90minで1.
5μmの厚さを有するSi添加n型GaAs薄膜が得ら
れた。
On a Si-doped GaAs substrate, a Si-doped GaAs
Crystal growth was performed using the MBE crystal growth method to grow the s thin film. The crystal growth was performed according to the sequence shown in FIG. The Si-added n-type GaAs substrate was introduced into the load lock chamber, and after evacuation, the substrate was heated to 250 ° C. to remove water from the substrate surface, and then transferred to the growth chamber. After the transfer, the shutter of the As cell is opened, As is supplied to the substrate surface, the substrate temperature is raised to 620 ° C, and then the substrate temperature is lowered to 480 ° C. afterwards,
The supply of As is temporarily stopped, the shutter of the Ga and Si cells is opened, and the supply of As is performed on the Si-doped n-type GaAs substrate. Then, the shutter of the As cell is opened again, and As, Ga, S
i is supplied onto the Si-doped n-type GaAs substrate, and at the same time, the substrate temperature is raised to 620 ° C.
Crystal growth of the thin film was performed. The growth time is 1.
A Si-added n-type GaAs thin film having a thickness of 5 μm was obtained.

【0064】得られた成長層の不純物分析を2次イオン
質量分析(SIMS)装置で測定した結果、Si添加n
型GaAs基板とSi添加GaAs薄膜の界面での酸素
濃度が、図4に記載されている第二工程を除いた成長法
で得られた膜に比べ、本発明の結晶成長方法を用いるこ
とにより、低減されていた。
As a result of impurity analysis of the obtained grown layer measured by a secondary ion mass spectrometer (SIMS), it was found that
By using the crystal growth method of the present invention, the oxygen concentration at the interface between the type GaAs substrate and the Si-doped GaAs thin film is larger than that of the film obtained by the growth method excluding the second step described in FIG. Had been reduced.

【0065】以上より、本発明の結晶成長方法を用いる
ことにより、高品質なSi添加GaAs薄膜を作製する
ことが可能であることがわかる。
From the above, it can be understood that a high quality Si-doped GaAs thin film can be produced by using the crystal growth method of the present invention.

【0066】また、上記全ての実施例に於いて、第一工
程、第二工程の原料供給・停止の切り替えは、成長温度
が一定にならない間に切り替えても、Si添加AlGa
As薄膜の酸素濃度及び結晶成長後の転位欠陥密度には
特に関係しない。しかし、結晶成長の原料供給は、基板
温度がある一定温度まで上昇した後に行う方が、Si添
加量の制御が容易になるという点で好ましい。より好ま
しくは、基板温度が650℃以上になってから結晶成長
を行う方が、膜中に酸素を取り込みにくくなるため、結
晶品質の低下を防ぐことが可能となる。
In all of the above embodiments, the switching between the supply and the stop of the raw material in the first step and the second step is performed even if the switching is performed while the growth temperature is not constant.
There is no particular relation to the oxygen concentration of the As thin film and the dislocation defect density after crystal growth. However, it is preferable to supply the raw material for crystal growth after the substrate temperature is raised to a certain temperature, since the control of the amount of added Si becomes easy. More preferably, when crystal growth is performed after the substrate temperature has reached 650 ° C. or higher, oxygen is less likely to be taken into the film, so that deterioration in crystal quality can be prevented.

【0067】[0067]

【発明の効果】以上説明したとおり、本発明は、III
−V族化合物半導体結晶層が表面に形成されている結晶
基板の上にSiを添加したIII−V族化合物半導体結
晶を結晶成長する気相成長法において、結晶成長開始前
の過程で、第一の工程;V族原料を前記結晶基板上に供
給する第二の工程;V族原料を前記結晶基板上に供給す
るのを中断し、Si原料とIII族原料を前記結晶基板
上に供給するを行った後、V族原料とSi原料とIII
族原料を前記結晶基板上に供給し、III−V族化合物
半導体結晶層の結晶成長を行うことにより、酸素原子に
起因した点欠陥及び基板表面のダメージに起因した転位
欠陥を低減することが可能となり、欠陥に寄与した添加
不純物の拡散を抑制することが可能となるので、結晶基
板上に良好な結晶性を有するIII−V族化合物半導体
結晶を結晶成長することができ、半導体レーザ、LED
等の半導体発光素子の特性向上に寄与するところが大き
い。
As described above, the present invention relates to III
In a vapor phase growth method for growing a group III-V compound semiconductor crystal to which Si is added on a crystal substrate having a group V compound semiconductor crystal layer formed on the surface, a first step is performed before starting crystal growth. Supplying a group V material onto the crystal substrate; stopping supplying the group V material onto the crystal substrate, and supplying a Si material and a group III material onto the crystal substrate. After performing, group V raw material, Si raw material and III
By supplying a group III raw material onto the crystal substrate and performing crystal growth of the group III-V compound semiconductor crystal layer, it is possible to reduce point defects caused by oxygen atoms and dislocation defects caused by damage to the substrate surface. Since it becomes possible to suppress the diffusion of the additional impurity that has contributed to the defect, it is possible to grow a group III-V compound semiconductor crystal having good crystallinity on a crystal substrate, and to obtain a semiconductor laser, an LED.
Greatly contribute to the improvement of the characteristics of the semiconductor light emitting device.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の原料ガスのシーケンスを表す図であ
る。
FIG. 1 is a diagram showing a source gas sequence of the present invention.

【図2】本発明の原料ガスのシーケンスを表す図であ
る。
FIG. 2 is a diagram showing a sequence of a source gas of the present invention.

【図3】従来方法の原料ガスのシーケンスを表す図であ
る。
FIG. 3 is a diagram showing a sequence of a source gas in a conventional method.

【図4】本発明のMBEセルのシーケンスを表す図であ
る。
FIG. 4 is a diagram illustrating a sequence of an MBE cell according to the present invention.

【図5】本発明の原料ガス及び基板温度のシーケンスを
表す図である。
FIG. 5 is a diagram showing a sequence of a source gas and a substrate temperature according to the present invention.

【図6】本発明方法によるIII−V族化合物半導体結
晶の原子配置図である。
FIG. 6 is an atomic arrangement diagram of a group III-V compound semiconductor crystal according to the method of the present invention.

【図7】従来方法によるIII−V族化合物半導体結晶
の原子配置図である。
FIG. 7 is an atomic arrangement diagram of a group III-V compound semiconductor crystal according to a conventional method.

【図8】本発明方法によるIII−V族化合物半導体結
晶のSIMS測定結果を表す図である。
FIG. 8 is a diagram showing a result of SIMS measurement of a group III-V compound semiconductor crystal according to the method of the present invention.

【図9】第一の従来方法によるIII−V族化合物半導
体結晶のSIMS測定結果を表す図である。
FIG. 9 is a diagram showing a SIMS measurement result of a group III-V compound semiconductor crystal according to a first conventional method.

【図10】第二の従来方法によるIII−V族化合物半
導体結晶のSIMS測定結果を表す図である。
FIG. 10 is a diagram showing a result of SIMS measurement of a group III-V compound semiconductor crystal by the second conventional method.

【図11】実施例4の半導体レーザ素子の断面図であ
る。
FIG. 11 is a sectional view of a semiconductor laser device of Example 4.

【図12】本発明方法による半導体レーザ素子の電流ブ
ロック部のSIMS測定結果を表す図である。
FIG. 12 is a diagram illustrating a SIMS measurement result of a current block portion of a semiconductor laser device according to the method of the present invention.

【図13】従来方法による半導体レーザ素子の電流ブロ
ック部のSIMS測定結果を表す図である。
FIG. 13 is a diagram showing a SIMS measurement result of a current block portion of a semiconductor laser device according to a conventional method.

【図14】実施例5の発光ダイオードの断面図である。FIG. 14 is a sectional view of a light emitting diode according to a fifth embodiment.

【符号の説明】[Explanation of symbols]

1、15 Si添加n型GaAs基板 2 Si添加n型GaAsバッファ層 3 n型AlGaAsクラッド層 4 AlGaAs活性層 5 p型AlGaAs第一クラッド層 6 p型GaAsエッチングストップ層 7 p型AlGaAs第二クラッド層 8 p型GaAs保護層 9 Si添加n型AlGaAs電流ブロック層 10 n型GaAs電流ブロック層 11 p型GaAs平坦化層 12 p型GaAsコンタクト層 13、20 p側金属電極 14、21 n側金属電極 16 Si添加n型AlInPクラッド層 17 AlGaInP活性層 18 p型AlInPクラッド層 19 p型GaP電流拡散層 1, 15 Si-doped n-type GaAs substrate 2 Si-doped n-type GaAs buffer layer 3 n-type AlGaAs cladding layer 4 AlGaAs active layer 5 p-type AlGaAs first cladding layer 6 p-type GaAs etching stop layer 7 p-type AlGaAs second cladding layer Reference Signs List 8 p-type GaAs protective layer 9 Si-doped n-type AlGaAs current blocking layer 10 n-type GaAs current blocking layer 11 p-type GaAs planarization layer 12 p-type GaAs contact layer 13, 20 p-side metal electrode 14, 21 n-side metal electrode 16 Si-doped n-type AlInP cladding layer 17 AlGaInP active layer 18 p-type AlInP cladding layer 19 p-type GaP current diffusion layer

Claims (7)

【特許請求の範囲】[Claims] 【請求項1】 III−V族化合物半導体結晶層が表面
に形成されている結晶基板の上にSiを添加したIII
−V族化合物半導体結晶を結晶成長する気相成長法にお
いて、結晶成長開始前の過程で、 第一の工程;V族元素を含む原料化合物を前記結晶基板
上に供給する第二の工程;V族原料を前記結晶基板上に
供給するのを中断し、Si原料とIII族原料を前記結
晶基板上に供給するを行った後、V族原料とSi原料と
III族原料を前記結晶基板上に供給し、III−V族
化合物半導体結晶層の結晶成長を行うことを特徴とする
III−V族化合物半導体の気相成長方法。
1. A semiconductor comprising a group III-V compound semiconductor crystal layer on a surface of which a silicon is added.
In a vapor phase growth method for growing a group V compound semiconductor crystal, a first step; a step of supplying a raw material compound containing a group V element onto the crystal substrate; After the supply of the group V raw material onto the crystal substrate is interrupted and the supply of the Si raw material and the group III raw material onto the crystal substrate is performed, the group V raw material, the Si raw material, and the group III raw material are placed on the crystal substrate. A method for vapor-phase growing a group III-V compound semiconductor, comprising supplying and growing a group III-V compound semiconductor crystal layer.
【請求項2】 III−V族化合物半導体結晶層が表面
に形成されている結晶基板の上にSiを添加したIII
−V族化合物半導体結晶を結晶成長する気相成長法にお
いて、結晶成長開始前の過程で、 第一の工程;V族原料を前記結晶基板上に供給する第二
の工程;V族原料を前記結晶基板上に供給するのを中断
し、Si原料とIII族原料を前記結晶基板上に供給す
る第三の工程;Si原料とIII族原料を前記結晶基板
上に供給するのを中断し、V族原料を前記結晶基板上に
供給するを行った後、V族原料とSi原料とIII族原
料を前記結晶基板上に供給し、III−V族化合物半導
体結晶層の結晶成長を行うことを特徴とするIII−V
族化合物半導体の気相成長方法。
2. A III-V compound semiconductor crystal layer, comprising a crystal substrate having a surface on which a Si-added III is formed.
In a vapor phase growth method for growing a group V compound semiconductor crystal, a first step; a second step of supplying a group V material onto the crystal substrate; A third step of interrupting the supply of the Si source and the group III source onto the crystal substrate; and stopping the supply of the Si source and the group III source onto the crystal substrate; After supplying the group V raw material onto the crystal substrate, supplying a group V raw material, a Si raw material, and a group III raw material onto the crystal substrate, and performing crystal growth of a III-V compound semiconductor crystal layer. III-V
A vapor phase growth method for a group III compound semiconductor.
【請求項3】 前記III−V族化合物半導体結晶層が
表面に形成されている結晶基板の最表面層にSiが含ま
れていることを特徴とする請求項1、2のいずれかに記
載のIII−V族化合物半導体の気相成長方法。
3. The crystal substrate according to claim 1, wherein the outermost surface layer of the crystal substrate on which the III-V compound semiconductor crystal layer is formed contains Si. A vapor phase growth method for a III-V compound semiconductor.
【請求項4】 前記III−V族化合物半導体結晶層が
表面に形成されている結晶基板の最表面層にAlが含ま
れていることを特徴とする請求項1、2のいずれかに記
載のIII−V族化合物半導体の気相成長方法。
4. The crystal substrate according to claim 1, wherein the outermost surface layer of the crystal substrate on which the III-V compound semiconductor crystal layer is formed contains Al. A vapor phase growth method for a III-V compound semiconductor.
【請求項5】 前記第一の工程は、III−V族化合物
半導体結晶層が表面に形成されている結晶基板の温度を
600℃以上850℃以下の温度まで昇温することを特
徴とする請求項1〜4のいずれかに記載のIII−V族
化合物半導体の気相成長方法。
5. The method according to claim 1, wherein in the first step, the temperature of the crystal substrate on which the III-V compound semiconductor crystal layer is formed is raised to a temperature of 600 ° C. or more and 850 ° C. or less. Item 5. The method for vapor-phase growth of a group III-V compound semiconductor according to any one of items 1 to 4.
【請求項6】 前記第二の工程は、III−V族化合物
半導体結晶層が表面に形成されている結晶基板の温度が
550℃以上650℃以下の温度になる期間を含むこと
を特徴とする請求項1〜5のいずれかに記載のIII−
V族化合物半導体の気相成長方法。
6. The method according to claim 1, wherein the second step includes a period in which the temperature of the crystal substrate on which the III-V compound semiconductor crystal layer is formed is 550 ° C. or more and 650 ° C. or less. III- according to any one of claims 1 to 5.
A vapor phase growth method for a group V compound semiconductor.
【請求項7】 n型添加不純物にSiを用いるIII−
V族化合物半導体発光素子において、請求項1〜6のい
ずれかに記載のIII−V族化合物半導体の気相成長方
法を用いて作製されたことを特徴とするIII−V族化
合物半導体発光素子。
7. The method according to claim 1, wherein Si is used as the n-type additive impurity.
A III-V compound semiconductor light-emitting device, which is manufactured using the method for vapor-phase growing a III-V compound semiconductor according to claim 1.
JP30548397A 1997-11-07 1997-11-07 Vapor growth method for group iii-v compound semiconductor, and light emitting element Pending JPH11145061A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP30548397A JPH11145061A (en) 1997-11-07 1997-11-07 Vapor growth method for group iii-v compound semiconductor, and light emitting element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP30548397A JPH11145061A (en) 1997-11-07 1997-11-07 Vapor growth method for group iii-v compound semiconductor, and light emitting element

Publications (1)

Publication Number Publication Date
JPH11145061A true JPH11145061A (en) 1999-05-28

Family

ID=17945711

Family Applications (1)

Application Number Title Priority Date Filing Date
JP30548397A Pending JPH11145061A (en) 1997-11-07 1997-11-07 Vapor growth method for group iii-v compound semiconductor, and light emitting element

Country Status (1)

Country Link
JP (1) JPH11145061A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009111292A (en) * 2007-10-31 2009-05-21 Sumco Corp Method and device for manufacturing epitaxial wafer
CN114341408A (en) * 2019-07-09 2022-04-12 集成太阳能公司 Method for controlled n-doping of III-V materials grown on (111) Si

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009111292A (en) * 2007-10-31 2009-05-21 Sumco Corp Method and device for manufacturing epitaxial wafer
CN114341408A (en) * 2019-07-09 2022-04-12 集成太阳能公司 Method for controlled n-doping of III-V materials grown on (111) Si

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