JPH0832113A - Manufacture of p-type gan semiconductor - Google Patents

Abstract

PURPOSE:To provide a p-type GaN semiconductor manufacturing method by which the fraction defective of a p-type GaN semiconductor can be reduced by suppressing the cracking of the semiconductor and the cost of the semiconductor can be reduced by simplifying the manufacturing process. CONSTITUTION:In a p-type GaN semiconductor manufacturing method, a GaN semiconductor doped with a p-type impurity is cooled at a cooling rate slower than the natural cooling rate in, desirably, an inert gas atmosphere after the semiconductor is grown. Therefore, no post-treatment-like heat treatment is required for the semiconductor after the semiconductor is grown and, since the semiconductor is gradually cooled, the cracking of the semiconductor is suppressed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a p-type GaN-based semiconductor, and more particularly to a method for manufacturing a p-type GaN-based semiconductor which can simplify the manufacturing process to reduce the cost and the defect rate. Regarding

[0002]

2. Description of the Related Art As a semiconductor constituting a light emitting device such as an LED or an LD, for example, a general formula Al _x Ga _y In _1-xy N
(Where 0 ≦ x ≦ 1, 0 ≦ y ≦ 1),
It is known that a so-called GaN-based semiconductor can be used to obtain a blue light emitting device that exhibits excellent light emitting characteristics at room temperature. FIG. 1 is an example of a general light emitting diode (LED) using such a GaN-based semiconductor. A light emitting diode D shown in FIG. 1 is a substrate 1 made of, for example, sapphire, SiC, or the like. N-type GaN clad layer 31, GaInN active layer 32 via the buffer layer 2 made of
And the p-type GaN clad layer 33 are grown in this order by vapor phase epitaxy.

In the above GaN-based semiconductor, since the semiconductor is of n-type / p-type conductivity type, the semiconductor is n-type / p-type.
I try to grow it by doping type impurities,
In the case of p-type, a low-resistance p-type semiconductor cannot be obtained only by growing it by doping with p-type impurities. This is because 1) GaN-based crystals have poor crystallinity and have many nitrogen vacancies in the crystals, so that an n-type semiconductor with low resistance is likely to be obtained without doping impurities. Or 2) during or after the growth of the GaN-based semiconductor, NH ₃ which is an N source is decomposed to generate a hydrogen atom, and the hydrogen atom is a p-type impurity M
It is considered that the main cause is that these p-type impurities bind to g, Zn, etc. to prevent them from functioning as an acceptor, and as a result, the GaN-based semiconductor doped with the p-type impurities exhibits high resistance. Has been.

The above problem 1) can be solved by optimizing the crystal growth conditions to improve the crystallinity of the GaN-based crystal. On the other hand, as a method to solve the problem of 2) above, p
A method is known in which a GaN-based semiconductor doped with a type impurity is grown and then subjected to electron beam irradiation treatment (LEEBI) to reduce the resistance of the GaN-based semiconductor.

However, the above method has a problem in that only the semiconductor surface layer portion into which the electron beam can penetrate can be made low in resistance, and since the electron beam is irradiated while scanning, the wafer surface cannot be made uniformly low in resistance. Further, there is a problem that it takes a long time to scan the electron beam, and this LEEBI treatment must be performed in a process and an apparatus different from the crystal growth step and the apparatus, resulting in high manufacturing cost.

Therefore, a method of obtaining a p-type semiconductor by performing heat treatment (annealing) in a nitrogen atmosphere after growing the semiconductor has been proposed (Japanese Patent Laid-Open No. 5-183).
189). According to this method, a hydrogen atom bonded to Mg, Zn or the like is dissociated by heat treatment to allow Mg, Zn or the like to function normally as an acceptor to obtain a low-resistance p-type semiconductor. It is possible to uniformly reduce the resistance inside and on the entire surface.

[0007]

However, in the above method, there is a problem that cracks are likely to occur due to the difference in thermal expansion coefficient and lattice constant between the semiconductor layers in the process of cooling after the heat treatment, and in this case also. Since a heat treatment process / apparatus is required in addition to the crystal growth process / apparatus, the manufacturing cost is still high.

An object of the present invention is to solve the above problems, suppress the occurrence of cracks and the like, reduce the defect rate, and simplify the manufacturing process to reduce the cost, and a method for manufacturing a p-type GaN-based semiconductor. To provide.

[0009]

The inventors of the present invention have found that an effect equivalent to that of heat treatment can be obtained by gradually cooling a semiconductor after it has been grown, and completed the present invention. It was That is, in the method for manufacturing a p-type GaN-based semiconductor of the present invention, after growing a GaN-based semiconductor doped with a p-type impurity, cooling is preferably performed in an inert gas atmosphere at a slower rate than natural cooling. It is a feature.

[0010]

The present invention maintains the temperature of the semiconductor as high as possible by cooling the semiconductor after growth at a slower rate than natural cooling, thereby obtaining the same effect as in the case of performing heat treatment. It was done like this. That is, by maintaining the temperature of the semiconductor as high as possible, it is possible to suppress the bonding of hydrogen atoms with p-type impurities.
The p-type semiconductor having a low resistance is obtained by allowing the type impurities to function normally as an acceptor.
Therefore, in the present invention, a post-treatment heat treatment is not necessary, and since the semiconductor is gradually cooled, the generation of cracks or the like in the semiconductor layer is suppressed.

Hereinafter, the method for manufacturing the p-type GaN-based semiconductor of the present invention will be described more specifically by taking the case of manufacturing the general light emitting diode D shown in FIG. 1 as an example.

(1) Formation of Semiconductor Layer First, the n-type GaN cladding layer 31, the GaInN active layer 32 and the p-type GaN are formed on the substrate 1 with the buffer layer 2 interposed therebetween.
The clad layer 33 is formed in this order to form the multilayer portion 3 similar to that shown in FIG.

The substrate 1 is preferably one having a lattice constant close to that of the buffer layer 2 and the multilayer portion 3 intended to be formed so that the crystallinity of the buffer layer 2 and the multilayer portion 3 is good, and further, the occurrence of cracks is suppressed as much as possible. As described above, those having a close thermal expansion coefficient are preferable. As such a material, sapphire, SiC, quartz, for example, the general formula Al _x Ga _y In
Examples include GaN-based semiconductors represented by _1-xy N (where 0 ≦ x ≦ 1, 0 ≦ y ≦ 1), and among them, sapphire or GaN-based semiconductors are preferable.

Although the thickness of the substrate 1 is not particularly limited,
It has sufficient mechanical strength and is economically inexpensive. 20
It is suitable that the thickness is about 0 to 300 μm.

The buffer layer 2 is for alleviating the difference in lattice constant and thermal expansion coefficient between the substrate 1 and the multilayer portion 3. For this reason, it is preferable that the buffer layer 2 has a lattice constant as close as possible to that of the crystals forming the substrate 1 and the multilayer portion 3 in order to improve the crystallinity of the multilayer portion 3, and further, the thermal expansion. It is preferable to use those having a coefficient as close as possible in order to prevent the occurrence of cracks and the like.

The buffer layer 2 has the general formula Al _x
Ga _y In _1-xy N (provided that 0 ≦ x ≦ 1,0 ≦ y ≦ 1)
GaN-based semiconductor represented by, ZnO, MgO, B
eO, BeO-ZnO compounds, ZnO-HgO compounds, ZnO-MgO compounds, BeO-ZnO-HgO
Examples thereof include a system compound and a BeO—ZnO—MgO system compound. Particularly, for example, when the multilayer portion 3 is GaInN / GaAlN, AlN or GaN is preferable.

The buffer layer 2 is formed by a method such as sputtering, CVD, MOVPE. When a GaN-based semiconductor is used as the buffer layer 2, for example, when the buffer layer 2 is formed by MOVPE, the buffer layer 2 is formed. It is preferable because the crystallinity of 2 can be improved.

The buffer layer 2 has a thickness of 50 to 1000.
Å, preferably 200 to 500Å. If the thickness of the buffer layer 2 is 50 Å or more, the difference in the lattice constant and the thermal expansion coefficient between the substrate 1 and the multilayer portion 3 can be sufficiently relaxed, while if the thickness is 1000 Å or less, the buffer layer 2 on the The high-quality GaN epitaxial growth layer can be obtained by two-dimensional growth.

As a combination of the respective semiconductor materials of the active layer 32 / cladding layers 31 and 33 constituting the above-mentioned multilayer portion 3, those having lattice constants close to each other so as to obtain good crystallinity are preferable. For example, as shown in FIG. GaI as shown
nN / AlGaN, GaInN / GaN, GaInN
/ AlGaInN and the like are preferable, and GaInN among them is preferable.
/ AlGaN is preferred.

As a method of forming the multi-layer portion 3, MOV is used.
PE, MBE, GS-MBE, MO-MBE, CBE,
A vapor phase growth method such as HVPE is exemplified. For example, when the multilayer portion 3 is made of GaInN / GaN, MOV is used.
PE is preferably used.

The thicknesses of the n-type clad layer 31, the active layer 32 and the p-type clad layer 33 are not particularly limited, but in view of crystallinity of each layer and confinement of electrons and holes, 1 to 5 μm and 100 to 2000 Å, respectively. , 0.3 to 1 μm is suitable.

As the structure of the multi-layer part 3, Homo is
Type, SH (single hetero) type, DH (double hetero)
Type, quantum well type, multi-layer quantum well type, and the like. Among them, when the DH type is used, the cladding layers formed above and below the active layer do not absorb light emitted from the active layer, and electrons for light emission are used. And holes are efficiently confined in the active layer,
The brightness of the light emitting element can be improved.

A method known per se may be used as a method for doping the n-type / p-type impurities into the multi-layer portion 3. For example, while the multi-layer portion 3 is being grown by the vapor phase epitaxy method, an impurity gas is introduced into the reaction vessel. Should be supplied. Examples of the n-type impurity include Si and Ge. Among them, Si is preferable in terms of doping efficiency and crystallinity of the host crystal. As described above, in the case of the GaN-based semiconductor, it is possible to obtain an n-type semiconductor with low resistance without doping impurities. The p-type impurities include Zn, Cd, Be, Mg and C.
a, Ba, etc. are exemplified, and among them, Mg or Zn is preferable in terms of doping efficiency, carrier activation rate, and impurity level.
Is preferred.

(2) Cooling of the semiconductor layer Next, the multilayer portion 3 grown as described above is cooled from the high temperature during growth (usually about 1050 ° C.) to room temperature.

In the present invention, the cooling of the multilayer portion 3 is performed at a slower rate than natural cooling. More specifically, about 0.1 to 3 ° C. per minute, preferably 0.5.
It is desirable that the temperature be lowered at a rate of about 1.5 ° C. When the rate of temperature drop is 3 ° C./min or less, the effect of suppressing the bonding of hydrogen atoms with p-type impurities and the effect of suppressing the occurrence of cracks and the like become sufficient, while 0.1 ° C./minute With the above, the cooling time does not become excessively long and the manufacturing efficiency is maintained at a good level.

The cooling rate can be controlled by using a temperature controller known per se, but for more accurate control, PID (proportional) is used.
Preferably by integral differential control.

After the growth of the multilayer portion 3, it is desirable to remove the hydrogen-containing substance such as NH ₃ from the reaction vessel as much as possible. This makes it possible to more effectively suppress the bond between the hydrogen atom and the p-type impurity generated by the decomposition of the hydrogen-containing substance.

As described above, the hydrogen-containing substance may be removed from the reaction vessel and the multi-layer section 3 may be cooled by keeping the inside of the reaction vessel as close to vacuum as possible. It is more desirable to set below. According to this, it is possible to suppress decomposition and release of nitrogen in the semiconductor layer, and it is possible to improve the crystallinity of the semiconductor layer. Examples of such an inert gas include N ₂ and H
Examples of the gas include e, Ne, Ar, and mixed gases thereof, and among them, N ₂ is preferable. It should be noted that this inert gas is more desirable for suppressing the decomposition of nitrogen when it is pressurized to a pressure higher than the decomposition pressure of the semiconductor layer at the temperature before cooling.

(3) Electrode formation and chip formation After cooling as described above, the upper electrode 4 is formed on the upper surface of the multilayer portion 3 and the lower electrode 5 is formed on the lower surface of the substrate 1, and then this laminated body is diced. To obtain a light emitting diode D.

The upper electrode 4 has a p-layer directly below,
When AuBe, AuZn, Au, etc., or when the immediate underlying layer is an n-layer, AuGe, In, etc. are deposited on the upper surface of the multilayer portion 3 by vacuum deposition or the like, and then patterning, annealing, etc. are applied to an appropriate position on the surface. It is formed by molding into an arbitrary shape. The shape of the upper electrode 4 is not particularly limited, but it is preferable to use a dot electrode because it is easy to form.

The lower electrode 5 is formed by depositing AuBe, AuZn, Au or the like on the lower surface of the substrate 1 when the immediately upper layer is the p layer and by depositing AuGe, In, Al or the like on the lower electrode 5 when the directly upper layer is the n layer. , Is formed by alloying with the substrate 1 by an annealing process.

In the present invention, in addition to the light emitting diode, a laser diode (L
It is also possible to manufacture a light emitting device such as D).

[0033]

EXAMPLES Hereinafter, the present invention will be described more specifically by showing examples. These examples do not limit the present invention.

Example 1 (Formation of Semiconductor Layer) An n-type GaN substrate having a thickness of 300 μm was placed in a reaction vessel, the vessel was evacuated, and trimethylaluminum (TMA) was used as an Al source at 25 μmol / mol.
As a source of N, NH ₃ was introduced at a rate of 5 liters / minute to grow an AlN layer to form a buffer layer having a thickness of 250 Å. Then, in addition to the above gases, 30 μmol / min of trimethylgallium (TMG) as a Ga source and 10 as a Si source.
SiN ₄ of ₄ ppm was introduced at a rate of ₄ nmol / min, and Si-doped n-type G having a thickness of 4 μm was formed on the buffer layer.
An aN clad layer was grown. Then, in addition to the above-mentioned gas, trimethylindium (TMI) 25
μmol / min, TMG 2 μmol / min, Zn instead of SiH ₄
Dimethylzinc (DMZ) was introduced as a source at a rate of 3 μmol / min to grow a Zn-doped GaInN layer having a thickness of 200 Å on the n-type GaN cladding layer. Then, of the above gases, bis (cyclopentadienyl) magnesium (Cp ₂ M) was used as the Mg source instead of DMZ.
g) at a rate of 5 μmol / min to stop the TMI,
Mg-doped layer having a thickness of 0.8 μm on the GaInN layer
GaN layer was grown.

(Cooling of Semiconductor Layer) After the growth of the GaN layer,
The inside of the reaction vessel was replaced with nitrogen, the temperature was lowered at a rate of 0.5 ° C./min by a temperature controller for PID control, and the temperature was cooled to room temperature. A similar LED chip was obtained.

Examples 2 to 3 and Comparative Examples 1 to 2 LED chips were manufactured in the same manner as in Example 1 except that the cooling rate of the semiconductor layer was changed as shown in Table 1.

[0037]

[Table 1]

(Evaluation of Semiconductor) When the hole of the p-type GaN cladding layer was measured for each of the LED chips obtained in Examples 1 to 3 and Comparative Examples 1 to 2, the results shown in Table 1 were obtained. Was given. Further, when the extent of cracking of the semiconductor layer after cooling was examined, it was as shown in Table 1.

[0039]

According to the method for manufacturing a p-type GaN-based semiconductor of the present invention, after the semiconductor is grown, the temperature of the semiconductor is maintained as high as possible by cooling it at a slower rate than natural cooling. The binding of hydrogen atoms to the p-type impurities is suppressed, and as a result, the p-type impurities normally function as an acceptor as in the case of performing heat treatment, whereby a low-resistance p-type semiconductor is obtained. Therefore, no post-treatment heat treatment is required after the semiconductor growth, and the semiconductor is gradually cooled, so that the generation of cracks or the like in the semiconductor layer is suppressed.

Therefore, according to the present invention, it becomes possible to simplify the manufacturing process in the manufacture of the p-type GaN-based semiconductor, reduce the cost, and reduce the defective rate.

[Brief description of drawings]

FIG. 1 is a schematic cross-sectional view showing an example of a general light emitting diode (LED) using a GaN-based semiconductor.

[Explanation of symbols]

 1 substrate 2 buffer layer 3 multilayer part 31 n-type GaN cladding layer 32 GaInN active layer 33 p-type GaN cladding layer 4 upper electrode 5 lower electrode D light emitting diode (LED)

Claims (2)

[Claims] 1. A method of manufacturing a p-type GaN-based semiconductor, which comprises growing a GaN-based semiconductor doped with a p-type impurity and then cooling it at a slower rate than natural cooling. 2. The method for producing a p-type GaN-based semiconductor according to claim 1, wherein cooling is performed in an inert gas atmosphere.