JPH11135696A - Mesa-type semiconductor device - Google Patents
Mesa-type semiconductor deviceInfo
- Publication number
- JPH11135696A JPH11135696A JP9299899A JP29989997A JPH11135696A JP H11135696 A JPH11135696 A JP H11135696A JP 9299899 A JP9299899 A JP 9299899A JP 29989997 A JP29989997 A JP 29989997A JP H11135696 A JPH11135696 A JP H11135696A
- Authority
- JP
- Japan
- Prior art keywords
- chip
- mesa
- diode
- type semiconductor
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Thyristors (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、民生、産業分野で
の電源・音声回路、フライバックトランス、電子レン
ジ、レントゲンおよび自動車のイグニッションシステム
等の高圧整流回路等に使用される、メサ型ダイオードに
関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a mesa diode used for a power supply / voice circuit, a flyback transformer, a microwave oven, an X-ray, and a high-voltage rectifier circuit for an automobile ignition system in the consumer and industrial fields. .
【０００２】[0002]
【従来の技術】ｐｎ接合が半導体基板の側面に露出して
いるメサ型半導体装置、特にメサ型ダイオードは、製造
のし易さから、民生、産業分野での電源・音声回路、フ
ライバックトランス、電子レンジ、レントゲン装置等の
高圧整流回路等に広く使用されている。数ｋＶ〜２０ｋ
Ｖの高圧電源整流用等には、ダイオードチップを積層し
た高圧シリコンダイオードが用いられている。2. Description of the Related Art A mesa semiconductor device having a pn junction exposed on a side surface of a semiconductor substrate, particularly a mesa diode, is a power supply / voice circuit, a flyback transformer, a flyback transformer, etc. Widely used in high-voltage rectifier circuits such as microwave ovens and X-ray devices. Several kV to 20k
For rectifying a high-voltage power supply of V or the like, a high-voltage silicon diode in which diode chips are stacked is used.
【０００３】図１（ａ）はメサ型ダイオードの一例の断
面図である。図において、１はメサ型のダイオードチッ
プ、５はリードであり、２はその間を接合する鉛−錫系
のろう材である。３は表面保護用のパッシベーション
層、４は例えばエポキシ樹脂のモールド樹脂である。図
１（ｂ）、（ｃ）はダイオードチップの平面図であり、
このように角チップの場合と、丸チップの場合とがあ
る。リード５のヘッダー部５ａは通常丸型で、チップの
保護、熱放散等の目的でダイオードチップ５の最大寸法
（角チップなら対角長）より大きくしている。例えばチ
ップが０．５ｍｍ角のとき、ヘッダー部５ａの直径は
０．９ｍｍである。FIG. 1A is a sectional view of an example of a mesa diode. In the figure, 1 is a mesa-type diode chip, 5 is a lead, and 2 is a lead-tin-based brazing material joining between them. Reference numeral 3 denotes a passivation layer for protecting the surface, and reference numeral 4 denotes a mold resin such as an epoxy resin. FIGS. 1B and 1C are plan views of a diode chip.
Thus, there are a case of a square chip and a case of a round chip. The header portion 5a of the lead 5 is generally round, and is larger than the maximum dimension (diagonal length for a square chip) of the diode chip 5 for the purpose of protecting the chip, dissipating heat, and the like. For example, when the chip is 0.5 mm square, the diameter of the header portion 5a is 0.9 mm.
【０００４】図１のメサ型ダイオードは、ダイオードウ
ェハの製作→メタライズ→ダイシング→ダイオードチッ
プ１のエッチング→ダイオードチップ１とリード５との
接合→パッシベーション層３の塗布→樹脂モールドとい
う工程で製造される。図２（ａ）は高圧シリコンダイオ
ードの断面図である。１〜５は図１と同じである。ただ
し高圧シリコンダイオードでは、ダイオードチップ１同
士を接合するろう材２ａがはさまれている。このろう材
２ａは、端のろう材２と組成を変えることがある。この
場合も図２（ｂ）、（ｃ）のように、角チップの場合
と、丸チップの場合とがある。また、リード５のヘッダ
ー部５ａは通常丸型で、ダイオードチップ１より大き
い。製造工程においてダイオードチップ１をエッチング
する工程があるので、ダイオードチップ１間のろう材２
ａは、ダイオードチップ１からはみ出した形になってい
る。The mesa diode shown in FIG. 1 is manufactured in the following steps: diode wafer fabrication → metallization → dicing → diode chip 1 etching → diode chip 1 and lead 5 bonding → passivation layer 3 coating → resin molding. . FIG. 2A is a sectional view of a high-voltage silicon diode. 1 to 5 are the same as in FIG. However, in the high-voltage silicon diode, the brazing material 2a that joins the diode chips 1 is sandwiched. The brazing material 2a may have a different composition from the brazing material 2 at the end. Also in this case, as shown in FIGS. 2B and 2C, there are a case of a square chip and a case of a round chip. The header 5a of the lead 5 is generally round and larger than the diode chip 1. Since there is a step of etching the diode chip 1 in the manufacturing process, the brazing material 2 between the diode chips 1 is formed.
a has a shape protruding from the diode chip 1.
【０００５】[0005]
【発明が解決しようとする課題】上記のような高圧整流
回路で使用されているダイオードに速い立ち上がりの逆
電圧（逆サージ電圧）がかかる場合がある。逆サージ電
圧がかかった時、ダイオードを破壊させないために次の
ような対策を講じて逆サージ耐量の向上を図ってきた。The diode used in the above-mentioned high voltage rectifier circuit may be applied with a fast rising reverse voltage (reverse surge voltage). When a reverse surge voltage is applied, the following measures have been taken to prevent the diode from being destroyed, and the reverse surge withstand capability has been improved.
【０００６】ダイオードの耐圧を上げる。 ダイオードチップのｎベース層（またはｐベース層）
の比抵抗を下げる。 ｎベース層（またはｐベース層）の厚さを厚くし、か
つアバランシェ型のダイオードチップとする。 しかし、現状の高耐圧ダイオードは未だ十分な逆サージ
耐量を有しているとはいえない。The breakdown voltage of the diode is increased. N base layer (or p base layer) of diode chip
The specific resistance. The thickness of the n-base layer (or p-base layer) is increased, and an avalanche-type diode chip is formed. However, the current high breakdown voltage diode cannot be said to have sufficient reverse surge withstand capability yet.
【０００７】特性解析の結果、逆サージ耐量を向上させ
るためには、ダイオードチップの設計だけでなく、パッ
シベーション層に未塗布部やボイドがないこと、均一に
必要な厚さ以上に塗られていること、及び密着性が良い
こと等が重要であることがわかった。パッシベーション
層に未塗布部分やボイドができると、パッシベーション
層本来の能力より絶縁性能が大きく落ちるため、逆サー
ジ耐量の最も弱いチップ表面での絶縁性能が支配的にな
るのであろう。As a result of the characteristic analysis, in order to improve the reverse surge withstand capability, not only the diode chip is designed but also the passivation layer has no uncoated portions or voids, and is uniformly coated to a required thickness or more. And good adhesion were found to be important. If an uncoated portion or a void is formed in the passivation layer, the insulation performance is much lower than the intrinsic ability of the passivation layer, so that the insulation performance on the chip surface having the weakest reverse surge resistance will be dominant.
【０００８】本発明の課題は、パッシベーション層の塗
布を均一で密着性が高いものとすることにより、更に高
い逆サージ耐量を有するメサ型半導体装置を提供するこ
とにある。An object of the present invention is to provide a mesa-type semiconductor device having a higher reverse surge withstand capability by making the application of a passivation layer uniform and having high adhesion.
【０００９】[0009]
【課題を解決するための手段】パッシベーション層の密
着性に影響する因子としては、ダイオードチップの寸
法とリードのヘッダー部との間の段差、ハンダ突起部
とチップとの段差、パッシベーション用絶縁材の粘度
が考えられる。の差が大きいと、ダイオードチップと
リードのヘッダーとの接合部近傍のパッシベーション層
の密着性および均一性が悪く、未塗布部やボイドが発生
する場合がある。特にダイオードチップが一枚のメサ型
ダイオードの場合は、パッシベーション層が二つのヘッ
ダー間で、ブリッジ状になり、チップ表面への濡れが不
十分となり、未塗布部或いはボイドの発生する可能性が
高くなる。の段差が大きいと、やはりダイオードチッ
プとろう材との接合部近傍にボイドが発生する場合があ
る。の粘度が大きいと、ボイドやブリッジの発生を増
加させる。The factors that affect the adhesion of the passivation layer include a step between the dimension of the diode chip and the header of the lead, a step between the solder protrusion and the chip, and a step of insulating material for passivation. Viscosity is possible. If the difference is large, the adhesion and uniformity of the passivation layer near the junction between the diode chip and the header of the lead are poor, and an uncoated portion or a void may be generated. In particular, when the diode chip is a single mesa diode, the passivation layer becomes a bridge between the two headers, so that the wettability of the chip surface becomes insufficient, and there is a high possibility that uncoated portions or voids will occur. Become. If the step is large, voids may also occur near the junction between the diode chip and the brazing material. When the viscosity is high, the occurrence of voids and bridges is increased.
【００１０】の絶縁材の粘度については、作業性等か
ら現在使用中のものと大幅に変えることは困難である。
従って、これまでのものをそのまま使い、パッシベーシ
ョン層の濡れ状況についてヘッダ直径と、エッチング量
を変える実験をおこない、次の結論を得た。の段差に
ついては、ダイオードチップの厚さが０．２ｍｍ以上の
場合、段差０．２ｍｍ以下であれば、ブリッジは殆ど起
きない。いいかえるとダイオードチップの厚さより深い
段差をつくると危険ということになる。It is difficult to greatly change the viscosity of the insulating material from that currently in use due to workability and the like.
Therefore, an experiment was performed in which the header diameter and the etching amount were changed with respect to the wetting condition of the passivation layer, using the conventional one, and the following conclusions were obtained. When the thickness of the diode chip is 0.2 mm or more, the bridge hardly occurs when the step is 0.2 mm or less. In other words, it is dangerous to make a step deeper than the thickness of the diode chip.
【００１１】の段差については、６０μｍ以下のグル
ープでは、それ以上のグループに比べややボイドが減少
する傾向が見られた。ダイオードチップの厚さとの比較
でいうとダイオードチップの厚さに対するエッチング量
の比率（エッチング量／チップ厚）を０．２５以下とす
ることがよい。以上から上記課題解決のための手段とし
ては、ｐｎ接合を有するメサ型半導体チップの両主面に
ヘッダ付きのリードをろう付けし、エッチングした側面
をパッシベーション層で被い、トランスファーモールド
してなるメサ型半導体装置において、リードのヘッダー
部が半導体チップの最大寸法より大きく、かつヘッダー
部と半導体チップとの間の段差の最大部分が、半導体チ
ップの厚さより小さくするものとする。Regarding the step, the voids tended to be slightly reduced in the group of 60 μm or less as compared with the group of more than 60 μm. In comparison with the thickness of the diode chip, the ratio of the etching amount to the diode chip thickness (etching amount / chip thickness) is preferably 0.25 or less. As described above, as a means for solving the above problem, a mesa semiconductor chip having a pn junction is formed by brazing leads with headers to both main surfaces, covering the etched side surfaces with a passivation layer, and performing transfer molding. In the type semiconductor device, it is assumed that the header portion of the lead is larger than the maximum dimension of the semiconductor chip, and the maximum portion of the step between the header portion and the semiconductor chip is smaller than the thickness of the semiconductor chip.
【００１２】絶対値的には、段差の最大部分が、０．２
ｍｍより小さいことがよい。また、チップ側面のエッチ
ング量とチップ厚との比率（エッチング量／チップ厚）
を０．２５以下とするものとする。絶対値的には、チッ
プ側面のエッチング量が６０μｍより少なくすることが
よい。In terms of absolute value, the maximum part of the step is 0.2
mm. Also, the ratio of the etching amount on the chip side surface to the chip thickness (etching amount / chip thickness)
Is set to 0.25 or less. In terms of absolute value, it is preferable that the etching amount on the side surface of the chip is smaller than 60 μm.
【００１３】そのようにすれば、パッシベーション層の
未塗布部やボイドを少なくし、あるいは密着性、均一性
を向上させることができる。また、半導体チップ表面の
絶縁性能をパッシベーション膜本来の能力に近づけるこ
とができる。In this case, the uncoated portion and voids of the passivation layer can be reduced, or the adhesion and uniformity can be improved. Further, the insulation performance of the semiconductor chip surface can be made closer to the intrinsic performance of the passivation film.
【００１４】[0014]
［実施例１］比抵抗１５〜４０Ωｃｍ、厚さ２４０μｍ
のｎ型シリコン基板に、一面からアクセプタ不純物であ
るほう素を拡散してｐ+ アノード層を、他面からドナー
不純物である燐を拡散してｎ+ カソード層を形成する。
この時、予め一面にアクセプタ不純物を含んだソースを
塗布し、他面にドナー不純物を含んだソースを塗布し、
その後熱拡散をおこなうことにより、ほぼ等しい厚さの
ｐ+ アノード層およびｎ+ カソード層が得られ、工程時
間が短縮できる。その後、ライフタイムキラーとして白
金を拡散したダイオードウェハを作製する。[Example 1] Specific resistance 15 to 40 Ωcm, thickness 240 µm
In the n-type silicon substrate, boron as an acceptor impurity is diffused from one surface to form a p + anode layer, and phosphorus as a donor impurity is diffused from the other surface to form an n + cathode layer.
At this time, a source containing an acceptor impurity is applied on one side in advance, and a source containing a donor impurity is applied on the other side,
Thereafter, by performing thermal diffusion, ap + anode layer and an n + cathode layer having substantially the same thickness can be obtained, and the process time can be reduced. Thereafter, a diode wafer in which platinum is diffused is manufactured as a lifetime killer.
【００１５】そのダイオードウェハにニッケルめっきを
し、熱処理後、鉛を主成分とするろう材により、複数枚
（例えば１２枚）のダイオードウェハを積み重ねて接合
し、更にその両端に融点の低い半田を接合した後、ワイ
ヤーソーにより０．５ｍｍ角に切断して正方形の底面を
もつ積層ダイオードの柱状体を作製する。切断時の歪み
を除去するために、柱状体の側面を化学薬品で約６５μ
ｍエッチングした後、柱状体の両端にヘッダー直径０．
７０ｍｍのリードを接合し、更に柱状体の側面にポリイ
ミド（粘度６０±２０ｃｐｓ）を塗布およびキュアをお
こない、エポキシ樹脂にて封止した。The diode wafer is nickel-plated, and after heat treatment, a plurality of (for example, 12) diode wafers are stacked and joined with a brazing material containing lead as a main component. After joining, a 0.5 mm square is cut with a wire saw to produce a columnar body of a laminated diode having a square bottom surface. To remove the distortion during cutting, the side of the columnar body was
After etching, a header diameter of 0. 0 at both ends of the columnar body.
A 70 mm lead was bonded, and polyimide (viscosity 60 ± 20 cps) was applied to the side surface of the columnar body, cured, and sealed with an epoxy resin.
【００１６】本実施例の高圧シリコンダイオードは、へ
ッダー部直径が０．９ｍｍである従来の高圧シリコンダ
イオードに比べて、逆サージ耐量が平均で約１５％増大
した。へッダー部直径が０．９ｍｍの従来の高圧シリコ
ンダイオードでは、ヘッダ部との段差は最大で０．２６
５ｍｍであったのに対し、この実施例の場合、０．５ｍ
ｍ角にダイシングしたダイオードチップを約６５μｍエ
ッチングしたので、約０．３７ｍｍ角となり、直径０．
７ｍｍのヘッダ部との段差は最大で０．１６５ｍｍであ
り、０．２ｍｍより小さく、もちろんダイオードチップ
の厚さより小さく、パッシベーション層の密着性が向上
することが考えられる。The high-voltage silicon diode of this embodiment has an average increase in reverse surge resistance of about 15% as compared with a conventional high-voltage silicon diode having a header diameter of 0.9 mm. In a conventional high-pressure silicon diode having a header part diameter of 0.9 mm, the step difference from the header part is a maximum of 0.26.
In contrast to 5 mm, in the case of this embodiment, 0.5 m
Since the diode chip diced into the m-square was etched by about 65 μm, it became about 0.37 mm-square and had a diameter of 0.3 mm.
The step difference from the header portion of 7 mm is 0.165 mm at the maximum, smaller than 0.2 mm, and of course, smaller than the thickness of the diode chip, and it is considered that the adhesion of the passivation layer is improved.
【００１７】［実施例２］柱状体の側面エッチング量を
約５５μｍとした以外は、実施例１と全く同様にして高
圧シリコンダイオードを作製した。本実施例の高圧シリ
コンダイオードは、従来の高圧シリコンダイオードに比
べて、逆サージ耐量が平均で約２０％増大した。実施例
１との差は、エッチング量を少なくした効果と考えられ
る。Example 2 A high-voltage silicon diode was manufactured in exactly the same manner as in Example 1 except that the amount of side etching of the column was set to about 55 μm. The high-voltage silicon diode of this embodiment has an average increase in reverse surge withstand capability of about 20% as compared with the conventional high-voltage silicon diode. The difference from Example 1 is considered to be the effect of reducing the etching amount.
【００１８】この実施例の場合、側面エッチング量の約
５５μｍは、ダイオードチップの厚さ２４０μｍに対す
る比が０．２３となり、０．２５より小さい。従来の高
圧シリコンダイオードでは、エッチング量が約６５μｍ
で、比は０．２７であった。以上積層した高圧シリコン
ダイオードの実施例のみを示したが、前項において述べ
たようにダイオードチップが１枚のメサ型ダイオード、
あるいはメサ型であれば、他の半導体装置においても、
パッシベーション層の密着性が向上することから、大き
な効果が期待できる。In this embodiment, the ratio of the side surface etching amount of about 55 μm to the diode chip thickness of 240 μm is 0.23, which is smaller than 0.25. Conventional high-pressure silicon diode has an etching amount of about 65 μm
And the ratio was 0.27. Although only the embodiment of the stacked high-voltage silicon diode has been described above, as described in the previous section, a mesa-type diode having one diode chip,
Or, if it is a mesa type, even in other semiconductor devices,
Since the adhesion of the passivation layer is improved, a great effect can be expected.
【００１９】[0019]
【発明の効果】以上説明したように本発明によれば、メ
サ型半導体チップの両主面にヘッダ付きのリードをろう
付けし、エッチングした側面をパッシベーション層で被
い、トランスファーモールドしてなるメサ型半導体装置
において、ヘッダー部と半導体チップとの間の段差の最
大部分を、半導体チップの厚さより小さく、例えば０．
２ｍｍ以下とし、またチップ側面のエッチング量を制限
することによって、パッシベーション層に未塗布部やボ
イドがなく、均一に必要な厚さ以上に塗られる結果、逆
電圧サージ耐量が大幅に向上したメサ型半導体装置を得
ることができる。As described above, according to the present invention, a mesa formed by brazing leads with headers to both main surfaces of a mesa-type semiconductor chip, covering the etched side surfaces with a passivation layer, and transfer molding. In the semiconductor device of the type, the maximum part of the step between the header portion and the semiconductor chip is smaller than the thickness of the semiconductor chip.
By limiting the etching amount on the side of the chip to 2 mm or less, the passivation layer is uniformly coated to the required thickness without any uncoated portions or voids. As a result, the reverse voltage surge withstand capability is greatly improved. A semiconductor device can be obtained.
【図１】（ａ）はメサ型ダイオードの一例の断面図、
（ｂ）、（ｃ）は角型、丸型ダイオードチップの平面図FIG. 1A is a cross-sectional view of an example of a mesa diode,
(B) and (c) are plan views of square and round diode chips.
【図２】（ａ）は高圧シリコンダイオードの一例の断面
図、（ｂ）、（ｃ）は角型、丸型ダイオードチップの平
面図FIG. 2A is a cross-sectional view of an example of a high-voltage silicon diode, and FIGS. 2B and 2C are plan views of square and round diode chips.
【符号の説明】 １ ダイオードチップ ２ ろう材 ２ａ ろう材 ３ パッシベーション層 ４ モールド樹脂 ５ リード ５ａ ヘッダー部[Explanation of Signs] 1 Diode chip 2 Brazing material 2a Brazing material 3 Passivation layer 4 Mold resin 5 Lead 5a Header
Claims (4)
主面にヘッダ付きのリードをろう付けし、エッチングし
た側面をパッシベーション膜で被い、トランスファーモ
ールドしてなるメサ型半導体装置において、リードのヘ
ッダー部が半導体チップの最大寸法より大きく、かつヘ
ッダー部と半導体チップとの間の段差の最大部分が、半
導体チップの厚さより小さいことを特徴とするメサ型半
導体装置。1. A mesa-type semiconductor device comprising a mesa-type semiconductor device having a pn-junction, a lead with a header attached to both main surfaces of the mesa-type semiconductor chip, an etched side surface covered with a passivation film, and transfer molding. A mesa-type semiconductor device, wherein a header portion is larger than a maximum size of the semiconductor chip, and a maximum portion of a step between the header portion and the semiconductor chip is smaller than a thickness of the semiconductor chip.
さいことを特徴とする請求項１記載のメサ型半導体装
置。2. The mesa-type semiconductor device according to claim 1, wherein a maximum portion of said step is smaller than 0.2 mm.
比率（エッチング量／チップ厚）を０．２５以下とする
ことを特徴とする請求項１または２に記載のメサ型半導
体装置。3. The mesa-type semiconductor device according to claim 1, wherein the ratio of the etching amount on the chip side surface to the chip thickness (etching amount / chip thickness) is 0.25 or less.
であることを特徴とする請求項３記載のメサ型半導体装
置。4. The mesa-type semiconductor device according to claim 3, wherein the etching amount on the side surface of the chip is 60 μm or less.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP29989997A JP3639420B2 (en) | 1997-10-31 | 1997-10-31 | Mesa type semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP29989997A JP3639420B2 (en) | 1997-10-31 | 1997-10-31 | Mesa type semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH11135696A true JPH11135696A (en) | 1999-05-21 |
| JP3639420B2 JP3639420B2 (en) | 2005-04-20 |
Family
ID=17878288
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP29989997A Expired - Fee Related JP3639420B2 (en) | 1997-10-31 | 1997-10-31 | Mesa type semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3639420B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108987517A (en) * | 2018-09-13 | 2018-12-11 | 常州市北达机械制造有限公司 | The trapezoidal copper-based structure of optically focused painting tin copper strips |
-
1997
- 1997-10-31 JP JP29989997A patent/JP3639420B2/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108987517A (en) * | 2018-09-13 | 2018-12-11 | 常州市北达机械制造有限公司 | The trapezoidal copper-based structure of optically focused painting tin copper strips |
| CN108987517B (en) * | 2018-09-13 | 2024-04-16 | 常州市北达机械制造有限公司 | Trapezoidal copper-based structure of concentrating tin-coated copper strip |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3639420B2 (en) | 2005-04-20 |
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