JPH11135500A - Formation of damascene wiring - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a formation method of a damascene wiring which permits fine wiring without greatly increasing the number of manufacturing processes of a semiconductor device. SOLUTION: A method has a process for forming a groove or a hole for forming a wiring in a first insulation film 12 formed on a substrate 11, a process for forming an aluminum film on the first insulation film 12, a process for leaving an aluminum film 13 inside a groove or a hole formed in the first insulation film 12 and removing the aluminum film 13 on the first insulation film 2, a process for forming a reflection prevention film 14 whose reflectance in a surface thereof is lower than the aluminum film 13, a process for forming a second insulation film 15 on the first insulation film 12, and a process for patterning the second insulation film 15 by using photoresist 17.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for forming a damascene wiring in a semiconductor device, and more particularly to a method for forming a damascene wiring for reducing the manufacturing cost of an LSI.

[0002]

2. Description of the Related Art LSI (Large Scale In)
In order to further increase the integration and speed of integrated circuits (LSC), the design rules of LSl have become finer,
The number of wiring layers is increasing. With the miniaturization of manufacturing, the depth of focus in lithography has become shallower, and this has necessitated that the height of steps due to wiring must be as low as possible. On the other hand, the multilayer structure of the wiring layers increases the level difference.

[0003] From such a background, after depositing an insulating film, it is planarized by chemical mechanical polishing (CMP), then a groove is formed in the insulating film, a metal film is deposited, and a metal film other than the groove is removed. The damascene method for forming wiring has attracted attention. According to this method, in principle, the number of wiring layers can be increased to infinity.

FIG. 2 shows a first example of a method for forming a damascene wiring in a conventional semiconductor device. This first conventional example is U
SP 5,262,354. This first
According to the conventional method of forming a damascene wiring described in FIG.
As shown in (a), the insulating film 2 is formed on the entire surface of the Si substrate 201.
After depositing 02, a wiring groove is formed here.

Subsequently, aluminum (Al) 210 is deposited by a physical vapor deposition method. At this time, Al in the groove
Is smaller than the depth of the groove.

Next, as shown in FIG. 2B, tungsten (W) 211 is deposited on the entire surface. The total film thickness of aluminum (Al) 210 and tungsten (W) 211 in the groove is larger than the depth of the groove. Subsequently, aluminum Al and tungsten W on the insulating film are removed by chemical mechanical polishing to form a trench wiring. Thus, an Al wiring having W as an upper layer is formed.

FIG. 3 shows a second example of a conventional method for forming a damascene wiring. This second conventional example is disclosed in Japanese Unexamined Patent Publication No.
No. 41 publication. In the method of the second conventional example, first, as shown in FIG. 3A, an insulating film 202 is deposited on a Si substrate 201 to form a groove.

Subsequently, as shown in FIG. 3B, aluminum (Al) 203 is deposited by a sputtering method. Here, the film thickness of aluminum (Al) in the groove is smaller than the depth of the groove. Next, aluminum (Al) on the insulating film is removed by chemical mechanical polishing. Then, FIG.
As shown in (c), an Al trench wiring is formed.

Further, as shown in FIG. 3D, tungsten (W) 204 is deposited thereon. After this, FIG.
As shown in (e), the wiring is formed by chemical mechanical polishing.

[0010]

The above-described conventional method for forming a damascene wiring has the following problems.

The first conventional method has a problem in that the number of steps increases and the process becomes complicated, resulting in a significant increase in manufacturing cost.

In the method according to the second conventional example described above, there is a portion where aluminum (Al) is exposed on the upper surface. Thereafter, an insulating film is deposited, and when the insulating film is patterned, the aluminum is removed. Irregular reflection of the exposure light of
A fine pattern cannot be formed. For this reason, there is a problem that the degree of integration of the semiconductor device does not increase, the number of chips obtained per wafer decreases, and the cost of the semiconductor device increases. In addition, the manufacturing process is complicated and the number of steps is large, so that there is a problem that the production cost increases.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned conventional problems and to enable fine wiring to be formed without greatly increasing the number of manufacturing steps of a semiconductor device, thereby reducing the manufacturing cost of an LSI. An object of the present invention is to provide a method for forming a damascene wiring that can be used for a long time.

[0014]

According to a first aspect of the present invention, there is provided a method for forming a damascene wiring, comprising the steps of: forming a groove for forming a wiring in a first insulating film formed on a substrate; Forming a hole, forming a first conductive film on the first insulating film, and forming the first conductive film in a groove or hole formed in the first insulating film. Leave
Removing the first conductive film on the first insulating film; and forming the first conductive film on the first conductive film in the groove or hole.
Forming a conductive film having a lower reflectance on the surface than the conductive film as an anti-reflection film, forming a second insulating film on the first insulating film, and using a photoresist. Patterning the second insulating film.

According to a second aspect of the present invention, in the method of forming a damascene wiring according to the present invention, the second chemical vapor deposition method is used.
The conductive film is formed.

According to a third aspect of the present invention, in the method of forming a damascene wiring according to the present invention, aluminum is used as the first conductive film, and tungsten is used as the antireflection film.

According to a fourth aspect of the present invention, in the method of forming a damascene wiring according to the present invention, aluminum is used as the first conductive film, and copper is used as the antireflection film.

According to a fifth aspect of the present invention, in the method of forming a damascene wiring according to the present invention, in the step of patterning the second insulating film, after applying a photoresist on the second insulating film,
Lithography is performed using exposure light having a wavelength of 365 nm or less.

[0019]

Next, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a sectional view of a semiconductor device in a main manufacturing step of a method for forming a damascene wiring.
This embodiment exemplifies a case where the method of forming a damascene wiring according to the present invention is applied to a wiring process in a silicon integrated circuit.

In general, damascene wiring is effective for flattening and fine patterning of a multi-layered wiring layer. However, if an insulating film is directly deposited on the exposed lower aluminum (Al) wiring and the insulating film is patterned, Diffuse reflection of exposure light from the lower Al wiring occurs. This is because the reflectance of Al is as high as 90% or more even in the vacuum ultraviolet wavelength region.

Therefore, if a film having a low reflectance is formed in a self-aligned manner on the Al wiring, the film serves as an antireflection film and does not affect the lithography of the insulating film.
The wavelength used in lithography is i-line (3
65nm) to XrF excimer laser (248n)
m), the wavelength is shortened to an ArF excimer laser (193 nm). In these wavelength ranges, tungsten (W)
And copper (Cu) have a reflectance of 65% or less and 45% or less, respectively, which is sufficiently lower than the reflectance of Al. Further, by selectively depositing these antireflection films on Al, a multilayer damascene wiring can be formed without a large increase in the number of steps.

FIG. 1A shows a substrate having a structure after aluminum wiring is formed by using a standard integrated circuit manufacturing method. In FIG. 1A, 11 is a silicon (Si) substrate, 12 is a first silicon oxide film (SiO2), and 13 is an aluminum (Al) wiring. In this embodiment, an Al film is deposited by a vapor phase physical growth method, and an aluminum (Al) wiring 13 is formed by chemical mechanical polishing.

Next, as shown in FIG. 1 (b), Al is formed by selective chemical vapor deposition using WF6 gas and hydrogen gas.
Tungsten film 1 as an antireflection film only on wiring 13
4 is deposited. Here, the selective vapor phase chemical growth is performed at a substrate temperature of 250 to 500 ° C. and a flow ratio of H 2 to WF 6 of 3 to
20, at a total pressure of 0.1 to 760 Torr.

Subsequently, as shown in FIG.
A second SiO2 film 15 is deposited in the state shown in FIG.

Further, as shown in FIG. 1D, when lithography is performed after the application of the photoresist 17, only the portion irradiated with the exposure light 16 is exposed, for example, due to irregular reflection of the exposure light from the Al wiring 13. It is possible to form a desired resist pattern without disturbing the resist pattern.

In the present embodiment, the case where tungsten is used as the antireflection film has been exemplified. However, the same effect can be obtained when copper (Cu) is used. Selective vapor phase chemical growth of Cu can be realized using, for example, hexafluoroacetylacetonate copper pinyltrimethylsilane (hfac) Cu (VTMS) at a substrate temperature of 100 to 400 ° C.

The selective deposition of Cu is not limited to the combination of the raw material and the temperature range, and can be appropriately selected from these.

It should be noted that the present invention is not limited to the above-described embodiment, and can be variously modified and implemented within the scope of the technical idea.

[0029]

As described above, according to the present invention, by forming an anti-reflection film having a low reflectance in a self-aligning manner on a wiring, disturbance of a resist pattern due to irregular reflection of exposure light from the wiring is prevented. Since this does not occur, fine wiring can be formed without a large increase in the number of steps, so that the chip area of the LSI can be reduced.
There is an effect that the manufacturing cost of the LSI can be reduced.

Further, when the antireflection film is formed by the selective chemical vapor deposition method, the number of manufacturing steps can be further reduced.

When aluminum is used as the first conductive film and tungsten or copper is used as the antireflection film, the reflectance of tungsten or copper is 65% or less and 45% or less at a wavelength of 365 nm or less, respectively. And
Since these are extremely lower than the reflectivity of aluminum (90% or more), irregular reflection can be suppressed, and fine wiring by lithography can be realized.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of a semiconductor device showing main manufacturing steps in an embodiment of a method for forming a damascene wiring of the present invention.

FIG. 2 is a cross-sectional view of a semiconductor device showing a manufacturing process in a first conventional method for forming a damascene wiring.

FIG. 3 is a cross-sectional view of a semiconductor device showing a manufacturing step in a second conventional damascene wiring forming method.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 11 Si substrate 12 1st SiO2 film 13 Al wiring 14 Tungsten film 15 2nd SiO2 film 16 Exposure light 17 Photoresist

Claims (5)

[Claims] A step of forming a groove or a hole for forming a wiring in a first insulating film formed on a substrate; and forming a first conductive film on the first insulating film. Removing the first conductive film on the first insulating film while leaving the first conductive film in a groove or hole formed in the first insulating film; Or a step of forming a conductive film having a lower reflectance on the surface than the first conductive film as an antireflection film on the first conductive film in the hole; Forming a second insulating film; and patterning the second insulating film. 2. The method according to claim 1, wherein the anti-reflection film is formed by a selective chemical vapor deposition method. 3. The method according to claim 1, wherein aluminum is used as the first conductive film, and tungsten is used as the antireflection film. 4. The method according to claim 1, wherein aluminum is used as the first conductive film and copper is used as the antireflection film. 5. The method according to claim 1, wherein in the patterning step of the second insulating film, after applying a photoresist on the second insulating film, lithography is performed using exposure light having a wavelength of 365 nm or less. 5. The method for forming a damascene wiring according to 2, 3, or 4.