JPH11134605A - Write data frequency detector - Google Patents

Abstract

PROBLEM TO BE SOLVED: To correctly detect the frequency of recording data without depending upon the generation state of a flyback pulse by converting the voltage level of recording data into a voltage and performing a frequency detection with the converted voltage. SOLUTION: The input reference voltage TP2 of a comparator 1 is a voltage being lower than a power source voltage Vcc by a prescribed voltage VTH and when a potential is lower than a test point potential TP2 , the compactor 1 outputs an H. Then, a potential TP1 due to a write data WDx having a cycle T0 and the test point potential PT2 are set so as to become equal when the data WDx changes from an L to an H. Now, when the cycle T0 changes by ΔT, since the falling time of the potential TP1 becomes longer by ΔT/2 and the potential TP1 becomes lower then TP2 and the comparator outputs the H in this time, it is detected that the cycle of the write data WDx becomes longer, that is, the frequency of the data is lowered.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a write data frequency detecting device for detecting a frequency of data recorded on a magnetic recording device such as a hard disk drive.

[0002]

2. Description of the Related Art A conventional technique according to the present invention will be described with reference to FIGS. FIG. 9 is a drive circuit diagram of the magnetic head, FIG. 10 is a time chart of write data for driving the magnetic head, and FIG. 11 is a time chart of the drive circuit. FIG. 12 is a circuit diagram for detecting a conventional write data frequency, and FIG. 13 is a time chart thereof. 14 and 15 are diagrams showing a frequency detection error of the circuit shown in FIG.

Conventionally, HDDs (Hard Disk D)
live) and other data recorded by the magnetic head (hereinafter, referred to as
For example, the circuit shown in FIG. 9 has been used for driving by “write data”. Configuration and transistor Q ₁₁ and the transistor Q ₁₂ is also the transistor Q ₁₃ and the transistor Q ₁₄ is, are respectively connected between the emitter and collector, the collector of the transistor Q ₁₁ and the transistor Q ₁₃ to the power supply V _CC, transistor Q ₁₂ the emitter of the transistor Q ₁₄ is grounded via the current source I _W and. The connection point of both ends of the coil of the magnetic head in this circuit configuration the transistor Q ₁₁ and the transistor Q ₁₂ (test points:
TP ₁₁ ), and transistors Q ₁₃ and Q ₁₄
(Test point: TP ₁₂ ). Note that L _H is the head inductance, and L
_R is the head resistance.

In the above-described circuit configuration, the transistors Q _{11 to} Q ₁₄ are switched based on the write data to change the direction of the current flowing through the head coil, thereby generating a recording magnetic field and recording the data on a magnetic recording medium. That is, the write data WD _X shown in FIG. 10A is input to the transistors Q ₁₁ and Q ₁₄ , while the inverted write data WD _Y shown in FIG. 10B is input to the transistors Q ₁₂ and Q _13. I have. Write data WD
If _X is "H" level, WD _Y is at the "L" level, is turned ON transistors Q _11, Q _14, transistors Q _12, Q ₁₃
Is turned off, a current i _W1 flows, while WD
If _X is "L" level, WD _Y is at the "H" level, the ON transistor Q _12, Q _13, the transistors Q _11, Q ₁₄
Is turned off, a current i _W2 flows, and an inverted magnetic field is generated to be used for magnetic recording. In addition, i _W1
And i _{W2 depend} on the current source I _W and have the same value.
Further, the voltage drop due to head resistance L _R of the magnetic head V
It is _{LR = i W1 L R = i} W2 L R.

When the magnetic head 5 is driven as described above,
Both ends of the head coil shown in FIG.
In addition to the voltage drop V _LR to P _11, TP _12, the flyback pulse is generated due to the inductance L _H As shown in FIG. 11 (c). Conventionally, frequency detection has been performed using this flyback pulse. Here, the frequency detection means "determining that an error occurs when write data longer than a certain period is input".

The reason why the frequency detection has been performed using the flyback pulse is that the write data is inputted, and after passing through some circuit blocks, the current switching signal of the magnetic head 5 is used. This is because checking the write data with the head 5 could also check the function of the write circuit system, and could also be used to detect a short circuit in the magnetic head 5.

Next, an example of a conventional write data frequency detecting device will be described. Figure 12 is an example of its circuit, the emitter of transistor P ₁ of the pnp type current source I
_It is connected to the power supply V _CC via ₃ and the collector is grounded. Have the capacity C ₂ for charging provided between the transistors P ₁ of emitter and GND, the emitter is connected to the (+) input terminal of the comparator 6 further. A voltage of V _CC -V _TH lower than the power supply V _CC by a predetermined voltage V _TH is input to a (−) input terminal of the comparator 6 as a reference voltage for comparison. The base of the transistor P ₁ is being connected to TP ₁₂ of the magnetic head driving circuit shown in FIG. 9, it has a reference signal of the frequency detection. Incidentally, it is needless to say TP ₁₁ on behalf of the TP ₁₂ are similar operation described below is also connected.

Now, the write data W shown in FIG.
When D _X driving circuit of the magnetic head 5 shown in FIG. 9 by inverted WD _Y it is to have been operated, the voltage V (TP ₁₂₎ test points TP _12, as shown in FIG. 13 (b) Flyback The waveform has a period T having a pulse. The transistor P ₁ is accumulated charge in the capacitor C ₂ by the current from the current source I ₃ during OFF, the transistor P ₁ is turned on by the negative flyback pulse is applied to the base of transistor P ₁ State, the charge is released, and then charging is started again. Its charge voltage becomes linearly rising time with the charge supply from the current source I _3, as shown in V (TP ₁₃₎ of FIG. 13 (b), which is input to the (+) input terminal of the comparator 6 . On the other hand, the comparator 6 (-) to the input terminal is input voltage _{V (TP 14) = V CC} -V TH shown in FIG. 13 (b), V and (TP ₁₃₎ and V (TP ₁₄₎ Are compared. As a result, as shown in FIG.
“H” is output in the region of P ₁₃ )> V (TP ₁₄ ) [V
(TP ₁₅ )].

Usually, the "H" output is set to a critical state, and the charging time becomes longer, so that V (TP ₁₃ )> V (TP
_In the state of ₁₄ ), "H" is output, and it is recognized that the cycle T of the write data has become longer, that is, the frequency has dropped. However, the generation state of the flyback pulse differs depending on the L _H of the magnetic head, the current source I _W , the inductance of the wiring, and the like, and the state of discharging the charge stored in the capacitor C ₂ changes, and an accurate detection result cannot be obtained. There was something.

[0010] As shown in FIG. 14, for example, as a first example not accurate detection results can be obtained, if the peak V _P of the flyback pulse is increased, the charging is started from the peak voltage, constant Charging voltage V (TP
₁₃₎ does not reach the reference voltage V (TP _14), thus also the period T becomes longer without outputs "H", it will be determined to be the correct write data frequency.

As a second example, as shown in FIG. 15, when the width W of the flyback pulse is increased,
Since the charging is started from the peak voltage, the charging start is delayed, so that the charging voltage V (TP ₁₃ ) that is charged constantly does not reach the reference voltage V (TP ₁₄ ). Since "H" is not output, it is determined that the write data frequency is correct.

Further, in addition to the above-described problem, a plurality of HDs
D, that is, when a plurality of magnetic heads are driven by the same write data, it is necessary to provide a detection circuit for all magnetic heads, and there is a disadvantage that the circuit scale becomes large.

[0013]

Accordingly, the present invention relates to an HD
It is an object of the present invention to provide a write data frequency detection circuit that accurately detects the frequency of data recorded in a magnetic recording device such as D without depending on the state of generation of a flyback pulse.

[0014]

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and according to the present invention, there is provided a write data frequency detecting apparatus for detecting a frequency of data recorded on a magnetic recording apparatus. , A conversion means for converting the voltage level of the data to be recorded is provided, and a write data frequency detection device configured to perform frequency detection based on the voltage level converted by the conversion means.

According to the second and third aspects of the present invention, the level converting means for converting the voltage level of the data to be recorded, and the voltage level "L" (or "H") of the data to be recorded , A charge accumulating means for accumulating charges at a constant rate, a discharging means for discharging the charges stored at the voltage level "H" (or "L") of the data to be recorded, and a reference voltage generating means for generating a reference voltage And a comparing means for comparing the potential gradually decreased (or gradually increased) by the charge accumulation by the charge accumulating means with the reference voltage, and detects a frequency of data to be recorded from a comparison result of the comparing means. A write data frequency detection device according to claim 1 is configured.

Further, according to the invention described in claim 4,
The above object is achieved by configuring a write data frequency detecting device according to claim 1, wherein a converting means for converting a voltage level of data to be recorded is provided inside an IC circuit forming a driving circuit of the magnetic recording device.

Therefore, according to the write data frequency detecting device having the above-described configuration, the frequency of data to be recorded in a magnetic recording device such as an HDD is detected based on the write data, so that an accurate write data frequency can be detected. .

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention relates to an apparatus for detecting when the frequency of write data has decreased, and in which the data period has been increased directly from the write data, that is, the frequency has decreased. And a device for detecting that

An embodiment of the present invention will be described with reference to FIGS. FIG. 1 shows an embodiment of a write data frequency detecting device according to the present invention, and FIGS. 2 and 3 are time charts for explaining frequency detection of the circuit.
FIG. 4 is a configuration example of an output stage of the circuit shown in FIG.
FIG. 5 is a time chart thereof. FIG. 6 shows another example of the configuration of the output stage of the circuit shown in FIG.
Is the time chart.

As shown in FIG. 1, in the circuit configuration embodying the present invention, the transistor Q ₁ and the transistor Q ₂ have a common emitter and are grounded via a current source I ₁ . The collector of the transistor Q ₁ is connected directly to the power supply V _CC, also to the power source V _CC collector of the transistor Q ₂ is through a resistor R _1. The write data WD _X shown in FIG. 2A is input to the base of the transistor Q ₁ , while the WD _{Y obtained} by inverting the WD _X shown in FIG. 2B is input to the base of the transistor Q ₂ . . The collector of the transistor Q ₂ is connected to the base of the transistor Q _3, the transistor collector of Q ₃ are directly supply V _CC, The emitter is grounded through a current source I _2. Transistor Q
₃ of capacitance C ₁ of the charge storage between the emitter and the power supply V _CC have is provided, the emitter is connected to the (+) input terminal the comparator 1 further. Further, a voltage of V _CC -V _TH lower than the power supply V _CC by a predetermined voltage V _TH is input to a (−) input terminal of the comparator 6 as a reference voltage for comparison.

In the above-described circuit configuration example, claim 2
The transistors Q ₁ and Q ₂ , the resistor R _1, and the current source I ₁ correspond to the level conversion means for converting the data level described in ( _1), and charge is stored at a constant rate at the “L” level of the data to be recorded. The charge storage means comprises a capacitor C ₁ and a current source I ₂
There applicable and release means for releasing the charge accumulated in the "H" level of the data to be recorded, the transistor Q ₃ is applicable, the reference voltage generating means for generating a reference voltage is a voltage source V
_TH corresponds, and the comparator 1 corresponds to the comparing means.

The operation of the above-described circuit will be described with reference to FIGS. The write data WD _X of the cycle T ₀ is “H”
In, if the WD _Y is "L", the transistor Q ₁ is ON,
Transistor Q ₂ is turned OFF, test point TP ₁ subjected to any substantially voltage V _CC to the base of the transistor Q ₃
Potential V (TP ₁₎ becomes V _CC -V _F. Then WD
_X is "L", WD _{when Y} becomes "H", the transistor Q ₁ is OFF, next transistor Q ₂ is ON, the base of the transistor Q ₃ the voltage V _CC -i ₁ R ₁ applied, the potential V (TP ₁ ) is from V _CC -V _F to V _CC -V _F -i ₁
Linearly drops based on the magnitude of the current i ₂ of the current source I ₂ to R _1.

The reference voltage V (T
P ₂ ) is V _CC -V _TH and V (TP ₁ ) <V (TP
₂ ), the comparator 1 outputs “H” [V (T
P _3): FIG. 2 (d)]. Note that V _CC −V _F −i ₁ R ₁ is V
Each value so that a value smaller than _CC -V _TH is determined. Further, tau is the time delay which occurs until from the input of the write data to the test point TP _1.

Now, in the above-described circuit, the voltage V (TP) based on the write data WD _X of the cycle T ₀ [FIG.
The relationship between ₁ ) and the voltage V (TP ₂ ) is as shown in FIG.
That is, when WD _X changes from “L” to “H”, V
(TP ₁ ) = V (TP ₂ ) [point a in FIG. 3B].

From the state where this frequency is correct, the period is T ₀ +
When becomes [Delta] T, the fall time of the voltage V (TP ₁₎ it is extended by [Delta] T / 2, the time, the voltage V (TP ₁₎ becomes lower than the voltage V (TP _2). Therefore, FIG.
"H" is output from the comparator 1 from the point b to the point c in (b) [FIG. 3 (c)], and it is detected that the period of the write data has become long, that is, the frequency has dropped. .

FIG. 4 shows a D flip-flop (D-FF).
2 is an output stage following comparator 1 using 2. FIG.
(A), the have been output pulses detected from the comparator 1, and this by the sample with the write data WD _X has progressed in phase from pulses detected from the above-mentioned reasons. Based on the operation of the D-FF2, the result is output from the Q terminal of the D-FF2 as shown in FIG. By providing such an output stage, a decrease in the write data frequency can be reliably recognized.

FIG. 6 shows another example of the configuration of the output stage.
The "V _X (TP _3)" in FIG. And is the output of the comparator 1 relative to the WD _X as shown in FIG. 1, "V _Y (T
P ₃₎ "and is the output of the comparator 1 relative to the WD _Y which replaced the WD _X and WD _Y shown in FIG. Thus in order to configure the output stage of FIG. 6, it requires a detection circuit relative to the detection circuit and WD _Y relative to the WD _X.

As shown in FIG. 7, when the write data is input at the normal frequency and the WD _X remains "H" and therefore the WD _Y remains "L", FIG. As shown in ( ₅ ), an output “H” is obtained at V _Y (TP ₃ ). Therefore, the OR gate 4 input to the reset terminal of the D-FF 2
Output "H", and "H" is output from the Q terminal to detect an abnormality.

[0029] In addition, while after that had been entered in the write data is of normal frequency, as shown in Figure 8, WD _X is "L",
Therefore, when WD _Y remains at “H”, FIG.
As shown in FIG. 7, an output “H” is obtained at V _X (TP ₃ ). Therefore, the OR input to the reset terminal of D-FF2
“H” is output from the gate 4 and “H” is output from the Q terminal, and an abnormality is detected.

Therefore, when the output stage having the configuration shown in FIG. 6 is used, after write data is input at a normal frequency,
While D _X is "H", thus leaving WD _Y is "L", or leave WD _X is "L", therefore even if the WD _Y becomes remains "H", the abnormality of the write data It becomes possible to detect.

It should be noted that the present invention is not limited to the above-described embodiment, but may employ another circuit configuration that embodies the technical idea of the present invention.

[0032]

As is apparent from the above description, according to the write data frequency detecting device of the present invention, the frequency can be directly detected from the write data, so that the detection can be performed with high accuracy.

After the frequency at which the write data is normal,
Even if it is lost, that is, even if it remains "H" or "L", an abnormal state can be detected.

Further, even if the number of magnetic heads increases due to the parallel recording, one detecting device can cope with the increase.

[Brief description of the drawings]

FIG. 1 is an embodiment of a write data frequency detection device according to the present invention.

FIG. 2 is a time chart of the circuit shown in FIG. 1;

FIG. 3 is a time chart illustrating frequency detection of the circuit shown in FIG. 1;

FIG. 4 is a configuration example of an output stage of the circuit shown in FIG. 1;

FIG. 5 is a time chart of the circuit shown in FIG. 4;

FIG. 6 is another configuration example of the output stage of the circuit shown in FIG. 1;

FIG. 7 is a time chart of the circuit shown in FIG. 6;

FIG. 8 is a time chart of the circuit shown in FIG. 6;

FIG. 9 is a drive circuit diagram of the magnetic head.

FIG. 10 is a time chart of write data for driving a magnetic head.

11 is a time chart of the drive circuit shown in FIG.

FIG. 12 is a circuit diagram for detecting a conventional write data frequency.

13 is a time chart of the circuit shown in FIG.

14 is a diagram showing a frequency detection error by the circuit shown in FIG.

FIG. 15 is a diagram showing a frequency detection error by the circuit shown in FIG. 12;

[Explanation of symbols]

1, 6 comparator, 2 D-FF, 4 OR gate, 5 ...
Magnetic head

Claims (4)

[Claims] 1. A write data frequency detecting device for detecting a frequency of data to be recorded on a magnetic recording device, comprising a converting means for converting a voltage level of the data to be recorded, based on the voltage level converted by the converting means. A write data frequency detecting device for performing frequency detection. 2. A level converting means for converting a voltage level of data to be recorded, a charge accumulating means for accumulating charges at a constant rate at a voltage level "L" of the data to be recorded, and a voltage level of the data to be recorded. Emission means for emitting the charge accumulated at "H"; reference voltage generation means for generating a reference voltage; and comparison means for comparing the reference voltage with a potential gradually reduced by charge accumulation by the charge accumulation means. 2. The write data frequency detecting device according to claim 1, wherein a frequency of data to be recorded is detected from a comparison result of said comparing means. 3. A level converting means for converting a voltage level of data to be recorded, a charge accumulating means for accumulating charges at a constant rate at a voltage level "H" of the data to be recorded, and a voltage level of the data to be recorded. Emission means for emitting the charge accumulated at "L"; reference voltage generation means for generating a reference voltage; and comparison means for comparing the reference voltage with a potential gradually increased by charge accumulation by the charge accumulation means. 2. The write data frequency detecting device according to claim 1, wherein a frequency of data to be recorded is detected from a comparison result of said comparing means. 4. The write data frequency detecting device according to claim 1, wherein a converting means for converting a voltage level of data to be recorded is provided inside an IC circuit constituting a drive circuit of the magnetic recording device. .