JPH10124890A - Tracking error signal detector - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a tracking error signal detector capable of minimizing disorder generated due to the scratch on the surface of a disk. SOLUTION: A false signal is canceled by an amount corresponding to the low band component of a phase difference when the phase difference generated between the diagonal sum signals of a detector is <=T2 time; by limiting the time to T2 and by an amount corresponding to the low band component of a phase difference when the phase difference is >=T2 and <=T3 by means of a phase difference storage means 8, a pulse width detecting means 9 and an erasing pulse generating means 10; and when the phase difference is >=T3, by canceling the false signal by means of a first and a second logical means 7, 11 and the erasing pulse generating means 10, and a tracking error signal as a final output is hardly affected by the false signal.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a tracking error signal detecting device in an apparatus for reproducing information by irradiating a focused light beam onto an optical information recording medium such as an optical disk.

[0002]

2. Description of the Related Art In recent years, there has been a demand for a new technical invention for a tracking error signal detecting device as the density of an information recording optical disk increases.

A conventional tracking error signal detecting device will be described below. FIG. 8 is a block diagram of a conventional tracking error signal detection device. In FIG. 8, reference numeral 1 denotes a quadrant light receiving element having four light receiving surfaces 1a, 1b, 1c, and 1d, and reference numerals 2 and 3 denote diagonal pairs (1a and 1c) and (1b and 1d) outputs of the quadrant light receiving element. Adders 4 and 5 for converting the outputs of the adders 2 and 3 into binary signals A and B, respectively, and 6 for detecting the phase difference between the binary signals A and B When the pulse widths of the phase difference pulses P1 and D1 exceed a predetermined value T1, the phase comparison means 13 and 14 output the phase difference pulses P1 and D1 to limit the pulse width to T1 and output the pulse widths as P2 and D2. The pulse width limiting means 12 performs pulse width limiting means 13,
This is a low-pass filter that obtains a tracking error signal TE from fourteen outputs P2 and D2.

The operation of the tracking error signal detecting device configured as described above will be described below with reference to FIG.

FIGS. 9 to 11 show the above A, B, P1, D
FIG. 4 is a timing chart schematically showing each signal of 1, P2, D2, and TE in three representative states.

The sum signal of 1a and 1c and 1b
And the above 1d sum signal has a phase difference having a polarity and magnitude depending on the direction and amount of displacement of the light beam with respect to the information recording track. The phase difference is taken out as a signal to remove high frequency components. , A tracking error signal is obtained.

First, the state, FIG. 9 shows a case where there is a small displacement in a certain direction, FIG. 10 shows a case where there is a relatively large displacement in a direction opposite to FIG. 9, and FIG. This causes the reproduced signal to be disturbed, resulting in a phase difference larger than usual.

[0008] The set value T1 of the pulse width limiting means 13 and 14 in FIG. 8 is selected to be a value slightly larger than the phase difference generated by the displacement between the light beam and the track. Therefore, in the case of the state diagrams 9 and 10, the pulse width limiting means has no function. However, as shown in the state diagram 11, when a phase difference larger than usual occurs due to a scratch on the optical disk or the like, the pulse width limiting means limits the output pulse width to T1, and
Significant disturbance of the tracking error signal is reduced.

[0009]

However, in the above configuration, the effect is insufficient, the tracking error signal is largely disturbed, and the tracking control is unstable, depending on the degree of scratches or dirt on the optical disk surface or the reflection surface. In addition, the error in the count of the number of tracks becomes large at the time of a search for moving to an arbitrary track at a high speed, and the search accuracy deteriorates.

An object of the present invention is to solve such a problem in a conventional tracking error signal detecting device and to provide a device capable of detecting a tracking error signal more stably.

[0011]

In order to solve the above-mentioned problems, a tracking error signal detecting device according to the present invention is connected to an output of a phase comparing means, and comprises a phase difference storing means and a pulse width detecting means. When the detected phase difference T1 exceeds a predetermined constant T2 and is equal to or less than a constant T3 larger than T2 by the phase comparing means, the pulse width is limited to T2, and the detected phase difference reduces the time T3. When it exceeds, the erasing pulse generating means generates an erasing pulse with a polarity for canceling the once output pulse.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The invention according to claim 1 of the present invention is directed to a means for irradiating a laser beam near an information track of an optical information recording medium, and a divided light receiving means provided in the optical path of the reflected beam. And a tracking error signal detection device that detects a mutual phase difference between output signals of the first light receiving element group and the second light receiving element group that constitute the divided light receiving means and forms a tracking error signal, Phase comparing means for the outputs of the first and second light receiving element groups, erasing pulse generating means for generating an erasing pulse from the output of the phase comparing means, the output of the storage means and the output of the pulse width detecting means,
First logic means for generating a logical output of the output of the phase comparing means and the output of the erasing pulse generating means, and a logical output of the output of the phase comparing means, the output of the erasing pulse generating means and the output of the storage means And a filter for obtaining a tracking error signal from the output of the second logic means, and the storage means and the pulse width detection means are controlled by the output of the first logic means. According to this configuration, most of the phase difference components generated due to scratches and dirt on the disk surface and the reflection surface are large phase difference components exceeding T3. If the phase difference exceeds T3, an erasing pulse is generated to almost cancel the already generated pulse. An effect that it is possible to minimize the disturbance of the tracking error signal in.

The invention according to claim 2 of the present invention is characterized in that the filter is a low-pass filter, and has an effect of shaping into a waveform suitable for tracking control.

(Embodiment 1) Hereinafter, a tracking error signal detecting apparatus according to Embodiment 1 of the present invention will be described with reference to FIG. 1 which is a block diagram and FIG. In FIG. 1, the same components as those in FIG. 8 described in the related art are denoted by the same reference numerals, and detailed description thereof will be omitted.

In FIG. 1, two diagonal sum outputs of the quadrant light receiving element of the optical head are converted into high level or low level binarized signals A and B by binarizing means 4 and 5, respectively. The signal is input to two input terminals 61 and 62 of the means 6. The phase comparing means 6 outputs P1 and D1 pulses to the advance output terminal 63 or the delay output terminal 64, respectively, according to the phase difference between the input terminals 61 and 62.

The output terminals 63 and 64 of the phase comparison means are input terminals 71 and 72 of the first logic means 7 and input terminals 101 and 102 of the erase pulse generation means 10, respectively.
Are connected to the input terminals 111 and 112 of the logic means 11. The first logic means additionally has input terminals 73 and 74. When the signal levels of the input terminals 73 and 74 are both low and the input terminal 71 or 72 is high,
The signal CRG at the output terminal 75 goes low when the signal CRG at the output terminal 75 goes high and the signal level at one of the input terminals 73 and 74 goes high. The output terminal 75 is an input terminal 81 of the phase difference storage means 8 and an input terminal 91 of the pulse width detection means 9.
Connected to.

In the phase difference storage means 8, when the signal level of the input terminal 81 becomes high, the internal capacitor is charged with a constant current, and the terminal voltage VC of the capacitor rises with time over time. Capacitor voltage VC
Reaches the VH detection level, the terminal voltage VC of the capacitor
Is held at the VH detection level, and the signal VH of the output terminal 83 is changed from the low level to the high level. When the signal level of the input terminal 81 changes from the high level to the low level, the internal capacitor is discharged with the same current value as the charging, so that the output terminal 83 changes from the high level to the low level and the terminal voltage VC of the capacitor becomes negative. Decreases over time. The terminal voltage VC of the capacitor is V
When the L detection level is reached, the terminal voltage VC of the capacitor is changed to V
L level and the signal V at the output terminal 82.
L is changed from a high level to a low level. Here, when the signal level of the input terminal 81 is changed from the low level to the high level, the time required for the terminal voltage VC of the capacitor to change from the VL detection level to the VH detection level is set to T2. Therefore, the input terminal 81
Is changed from high level to low level,
The time required for the terminal voltage of the capacitor to change from the VH detection level to the VL detection level is also T2. The detection results of VL and VH output from the output terminals 82 and 83 are input to the input terminal 103 of the erase pulse generating means 10 and the input terminal 115 of the second logic means 11, respectively. On the other hand, the pulse width detecting means 9 determines the time T3 set internally after the input terminal 91 changes from the low level to the high level.
When the time has elapsed, the signal PL at the output terminal 92 is changed from low level to high level, and immediately after the input terminal 91 returns to low level, the signal PL at the output terminal 92 is changed from high level to low level. Here, T3 is usually set to a value larger than T2. The signal PL at the output terminal 92 is input to the input terminal 104 of the erase pulse generating means 10. When the signal VL of the input terminal 103 is at the high level and the signal P1 of the input terminal 101 is at the high level, the signal EP of the input terminal 104 becomes high level even for a moment. From the low level to the high level, and when the signal VL at the input terminal 103 is at the high level and the signal D1 at the input terminal 102 is at the high level, the signal P at the input terminal 104 is high.
When L becomes high level even for a moment, the signal ED at the output terminal 106 is changed from low level to high level. The signals EP and ED of the output terminal 105 or 106 are respectively
When the signal VL at the input terminal 103 becomes low level even for an instant, it is reset to low level. Output terminals 105 and 10
6 is connected to the input terminals 113 and 114 of the second logic means 11 or the input terminals 74 and 73 of the first logic means 7 described above. The second logic means 11 determines that the signal VH of the input terminal 115 is at a low level and the signal EH of the input terminal 114 is low.
When both D and the signal EP of the input terminal 113 are at the low level, the signal P3 of the output terminal 116
Similarly, when the signal VH of the input terminal 115 is at a low level and the signal ED of the input terminal 114 and the signal EP of the input terminal 113 are both at a low level, the output terminal The signal D3 at 117 becomes a signal having the same level as the signal D1 at the input terminal 112. When the signal VH of the input terminal 115 is at a high level,
When the signal ED at the input terminal 114 is low, the signal P3 at the output terminal 116 is low. Similarly, when the signal VH at the input terminal 115 is high and the signal EP at the input terminal 113 is low, the output is low. Signal D at terminal 117
3 goes low. The signal E of the input terminal 114
When D is at the high level, the signal P3 at the output terminal 116 is at the high level, and similarly, the signal EP at the input terminal 113 is
Is high level, the signal D3 of the output terminal 117 becomes high level.

The signal P3 at the output terminal 116 of the second logic means 11 and the signal D3 at the output terminal 117 are connected to the input terminals 121 and 122 of the low-pass filter 12, respectively.
In the low-pass filter 12, the signal P3 of the input terminal 121
When a pulse is generated at the output terminal 123, the signal TE at the output terminal 123 is changed to a positive voltage by an amount corresponding to the low frequency component. When a pulse is generated at the signal D3 at the input terminal 122, Output terminal 12 by an amount corresponding to the
3 is changed to a negative voltage.

With the configuration described above, as can be seen from FIG. 2, when the phase difference between the binary signals A and B is equal to or less than T2, the signal corresponding to the low-frequency component of the phase difference, that is, the average value, is generated. If the phase difference between A and B exceeds T2 and is equal to or less than T3, TE corresponding to the low-frequency component of the signal whose time is limited to T2 is output.
When the phase difference of B occurs for a time exceeding T3, the pulse is limited to T2 and the once output pulse is output to the opposite polarity for the same T2 time so that the TE output as a low-frequency component hardly changes. be able to.

Next, an embodiment of each block configuration will be described. FIG. 3 is a block diagram showing an embodiment of the phase difference storage means 8.

While the input terminal 81 is at the high level, the switch 8a connects the current source 8b having a current value of 2I1 to the capacitor 8c. On the other hand, since a current source 8d having a current value of I1 is always connected to the capacitor 8c, when a phase difference occurs, the terminal voltage VC of the capacitor 8c is charged at a constant rate toward a positive voltage, and the phase difference Is completed, the battery is discharged at the same fixed rate as the charge.
Further, the terminal voltage VC of the capacitor 8c is a diode 8e.
The operating range is limited by a positive voltage limiter composed of a voltage source 8f and a negative voltage limiter composed of a diode 8g and a voltage source 8h. Whether the positive voltage limiter has been activated is set by a low resistance 8i and a judgment level, respectively. The voltage is detected by a VH detection circuit composed of a voltage source 8j and a comparator 8k, and output to an output terminal 83. Similarly, whether the negative voltage limiter has been activated is determined by the low resistance 8l, the voltage source 8
m and a VL detection circuit composed of a comparator 8n and output to an output terminal 82.

Therefore, the voltage of the capacitor 8c is V
As shown in C, while the signal CRG at the input terminal 81 is at the high level, the signal rises positively with time at a constant rate, and when the signal CRG becomes low level, the voltage of the capacitor 8c decreases at the same rate toward negative. I do. When the terminal voltage VC of the capacitor is rising, the diode 8e and the voltage source 8
When the voltage exceeds the VH detection level set by f, a current flows through the low resistance 8i, a potential difference is generated between both ends, and the voltage exceeds the voltage set by the voltage source 8j, so that the VH detection output terminal 83 which is the output of the comparator 8k. Changes from a low level to a high level at that moment, as shown by VH in FIG. Similarly,
While the voltage of the capacitor 8c is falling, if it tries to become lower than the VL detection level set by the diode 8g and the voltage source 8h, a current flows through the low resistance 8l, and as a result, the comparator 8n
The VL detection force terminal 82, which is the output of, changes from a high level to a low level as shown by VL in FIG.

FIG. 4 is a block diagram showing an embodiment of the erasing pulse generating means 10, in which two D flip-flops 10 are provided.
a and 10b and an inverter 10c. Therefore, as shown in FIG. 2, when the signal VL of the input terminal 103 is at a high level and the signal P1 of the input terminal 101 is at a high level, and the signal PL of the input terminal 104 is at a high level for a moment, the output terminal 105 The signal EP is changed from a low level to a high level.
3 is at a high level and the signal D of the input terminal 102 is high.
When 1 is at the high level, the signal ED at the output terminal 106 is changed from the low level to the high level when the signal PL at the input terminal 104 goes to the high level even for a moment. EP and ED signals at output terminal 105 or 106 respectively
Is reset to the low level when the signal VL of the input terminal 103 is instantaneously changed to the low level.

FIG. 5 is a block diagram showing an embodiment of the second logic means 11, which comprises two AND gates 11a and 11b, two OR gates 11c and 11d, and three inverters 11e, 11f and 11g. It is configured. As shown in FIG. 2, when the signal VH of the input terminal 115 is at a low level,
When both the signal ED of the input terminal 114 and the signal EP of the input terminal 113 are at a low level, the signal P3 of the output terminal 116 becomes a signal having the same level as the signal P1 of the input terminal 111. When the signal VH at 115 is low and the signal ED at the input terminal 114 and the signal EP at the input terminal 113 are both at low level, the signal D3 at the output terminal 117 has the same level as the signal D1 at the input terminal 112. become. When the signal VH at the input terminal 115 is at a high level and the signal ED at the input terminal 114 is at a low level, the signal P3 at the output terminal 116 is at a low level. Similarly, when the signal VH at the input terminal 115 is at a high level. When the signal EP of the input terminal 113 is at a low level, the signal D3 of the output terminal 117 is at a low level. When the signal ED of the input terminal 114 is at a high level,
The signal P3 at the output terminal 116 goes high, and similarly, when the signal EP at the input terminal 113 goes high,
The signal D3 of the output terminal 117 becomes high level.

FIG. 6 is a block diagram showing an embodiment of the first logic means 7, in which two OR gates 7a, 7b and AN
It comprises a D gate 7c and an inverter 7d. As shown in FIG. 2, when the signal ED at the input terminal 73 and the signal EP at the input terminal 74 are both at a low level and the signal P1 at the input terminal 71 or the signal D1 at the input terminal 72 is at a high level, the signal at the output terminal 75 is output. When CRG goes high, and either the signal ED at the input terminal 73 or the signal EP at the input terminal 74 goes high, the output terminal 7
5 is configured to be low level.

FIG. 7 is a block diagram showing an embodiment of the low-pass filter 12, which includes two resistors 12a and 12b having a resistance value of R1 and two resistors 1a and 12b having a resistance value of R2.
2c, 12d and two capacitors 1 having a capacitance of C
2e and 12f and an operational amplifier 12g.
As shown in FIG. 2, when a positive-polarity pulse is generated in the signal P3 at the input terminal 121, the signal TE at the output terminal 123 changes to a positive voltage by an amount corresponding to the low-frequency component. When a positive pulse is generated at D3, the signal TE at the output terminal 123 changes to a negative voltage by an amount corresponding to the low frequency component.

According to the configuration described above, when the phase difference between the sum signals of the diagonals of the detector is equal to or less than the time T2, which frequently occurs in the normal operation, TE equals to the amount corresponding to the low-frequency component of the phase difference. In the case where the generated phase difference exceeds T2 and is equal to or less than T3, which is also likely to occur at the time of an abnormality such as a scratch, the time is limited to T2 and the phase difference is reduced. TE by the amount corresponding to the low frequency component
, And the first restriction is applied.
In the case of a phase difference exceeding T3, which hardly occurs in normal operation, and occurs mostly in an abnormal state, the pulse output once limited to the time of T2 is the same as T2 at the time of exceeding T3. It is canceled by outputting a pulse of the opposite polarity, and by applying the second restriction that the TE that is the final output is hardly affected, the original signal is hardly lost and the signal is generated due to scratches or the like. Disturbance of the generated TE signal can be minimized.

In the above description, the phase difference storage means is described as a hold circuit using charge / discharge, the erase pulse generation means as a logic circuit using a D flip-flop, and the first and second logic circuits using a gate circuit. However, the present invention is not limited to this. In other words, the phase comparing unit, the first measuring unit that measures the time of the output pulse of the phase comparing unit and has a limiting constant T2, and the second measuring unit that has a limiting constant T3 , Pulse width limiting means and erasing pulse generating means, the output width of the phase comparing means is T1, the output of the phase comparing means is used when T1 ≦ T2, and the pulse width limiting means is used when T3>T1> T2. The output of the pulse width limiting means is output when T3.ltoreq.T1, and then the tracking error signal of the present invention is used if it is composed of waveform synthesizing means for generating the output of the erasing pulse generating means. In the range of the detection device, it is not limited to the circuit configuration of the above description.

Also, it has been described that the erase pulse is also canceled after the output of the pulse width limiting means. However, the present invention is not limited to this.
The frequency of the basic output pulse constituting the tracking error such as P1 and D1 is very high, around 10 MHz, and the required band of the tracking error signal is 100 KHz or less, which is sufficiently higher than P1 and D1.
If a memory or a shift register operating at a frequency of 0 MHz or more is used and a similar circuit is realized by a signal passed through the memory for one cycle, for example, an erase pulse is generated simultaneously with the output of the pulse width limiting means, or a gate circuit or the like is used. The same effect can be obtained by substantially eliminating the output of the pulse width limiting means by using the above method or by using a configuration other than canceling out in time series.

Further, the operation corresponding to the above circuit configuration is described as follows.
Obviously, it can be realized by software such as a high-speed microcomputer, which is within the scope of the present invention.

[0031]

According to the present invention, when the phase difference of the phase comparison means is less than the period frequently occurring in normal operation, the phase difference is output as a tracking error signal by an amount corresponding to the low-frequency component of the phase difference, If the phase difference that occurs occurs during normal operation and is less than or equal to the time of a specific period that is likely to occur even when an abnormality such as a scratch occurs, the pulse width is limited and the amount corresponding to the low-frequency component of the phase difference is limited. In the case of a phase difference that is hardly generated in normal operation, and that is longer than or equal to a specific period, such that a phase error hardly occurs in a normal operation and is mostly generated in an abnormal state, By applying the second restriction so as not to output the tracking error signal, disturbance of the tracking error signal caused by scratches can be minimized and effectively suppressed without substantially losing the original signal. Can, with minimal disturbance of the tracking error signal generated by a scratch on the disk surface or the like, is capable to allow the retrieval of stable tracking control with high accuracy.

[Brief description of the drawings]

FIG. 1 is a block diagram of a tracking error detection device according to a first embodiment of the present invention.

FIG. 2 is a waveform diagram of a main part according to the first embodiment.

FIG. 3 is a block diagram of a phase difference storage unit according to one embodiment of the present invention;

FIG. 4 is a block diagram of an erase pulse generating means according to one embodiment of the present invention;

FIG. 5 is a block diagram of a second logic unit according to an embodiment of the present invention;

FIG. 6 is a block diagram of a first logic unit according to an embodiment of the present invention;

FIG. 7 is a block diagram of a low-pass filter according to one embodiment of the present invention.

FIG. 8 is a block diagram of a conventional tracking error signal detection device.

FIG. 9 is a main part waveform diagram of a tracking error detection device in a conventional example.

FIG. 10 is a waveform diagram of a main part of a tracking error detection device according to a conventional example.

FIG. 11 is a main part waveform diagram of a tracking error detection device in a conventional example.

[Explanation of symbols]

 Reference Signs List 1 quadrant light receiving element 2 adder 3 adder 4 binarization means 5 binarization means 6 phase comparison means 7 first logic means 8 phase difference storage means 9 pulse width detection means 10 erase pulse generation means 11 second Logic means 12 low-pass filter 13 pulse width limiting means 14 pulse width limiting means

Claims (2)

[Claims] 1. A means for irradiating a laser beam near an information track of an optical information recording medium, a divided light receiving means provided in an optical path of the reflected beam, and a first light receiving element constituting the divided light receiving means A tracking error signal detecting device for detecting a mutual phase difference between output signals of the first and second light receiving element groups and forming a tracking error signal, wherein a phase comparing means of the output of the first and second light receiving element groups is provided. Erasing pulse generating means for generating an erasing pulse from the output of the phase comparing means, the output of the storing means, and the output of the pulse width detecting means; and the logical output of the output of the phase comparing means and the output of the erasing pulse generating means. First logic means for generating, and second logic means for generating a logical output of an output of the phase comparing means, an output of the erasing pulse generating means, and an output of the storage means; A filter for obtaining a tracking error signal from an output of the second logic means;
A tracking error signal detection device configured to control the storage means and the pulse width detection means by an output of the logic means. 2. The tracking error signal detecting device according to claim 1, wherein said filter is a low-pass filter.