JPH11126979A - Multi-layer substrate and its base material - Google Patents

Multi-layer substrate and its base material

Info

Publication number
JPH11126979A
JPH11126979A JP9289989A JP28998997A JPH11126979A JP H11126979 A JPH11126979 A JP H11126979A JP 9289989 A JP9289989 A JP 9289989A JP 28998997 A JP28998997 A JP 28998997A JP H11126979 A JPH11126979 A JP H11126979A
Authority
JP
Japan
Prior art keywords
polyimide
layer
substrate
interface
surface roughness
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9289989A
Other languages
Japanese (ja)
Inventor
Koji Kanamori
孝司 金森
Toshikatsu Takada
俊克 高田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Niterra Co Ltd
Original Assignee
NGK Spark Plug Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NGK Spark Plug Co Ltd filed Critical NGK Spark Plug Co Ltd
Priority to JP9289989A priority Critical patent/JPH11126979A/en
Publication of JPH11126979A publication Critical patent/JPH11126979A/en
Pending legal-status Critical Current

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Abstract

PROBLEM TO BE SOLVED: To provide high adhesion to an insulating layer of organic high polymer and to prevent the insulating layer from blistering or peeling by specifying a surface roughness of the surface of a ceramics substrate. SOLUTION: With a surface roughness of a ceramics substrate 2 equal to 0.25 μmRa or above, the rough of a surface is appropriately coarse, thus adhesion to an insulating layer 3 of organic high polymer is raised. So, at manufacturing, the organic high polymer layer 3 is prevented from 'blistering' or 'peeling'. Further, when a multiple multi-layer substrates 1 are cut out of a base material, the organic high polymer layer is hard to peel off, preventing occurrence of a defective article. Although the adhesion is higher when a surface roughness is higher than a specified value, which is preferable, such new issue arises as variation in resistance value becomes larger if the surface roughness exceeds 1.0 μmRa. Therefore, the substrate with roughness 1.0 μmRa or less appropriate as variation in resistance value is small. Here, Ra is center line average roughness specified by JIS.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、セラミック基板の
表面にポリイミド等の有機高分子からなる絶縁層を積層
してなる例えばIC基板等に用いられる多層基板及びそ
の母材に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multi-layer substrate formed by laminating an insulating layer made of an organic polymer such as polyimide on the surface of a ceramic substrate and used for, for example, an IC substrate and a base material thereof.

【0002】[0002]

【従来の技術】従来より、例えば集積回路基板(IC基
板)等の基板として、セラミック基板の表面にポリイミ
ド等の有機高分子からなる絶縁層を積層してなる多層基
板が知られている。
2. Description of the Related Art Hitherto, as a substrate such as an integrated circuit substrate (IC substrate), there has been known a multilayer substrate formed by laminating an insulating layer made of an organic polymer such as polyimide on the surface of a ceramic substrate.

【0003】この多層基板に関する技術として、例えば
特開昭63−148659号公報には、ポリイミドを層
間絶縁層とした場合に、ポリイミド下の電極又は配線金
属の表面を、ポリイミドとの密着に優れた物質で覆う技
術が記載されている。また、実開平1−113387号
公報には、下層のポリイミド絶縁層の端部を、セラミッ
ク基板の上面に達するまで覆う技術が記載されている。
As a technique relating to this multi-layer substrate, for example, Japanese Patent Application Laid-Open No. 63-148659 discloses that, when polyimide is used as an interlayer insulating layer, the surface of an electrode or wiring metal under the polyimide is excellent in adhesion to the polyimide. Techniques for covering with materials are described. Japanese Utility Model Laid-Open Publication No. 1-11387 discloses a technique of covering an end of a lower polyimide insulating layer until it reaches the upper surface of a ceramic substrate.

【0004】[0004]

【発明が解決しようとする課題】しかしながら、上述し
た技術では、直接に有機高分子層とセラミック基板との
密着性を上げることができないので、必ずしも十分では
ない。つまり、従来では、セラミック基板の表面にポリ
イミド等からなる有機高分子層を積層すると、密着強度
が不足して、製造時等に有機高分子層が歪んで膨れる
「フクレ」や、有機高分子層がセラミック基板から剥が
れる「剥がれ」が生じるという問題があった。
However, the above-mentioned technique is not always sufficient because the adhesion between the organic polymer layer and the ceramic substrate cannot be directly increased. In other words, conventionally, when an organic polymer layer made of polyimide or the like is laminated on the surface of a ceramic substrate, the adhesion strength is insufficient, and the organic polymer layer is distorted and swelled during manufacturing or the like. However, there was a problem that "peeling" was caused to peel off from the ceramic substrate.

【0005】また、セラミック基板上に有機高分子層を
複数積層した多層基板を製造する場合には、一挙に多く
の多層基板を製造するために、目的とする寸法より大き
な多層基板の母材を製造し、それを切断して所望の寸法
の多層基板を多数切り出しているが、その切断の際に、
セラミック基板と有機高分子層との間で剥がれが生じ、
不良品が多発するという問題があった。
In the case of manufacturing a multi-layer substrate in which a plurality of organic polymer layers are laminated on a ceramic substrate, in order to manufacture many multi-layer substrates at once, a base material of the multi-layer substrate larger than a target size is required. Manufacture and cut it to cut out a large number of multi-layer boards of desired dimensions.
Peeling occurs between the ceramic substrate and the organic polymer layer,
There was a problem that defective products frequently occurred.

【0006】更に、有機高分子としてポリイミドを用い
る際には、セラミック基板の反りを低減するために、セ
ラミック基板と接する層に低膨張ポリイミドを使用する
ことがあるが、この場合には、分子鎖が剛直で直線状な
ため、密着強度は更に低下するという問題もあった。
Further, when polyimide is used as an organic polymer, a low expansion polyimide may be used for a layer in contact with the ceramic substrate in order to reduce the warpage of the ceramic substrate. However, there is also a problem that the adhesion strength is further reduced because of being rigid and linear.

【0007】そこで、本発明は、セラミックと有機高分
子との密着性に優れた多層基板及びその母材を提供する
ことを目的とする。
Accordingly, an object of the present invention is to provide a multilayer substrate having excellent adhesion between a ceramic and an organic polymer and a base material thereof.

【0008】[0008]

【課題を解決するための手段】上記目的を達成するため
になされた請求項1に記載の発明は、セラミック基板の
表面に、有機高分子からなる絶縁層を多数積層してなる
多層基板において、セラミック基板の表面の面粗度を、
0.25μmRa以上、1.0μmRa以下とすること
を特徴とする多層基板を要旨とする。
Means for Solving the Problems According to the first aspect of the present invention, there is provided a multi-layer substrate comprising a ceramic substrate and a plurality of insulating layers made of an organic polymer laminated on a surface of the ceramic substrate. The surface roughness of the surface of the ceramic substrate
The gist of the present invention is a multi-layer substrate characterized by being at least 0.25 μmRa and at most 1.0 μmRa.

【0009】つまり、セラミック基板の面粗度を0.2
5μmRa以上とすると、表面の凹凸が適度に粗くなっ
て、有機高分子からなる絶縁層(以下有機高分子層とも
記す)との密着性が高まる。それによって、製造時等に
おける有機高分子層の「フクレ」や「剥がれ」を防止す
ることができる。また、多くの多層基板を母材から切断
して切り出す場合にも、有機高分子層が剥がれ難く、不
良品の発生を防止できる。
That is, the surface roughness of the ceramic substrate is set to 0.2.
When it is 5 μmRa or more, the surface irregularities are appropriately roughened, and the adhesion to an insulating layer made of an organic polymer (hereinafter also referred to as an organic polymer layer) is enhanced. Thereby, "swelling" and "peeling" of the organic polymer layer at the time of manufacturing or the like can be prevented. Also, when many multi-layer substrates are cut from the base material and cut out, the organic polymer layer is hardly peeled off, and the occurrence of defective products can be prevented.

【0010】また、上述した様に、面粗度が所定値より
高い方が密着性が高く好ましいが、面粗度が1.0μm
Raを越える場合は、抵抗値のばらつきが大きくなると
いう別な問題が生じる。従って、1.0μmRa以下の
ものは、抵抗値のばらつきが小さく好適である。
As described above, it is preferable that the surface roughness is higher than a predetermined value because the adhesion is high and the surface roughness is preferably 1.0 μm.
When it exceeds Ra, another problem that the variation of the resistance value becomes large arises. Therefore, those having a resistance of 1.0 μm Ra or less have a small variation in the resistance value and are suitable.

【0011】この抵抗値が悪くなるのは、面粗度が大き
くなると、セラミック基板の表面に形成する電極層の寸
法のばらつき、及び抵抗層の寸法ばらつきが大きくな
り、また、シート抵抗(セラミック基板側の抵抗)もば
らつくため、全体として抵抗層における抵抗値のばらつ
きが大きくなると考えられる。
The reason why the resistance value deteriorates is that when the surface roughness increases, the dimensional variation of the electrode layer formed on the surface of the ceramic substrate and the dimensional variation of the resistance layer increase, and the sheet resistance (the ceramic substrate) increases. It is considered that the variation of the resistance value in the resistance layer becomes large as a whole because the resistance of the resistance layer also varies.

【0012】ここで、Raとは、JISにて規定される
中心線平均粗さである。また、セラミック基板の材料と
しては、アルミナ、窒化アルミニウム、ムライト、マグ
ネシウム、窒化珪素、スピネル等の焼結セラミックや、
結晶化ガラス、ガラス−セラミック複合体等の低温焼成
材料などが挙げられる。
Here, Ra is a center line average roughness defined by JIS. Further, as the material of the ceramic substrate, alumina, aluminum nitride, mullite, magnesium, silicon nitride, sintered ceramics such as spinel,
Low-temperature fired materials such as crystallized glass and glass-ceramic composites are exemplified.

【0013】請求項2の発明は、セラミック基板の表面
の面粗度を、0.4μmRa以上とすることを特徴とす
る請求項1に記載の多層基板を要旨とする。特に面粗度
が0.4μmRa以上の場合には、一層密着力が高く、
前記請求項1の発明によって得られる効果が一層顕著と
なるので好適である。
According to a second aspect of the present invention, there is provided a multilayer substrate as set forth in the first aspect, wherein the surface roughness of the surface of the ceramic substrate is 0.4 μm Ra or more. In particular, when the surface roughness is 0.4 μm Ra or more, the adhesion is even higher,
This is preferable because the effect obtained by the invention of claim 1 becomes more remarkable.

【0014】請求項3の発明は、有機高分子がポリイミ
ドであることを特徴とする請求項1又は2に記載の多層
基板を要旨とする。つまり、本発明では、絶縁層の材料
として、有機高分子であるポリイミドを採用することが
できる。
According to a third aspect of the present invention, there is provided a multilayer substrate according to the first or second aspect, wherein the organic polymer is polyimide. That is, in the present invention, polyimide, which is an organic polymer, can be adopted as the material of the insulating layer.

【0015】請求項4の発明は、絶縁層は、セラミック
基板の表面に接する通常の熱膨張係数を有する通常ポリ
イミドからなる界面部ポリイミド層と、界面部ポリイミ
ド層に積層される通常より小さい熱膨張係数を有する低
膨張ポリイミドからなる上ポリイミド層とを備えること
を特徴とする請求項3に記載の多層基板を要旨とする。
According to a fourth aspect of the present invention, the insulating layer has an interface polyimide layer made of a normal polyimide having a normal coefficient of thermal expansion in contact with the surface of the ceramic substrate, and a lower thermal expansion laminated on the interface polyimide layer. The multi-layer substrate according to claim 3, further comprising an upper polyimide layer made of a low expansion polyimide having a coefficient.

【0016】つまり、本発明では、従来とは逆に、熱膨
張率が大きな通常ポリイミドを用いて界面部ポリイミド
層を形成するとともに、熱膨張係数の小さな低膨張ポリ
イミドを用いて上ポリイミド層を形成している。この通
常ポリイミドは、低膨張ポリイミドに比べて、分子鎖が
比較的柔軟で直線状ではないため、セラミック基板に対
する密着性が高い。また、低膨張ポリイミドは、分子鎖
が剛直で直線状であるため、基板の反りに対する耐性が
高い。
That is, in the present invention, contrary to the prior art, the interface polyimide layer is formed using normal polyimide having a large coefficient of thermal expansion, and the upper polyimide layer is formed using low expansion polyimide having a small coefficient of thermal expansion. doing. This ordinary polyimide has higher adhesion to the ceramic substrate because the molecular chain is relatively flexible and not linear, as compared with the low expansion polyimide. In addition, the low expansion polyimide has a high resistance to substrate warpage because the molecular chain is rigid and linear.

【0017】従って、本発明によれば、通常ポリイミド
により密着性を高め、低膨張ポリイミドによって反りを
防止するので、密着性及び反りにおいて共に高い性能を
実現することができる。ここで、通常ポリイミドとは、
熱膨張係数が、30×10-6/℃以上のものを示し、一
方、低膨張ポリイミドとは、通常ポリイミドより熱膨張
係数が小さな、好ましくは20×10-6/℃以下のもの
を示す。例えば通常ポリイミドとしては、熱膨張係数が
58[×10-6/℃]の日立化成工業社製のPIQ(商
品名)を採用でき、一方、低膨張ポリイミドとしては、
熱膨張係数が10[×10-6/℃]の日立化成工業社製
のPIX−L110SX(商品名)や、熱膨張係数が2
0[×10-6/℃]の東レ社製のUR−5100FX
(商品名)等を採用できる。
Therefore, according to the present invention, the adhesion is usually increased by the polyimide, and the warpage is prevented by the low expansion polyimide, so that both the adhesion and the warpage can be realized with high performance. Here, the usual polyimide is
A polyimide having a coefficient of thermal expansion of 30 × 10 −6 / ° C. or more, while a low-expansion polyimide usually has a coefficient of thermal expansion smaller than that of polyimide, preferably 20 × 10 −6 / ° C. or less. For example, as a normal polyimide, a PIQ (trade name) manufactured by Hitachi Chemical Co., Ltd. having a thermal expansion coefficient of 58 [× 10 −6 / ° C.] can be adopted.
PIX-L110SX (trade name) manufactured by Hitachi Chemical Co., Ltd. having a coefficient of thermal expansion of 10 [× 10 −6 / ° C.], or having a coefficient of thermal expansion of 2
0 [× 10 -6 / ° C] UR-5100FX manufactured by Toray
(Product name) or the like can be adopted.

【0018】請求項5の発明は、界面部ポリイミド層の
厚さが、0.1μm以上、25μm以下であることを特
徴とする請求項4に記載の多層基板を要旨とする。つま
り、界面部ポリイミドの厚さが0.1μm以上である
と、セラミックとポリイミド層との密着性が確保できる
という利点があり、25μm以下であると、基板の反り
が小さく抑えられるという利点があるので、この範囲が
好適である。
According to a fifth aspect of the invention, there is provided a multi-layer substrate according to the fourth aspect, wherein the thickness of the interface polyimide layer is 0.1 μm or more and 25 μm or less. That is, when the thickness of the interface polyimide is 0.1 μm or more, there is an advantage that the adhesion between the ceramic and the polyimide layer can be ensured, and when it is 25 μm or less, there is an advantage that the warpage of the substrate can be suppressed small. Therefore, this range is preferable.

【0019】請求項6の発明は、界面部ポリイミド層の
厚さが、1μm以上、10μm以下であることを特徴と
する請求項5に記載の多層基板を要旨とする。つまり、
界面部ポリイミドの厚さが1μm以上、10μm以下で
あると、前記請求項5に記載した利点が一層大きくなる
ので、この範囲が一層好適である。
According to a sixth aspect of the present invention, there is provided a multilayer substrate as set forth in the fifth aspect, wherein the thickness of the interface polyimide layer is 1 μm or more and 10 μm or less. That is,
If the thickness of the polyimide at the interface is 1 μm or more and 10 μm or less, the advantage described in claim 5 becomes even greater, so this range is more preferable.

【0020】請求項7の発明は、多層基板が切り出され
る母材であって、請求項1〜6のいずれかに記載の多層
基板と同様な構成を有することを特徴とする多層基板の
母材を要旨とする。つまり、本発明では、母材から切り
出された多層基板ではなく、母材自身を示している。こ
の母材は、上述した多層基板と寸法は異なるものの同様
な構成を有しているので、高い密着性や抵抗のばらつき
の少なさ等の同様な効果を奏する。
According to a seventh aspect of the present invention, there is provided a base material from which a multilayer substrate is cut out, wherein the base material has a configuration similar to that of the multilayer substrate according to any one of the first to sixth aspects. Is the gist. That is, in the present invention, the base material itself is shown, not the multilayer substrate cut out from the base material. Since the base material has a similar configuration to the above-described multilayer substrate, although the dimensions are different, similar effects such as high adhesion and small variation in resistance are exhibited.

【0021】[0021]

【発明の実施の形態】本発明の多層基板及びその母材の
例(実施例)を図に基づいて説明する。 a)図1に本実施例の多層基板1の一部を破断して示す
が、多層基板1は、集積回路(IC)が搭載される基板
であり、セラミック基板2の表面に、複数のポリイミド
層からなる絶縁層3が積層されたものである。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Examples (embodiments) of a multilayer substrate and a base material thereof according to the present invention will be described with reference to the drawings. a) A part of the multilayer substrate 1 according to the present embodiment is cut away and shown in FIG. 1. The multilayer substrate 1 is a substrate on which an integrated circuit (IC) is mounted. Insulating layer 3 composed of layers is laminated.

【0022】前記セラミック基板2は、アルミナからな
り、縦横各20mm×厚さ1.0mmである。一方、絶
縁層3は、セラミック基板2の表面に直接に接合される
厚さ3μmの界面部ポリイミド層4と、界面部ポリイミ
ド層4の上に積層される4層の上ポリイミド層5、即ち
界面部ポリイミド層4側から、厚さ22μmの上第1ポ
リイミド層6、厚さ25μmの上第2ポリイミド層7、
厚さ25μmの上第3ポリイミド層8、厚さ25μmの
上第4ポリイミド層9から構成されている。
The ceramic substrate 2 is made of alumina and has a length and width of 20 mm and a thickness of 1.0 mm. On the other hand, the insulating layer 3 includes a 3 μm-thick interface polyimide layer 4 that is directly bonded to the surface of the ceramic substrate 2, and four upper polyimide layers 5 stacked on the interface polyimide layer 4, that is, the interface polyimide layer 4. From the side of the polyimide layer 4, the first polyimide layer 6 having a thickness of 22 μm, the second polyimide layer 7 having a thickness of 25 μm,
It comprises an upper third polyimide layer 8 having a thickness of 25 μm and an upper fourth polyimide layer 9 having a thickness of 25 μm.

【0023】このうち、界面部ポリイミド層4は、比較
的大きな熱膨張係数を有する通常ポリイミドからなり、
例えば熱膨張係数が58[×10-6/℃]の日立化成工
業社製のPIQ(商品名)から構成されている。また、
4層の上ポリイミド層5の各々は、熱膨張係数が小さな
低膨張ポリイミドからなり、例えば熱膨張係数が10
[×10-6/℃]の日立化成工業社製のPIX−L11
0SX(商品名)、又は熱膨張係数が20[×10-6
℃]の東レ社製のUR−5100FX(商品名)から構
成されている。
Of these, the interface polyimide layer 4 is made of ordinary polyimide having a relatively large coefficient of thermal expansion.
For example, it is composed of a PIQ (trade name) manufactured by Hitachi Chemical Co., Ltd. having a thermal expansion coefficient of 58 [× 10 −6 / ° C.]. Also,
Each of the four upper polyimide layers 5 is made of a low-expansion polyimide having a small coefficient of thermal expansion.
[× 10 −6 / ° C.] PIX-L11 manufactured by Hitachi Chemical Co., Ltd.
0SX (trade name) or a coefficient of thermal expansion of 20 [× 10 -6 /
C]] of UR-5100FX (trade name) manufactured by Toray Industries, Inc.

【0024】また、前記セラミック基板2の表面や、上
ポリイミド層5の各々の層の層間もしくは表面には、例
えばCr−Ti−Cu−Ni−Auからなる表面配線層
11やCr−Ti−Cu−Auからなる内部配線層1
1’が設けられ、各配線層11,11’を基板の厚み方
向に接続するために、例えばCuが孔に充填されてなる
ビア12が設けられている。
The surface wiring layer 11 made of, for example, Cr-Ti-Cu-Ni-Au or the Cr-Ti-Cu -Internal wiring layer 1 made of Au
1 ′ is provided, and a via 12 in which holes are filled with, for example, Cu is provided to connect the respective wiring layers 11, 11 ′ in the thickness direction of the substrate.

【0025】従って、前記界面部ポリイミド層4は、セ
ラミック基板2の表面のうち表面配線層11の設けられ
ていないセラミック部分を覆うとともに、表面配線層1
1の表面をも覆っている。 b)次に、本実施例の多層基板1の製造方法について、
図2に基づいて説明する。
Therefore, the interface polyimide layer 4 covers the ceramic portion of the surface of the ceramic substrate 2 where the surface wiring layer 11 is not provided, and also covers the surface wiring layer 1.
1 also covers the surface. b) Next, a method for manufacturing the multilayer substrate 1 of the present embodiment will be described.
A description will be given based on FIG.

【0026】図2は、多層基板1の製造過程を模式的に
示したものであり(特に縦方向を横方向より大きく拡大
している)、ここでは、本実施例の構成を明瞭にするた
めに、従来例(比較例)をも合わせて記載する。 セラミック板形成工程 まず、Al23、SiO2、CaO等のセラミック材料
と有機成形助剤を用い、ドクターブレード法によりグリ
ーンシートを形成し、これを、脱バインダー後、150
0〜1550℃の条件で焼成して、セラミック基板2の
切断前の板であるセラミック板21を製造する。
FIG. 2 schematically shows the manufacturing process of the multilayer substrate 1 (particularly, the vertical direction is larger than the horizontal direction). Here, in order to clarify the configuration of this embodiment. A conventional example (comparative example) will also be described. First, a green sheet is formed by a doctor blade method using a ceramic material such as Al 2 O 3 , SiO 2 , CaO and an organic molding aid.
By firing at a temperature of 0 to 1550 ° C., a ceramic plate 21 which is a plate before cutting the ceramic substrate 2 is manufactured.

【0027】このセラミック板21は、縦横各110m
m×厚さ1.0mmのアルミナセラミック製の板材であ
り、後述する様に、多層基板母材(母材)22を縦横各
々5列に切断することにより、5×5=合計25個の多
層基板1が切り出される。 研磨工程 次に、セラミック板21の表面を、所定の範囲(即ち
0.25μmRa以上、1μmRa以下)の面粗度とな
る様に、所定の粗さの研磨材を使用して研磨する。ここ
では、研磨により0.27μmRaの面粗度とした。
尚、従来例は、0.02μmRaである。
The ceramic plate 21 is 110 m in length and width.
It is a plate material made of alumina ceramic having a mx 1.0 mm thickness. As will be described later, a multi-layer substrate base material (base material) 22 is cut into five rows and five rows each to obtain 5 x 5 = 25 total multilayers. The substrate 1 is cut out. Polishing Step Next, the surface of the ceramic plate 21 is polished using a polishing material having a predetermined roughness so as to have a surface roughness within a predetermined range (that is, 0.25 μmRa or more and 1 μmRa or less). Here, the surface roughness was set to 0.27 μmRa by polishing.
Incidentally, in the conventional example, it is 0.02 μmRa.

【0028】界面部ポリイミド層形成工程 次に、セラミック板21表面の必要な箇所に、フォトレ
ジストの技術を用い、メッキによって配線層11を形成
した後に、セラミック板21表面及び配線層11の表面
に前記の通常ポリイミドを塗布し、その後乾燥させて、
界面部ポリイミド層4を形成する。尚、図2では、前記
図1で示した配線層11,11’及びビア12は省略し
てある。
Step of Forming Interface Polyimide Layer Next, the wiring layer 11 is formed by plating using a photoresist technique on a required portion of the surface of the ceramic plate 21, and then the surface of the ceramic plate 21 and the surface of the wiring layer 11 are formed. Apply the above-mentioned usual polyimide, then dry it,
An interface polyimide layer 4 is formed. In FIG. 2, the wiring layers 11, 11 'and the vias 12 shown in FIG. 1 are omitted.

【0029】上ポリイミド層形成工程 次に、界面部ポリイミド層4の表面に、前記の低膨張ポ
リイミドを塗布し、その後乾燥させて、上第1ポリイミ
ド層6を形成する。その後、界面部ポリイミド層4及び
上第1ポリイミド層6の必要な箇所、即ちセラミック板
21上の配線層11と接触可能な箇所に、フォトリソグ
ラフ等によって、ビア12となるスルーホール(図示せ
ず)を明ける。
Next, the above-mentioned low expansion polyimide is applied to the surface of the interface polyimide layer 4 and then dried to form the upper first polyimide layer 6. Thereafter, through holes (not shown) which become vias 12 are formed by photolithography or the like at necessary portions of the interface portion polyimide layer 4 and the upper first polyimide layer 6, that is, portions which can be in contact with the wiring layer 11 on the ceramic plate 21. ).

【0030】次に、上第1ポリイミド層6の表面の必要
な箇所に、フォトレジストの技術を用い、メッキによっ
て配線層11を形成するとともに、スルーホール内にC
uペーストを充填する。以下同様にして、上第2〜上第
4ポリイミド層7〜9を形成するとともに、各層におい
て配線層11及びビア12を形成し、多層基板母材22
を製造する。
Next, a wiring layer 11 is formed by plating using a photoresist technique at a necessary portion of the surface of the upper first polyimide layer 6, and a C layer is formed in the through hole.
Fill with u paste. Similarly, the upper second to upper fourth polyimide layers 7 to 9 are formed in the same manner, and the wiring layers 11 and the vias 12 are formed in the respective layers.
To manufacture.

【0031】切断工程 次に、多層基板母材22を、切断器(図示せず)を用い
て、縦横各々5列に切断して、合計25個の多層基板1
を切り出す。この様に、本実施例では、セラミック基板
2の表面の面粗度を、0.27μmRaの様に0.25
μmRa以上としているので、セラミック基板2と界面
部ポリイミド層4との密着強度が大きい。そのため、絶
縁層3のフクレを防止できるとともに、図3に示す様
に、多層基板母材22を切断する際の絶縁層3の(比較
例の様な)剥がれを防止することができる。
Cutting Step Next, the multi-layer substrate base material 22 is cut into five rows and five columns using a cutter (not shown), and a total of 25 multi-layer substrates 1 are cut.
Cut out. Thus, in this embodiment, the surface roughness of the surface of the ceramic substrate 2 is set to 0.25 μm, such as 0.27 μm Ra.
Since it is at least μmRa, the adhesion strength between the ceramic substrate 2 and the interface polyimide layer 4 is large. Therefore, it is possible to prevent blistering of the insulating layer 3 and, as shown in FIG. 3, to prevent the insulating layer 3 from peeling (as in the comparative example) when cutting the multilayer substrate base material 22.

【0032】また、本実施例では、界面部ポリイミド層
4に、それほど剛直ではない通常ポリイミドを使用して
いるので、その点からも、セラミック基板2への密着性
に優れている。更に、本実施例では、絶縁層3の大部分
を占める上ポリイミド層5に、剛直な低膨張ポリイミド
を使用しているので、多層基板1の反りを防止できると
いう効果がある。 <実験例>次に、本実施例の多層基板の効果を確認する
ために行った実験例について説明する。
Further, in this embodiment, since the ordinary polyimide which is not so rigid is used for the interface portion polyimide layer 4, the adhesiveness to the ceramic substrate 2 is excellent also from that point. Further, in the present embodiment, since the rigid low expansion polyimide is used for the upper polyimide layer 5 occupying most of the insulating layer 3, there is an effect that the warpage of the multilayer substrate 1 can be prevented. <Experimental Example> Next, an experimental example performed to confirm the effect of the multilayer substrate of the present embodiment will be described.

【0033】ここでは、セラミック基板の表面の面粗度
(表面粗度)を変更するとともに、界面部ポリイミド層
及び上ポリイミド層を構成するポリイミドの種類を変更
した。そして、下記の様にしてカッターナイフ評価、
切断時の剥がれ、基板の反り量、抵抗バラツキを
測定した。その結果を、下記表1に記す。
Here, the surface roughness (surface roughness) of the surface of the ceramic substrate was changed, and the kind of polyimide constituting the interface polyimide layer and the upper polyimide layer was changed. Then, as shown below, cutter knife evaluation,
Peeling during cutting, the amount of substrate warpage, and resistance variation were measured. The results are shown in Table 1 below.

【0034】カッターナイフ評価 カッターナイフをセラミック基板と界面部ポリイミド層
との間に差込み、剥がれ易いか否かを調べた。表1にお
いて、1,2,3,4,5のうち数値が大きいほど剥が
れ易いことを示している。
Evaluation of Cutter Knife A cutter knife was inserted between the ceramic substrate and the polyimide layer at the interface, and it was examined whether or not it was easily peeled. In Table 1, it is shown that the larger the numerical value among 1, 2, 3, 4, and 5, the easier it is to peel off.

【0035】切断時の剥がれ 切断により100個の多層基板を製造した場合におい
て、界面部ポリイミド層がセラミック基板から剥がれた
ものの個数を示した。 基板の反り量 多層基板母材において、図4(a)に示す様な反り量を
測定した。
Peeling at the time of cutting In the case where 100 multilayer substrates were manufactured by cutting, the number of polyimide layers in which the interface portion polyimide layer was peeled off from the ceramic substrate was shown. The amount of warpage of the substrate The amount of warpage as shown in FIG.

【0036】抵抗バラツキ 図4(b),(c)に示す様に、セラミック基板上に電
極層(縦300μm×横300μm×厚さ5μm)を形
成し、この電極層間に、Ta3Nからなる縦横200μ
mの寸法の抵抗層を形成してその抵抗値を測定した。そ
して、目標とする抵抗値(50Ω)に対してどの程度バ
ラツキがあるかを調べた。
Resistance Variation As shown in FIGS. 4B and 4C, an electrode layer (300 μm × 300 μm × 5 μm in thickness) is formed on a ceramic substrate, and Ta 3 N is formed between the electrode layers. Length and width 200μ
A resistance layer having a dimension of m was formed, and the resistance value was measured. Then, the degree of variation with respect to the target resistance value (50Ω) was examined.

【0037】尚、以下の表において、総合の評価の欄
は、×,△,○,◎の順で評価が高くなることを示して
いる。
In the following table, the column of total evaluation indicates that the evaluation becomes higher in the order of ×, Δ, ○, ◎.

【0038】[0038]

【表1】 [Table 1]

【0039】更に、界面部ポリイミド層の厚さを変更し
て複数の多層基板を製造して、セラミック基板との密着
性及び基板の反り量を確認した。その結果を表2に記
す。
Further, a plurality of multilayer substrates were manufactured by changing the thickness of the interface portion polyimide layer, and the adhesion to the ceramic substrate and the amount of warpage of the substrate were confirmed. Table 2 shows the results.

【0040】[0040]

【表2】 [Table 2]

【0041】また、表1及び表2のポリイミドの種類
A,B,Cを下記表3に記す。
The types A, B and C of the polyimides in Tables 1 and 2 are shown in Table 3 below.

【0042】[0042]

【表3】 [Table 3]

【0043】i)前記表1から明かな様に、面粗度が
0.25μmRa以上の場合には、剥がれが少なく好適
である。また、抵抗バラツキは、面粗度が小さいほど小
さく、特に、面粗度が1.0μmRa以下の場合には、
±10%以内であるので、好適である。
I) As is clear from Table 1, when the surface roughness is 0.25 μm Ra or more, it is preferable that the peeling is small. The resistance variation is smaller as the surface roughness is smaller. In particular, when the surface roughness is 1.0 μmRa or less,
This is preferable because it is within ± 10%.

【0044】従って、剥がれ及び抵抗バラツキを考慮す
ると、面粗度が0.25μmRa以上、1μmRa以下
の範囲内が好適である。尚、面粗度が0.4μmRa以
上の場合には、剥がれが更に少なく一層好適である。
Therefore, considering the peeling and the resistance variation, it is preferable that the surface roughness is in the range of 0.25 μmRa or more and 1 μmRa or less. When the surface roughness is 0.4 μm Ra or more, the peeling is further reduced, which is more preferable.

【0045】ii)更に、多層基板の反りに関しては、界
面部ポリイミド層と上ポリイミド層とが、低膨張ポリイ
ミドA−低膨張ポリイミドA、低膨張ポリイミドA−低
膨張ポリイミドA、通常ポリイミドC−低膨張ポリイミ
ドAの関係の場合が好適であるが、カッターナイフ評価
及び切断時の剥がれの実験結果によって示される密着性
は、界面部ポリイミド層が通常ポリイミドから形成され
ているものが高い。
Ii) Further, with respect to the warpage of the multilayer substrate, the polyimide layer at the interface and the upper polyimide layer are made of low expansion polyimide A-low expansion polyimide A, low expansion polyimide A-low expansion polyimide A, and usually polyimide C-low. The case of the expanded polyimide A is preferable, but the adhesiveness indicated by the experimental results of the evaluation of the cutter knife and the peeling at the time of cutting is high when the interface portion polyimide layer is usually formed of polyimide.

【0046】従って、反りが少なく且つ密着性の高いも
のは、界面部ポリイミド層と上ポリイミド層とが、通常
ポリイミドC−低膨張ポリイミドAの関係のものである
ことが分かる。尚、界面部ポリイミド層と上ポリイミド
層とが、低膨張ポリイミドA−低膨張ポリイミドA、低
膨張ポリイミドA−低膨張ポリイミドAの関係の場合で
も、面粗度が、0.25μmRa以上、1.0μmRa
以下の範囲内であれば、ある程度密着性が高いという効
果はある。
Therefore, it can be understood that the polyimide having a small warpage and high adhesiveness has a relationship between the polyimide layer at the interface portion and the polyimide layer at the upper layer, which is usually a polyimide C-low expansion polyimide A. Note that even when the interface polyimide layer and the upper polyimide layer have a relationship of low expansion polyimide A-low expansion polyimide A, low expansion polyimide A-low expansion polyimide A, the surface roughness is 0.25 μm Ra or more. 0 μm Ra
Within the following range, there is an effect that the adhesion is high to some extent.

【0047】iii)また、前記表2から明かな様に、界
面部ポリイミド層の厚さが、0.1μm以上、25μm
以下の場合には、密着性を確保しつつ、基板の反り量も
少ない点で好適であり、特に、界面部ポリイミド層の厚
さが、1μm以上、10μm以下の場合は、その効果が
一層顕著になる。
Iii) As apparent from Table 2, the thickness of the polyimide layer at the interface is 0.1 μm or more and 25 μm or more.
In the following cases, it is preferable in that the amount of warpage of the substrate is small while ensuring the adhesion, and the effect is more remarkable particularly when the thickness of the interface polyimide layer is 1 μm or more and 10 μm or less. become.

【0048】[0048]

【発明の効果】上述した様に、請求項1に記載の発明で
は、セラミック基板の表面の面粗度を、0.25μmR
a以上、1.0μmRa以下とするので、有機高分子か
らなる絶縁層との密着性が高く、該絶縁層の「フクレ」
や「剥がれ」を防止することができる。また、抵抗値の
ばらつきが小さく好適である。
As described above, according to the first aspect of the present invention, the surface roughness of the surface of the ceramic substrate is set to 0.25 μmR.
Since it is not less than a and not more than 1.0 μmRa, the adhesiveness with the insulating layer made of an organic polymer is high, and “swelling” of the insulating layer
And "peeling" can be prevented. In addition, the resistance value is preferably small in variation.

【0049】請求項2の発明では、セラミック基板の表
面の面粗度を、0.4μmRa以上とするので、一層密
着力が高く好適である。請求項3の発明では、絶縁層の
材料として、有機高分子であるポリイミドを用いるの
で、絶縁性や耐熱性などに優れている。
According to the second aspect of the present invention, since the surface roughness of the surface of the ceramic substrate is set to 0.4 μmRa or more, it is preferable to further increase the adhesion. According to the third aspect of the present invention, since the insulating layer is made of polyimide, which is an organic polymer, the insulating layer is excellent in insulation properties and heat resistance.

【0050】請求項4の発明では、セラミック基板の表
面に界面部ポリイミド層を積層し、更に上ポリイミド層
を積層するので、セラミック基板に対する密着性が高
く、しかも、基板の反りに対する耐性が高い。請求項5
の発明では、界面部ポリイミド層の厚さが、0.1μm
以上、25μm以下であるので、セラミック基板に対す
る密着性を高く維持し、基板の反りを小さく抑えられ
る。
According to the fourth aspect of the present invention, since the interface polyimide layer is laminated on the surface of the ceramic substrate and the upper polyimide layer is further laminated, the adhesion to the ceramic substrate is high, and the resistance to warpage of the substrate is high. Claim 5
In the invention, the thickness of the interface polyimide layer is 0.1 μm
As described above, since the thickness is 25 μm or less, the adhesion to the ceramic substrate is maintained high, and the warpage of the substrate can be suppressed to a small value.

【0051】請求項6の発明では、界面部ポリイミド層
の厚さが、1μm以上、10μm以下であるので、一層
上記の効果が大きい。請求項7の発明では、多層基板が
切り出される母材は、多層基板と同様な構成を有してい
るので、高い密着性や抵抗のばらつきの少なさ等の同様
な効果を奏する。
According to the sixth aspect of the present invention, since the thickness of the interface polyimide layer is not less than 1 μm and not more than 10 μm, the above effect is further enhanced. According to the seventh aspect of the present invention, since the base material from which the multilayer substrate is cut has the same configuration as the multilayer substrate, similar effects such as high adhesion and small variation in resistance can be obtained.

【図面の簡単な説明】[Brief description of the drawings]

【図1】 実施例の多層基板を一部破断して示す説明
図。
FIG. 1 is an explanatory diagram showing a multilayer substrate according to an embodiment with a part cut away.

【図2】 実施例の多層基板の製造方法を、従来例とと
もに示す説明図である。
FIG. 2 is an explanatory view showing a method for manufacturing a multilayer substrate according to an embodiment together with a conventional example.

【図3】 切断後の多層基板の状態を示す説明図であ
る。
FIG. 3 is an explanatory diagram showing a state of the multilayer substrate after cutting.

【図4】 実験例を示し、(a)は反りを示す説明図、
(b)は抵抗の実験例を示す平面図、(c)は(b)の
I−I断面図である。
FIG. 4 shows an experimental example, (a) is an explanatory diagram showing warpage,
(B) is a plan view showing an experimental example of resistance, and (c) is a cross-sectional view taken along the line II of (b).

【符号の説明】[Explanation of symbols]

1…多層基板 2…セラミック基板 3…絶縁層 4…界面部ポリイミド層 5…上ポリイミド層 6…上第1ポリイミド層 7…上第2ポリイミド層 8…上第3ポリイミド層 9…上第4ポリイミド層 11…表面配線層 11’…内部配線層 12…ビア 21…セラミック板 22…多層基板母材 DESCRIPTION OF SYMBOLS 1 ... Multilayer board 2 ... Ceramic substrate 3 ... Insulating layer 4 ... Interface polyimide layer 5 ... Upper polyimide layer 6 ... Upper first polyimide layer 7 ... Upper second polyimide layer 8 ... Upper third polyimide layer 9 ... Upper fourth polyimide Layer 11: Surface wiring layer 11 ': Internal wiring layer 12: Via 21: Ceramic plate 22: Multilayer substrate base material

Claims (7)

【特許請求の範囲】[Claims] 【請求項1】 セラミック基板の表面に、有機高分子か
らなる絶縁層を多数積層してなる多層基板において、 前記セラミック基板の表面の面粗度を、0.25μmR
a以上、1.0μmRa以下とすることを特徴とする多
層基板。
1. A multilayer substrate comprising a ceramic substrate and a plurality of insulating layers made of an organic polymer laminated on the surface thereof, wherein the surface of the ceramic substrate has a surface roughness of 0.25 μmR.
a multilayer substrate having a thickness of not less than a and not more than 1.0 μmRa.
【請求項2】 前記セラミック基板の表面の面粗度を、
0.4μmRa以上とすることを特徴とする前記請求項
1に記載の多層基板。
2. The surface roughness of the surface of the ceramic substrate,
2. The multilayer substrate according to claim 1, wherein the thickness is 0.4 μm Ra or more.
【請求項3】 前記有機高分子がポリイミドであること
を特徴とする前記請求項1又は2に記載の多層基板。
3. The multilayer substrate according to claim 1, wherein the organic polymer is polyimide.
【請求項4】 前記絶縁層は、前記セラミック基板の表
面に接する通常の熱膨張係数を有する通常ポリイミドか
らなる界面部ポリイミド層と、該界面部ポリイミド層に
積層される通常より小さい熱膨張係数を有する低膨張ポ
リイミドからなる上ポリイミド層とを備えることを特徴
とする前記請求項3に記載の多層基板。
4. The insulating layer has an interface polyimide layer made of normal polyimide having a normal thermal expansion coefficient in contact with the surface of the ceramic substrate, and a lower thermal expansion coefficient laminated on the interface polyimide layer. The multilayer substrate according to claim 3, further comprising an upper polyimide layer made of a low-expansion polyimide.
【請求項5】 前記界面部ポリイミド層の厚さが、0.
1μm以上、25μm以下であることを特徴とする前記
請求項4に記載の多層基板。
5. The method according to claim 1, wherein the polyimide layer at the interface has a thickness of 0.1.
The multilayer substrate according to claim 4, wherein the thickness is 1 m or more and 25 m or less.
【請求項6】 前記界面部ポリイミド層の厚さが、1μ
m以上、10μm以下であることを特徴とする前記請求
項5に記載の多層基板。
6. The method according to claim 1, wherein the thickness of the interface polyimide layer is 1 μm.
The multilayer substrate according to claim 5, wherein the thickness is not less than m and not more than 10 µm.
【請求項7】 多層基板が切り出される母材であって、 前記請求項1〜6のいずれかに記載の多層基板と同様な
構成を有することを特徴とする多層基板の母材。
7. A base material from which a multilayer substrate is cut out, wherein the base material has a configuration similar to that of the multilayer substrate according to any one of claims 1 to 6.
JP9289989A 1997-10-22 1997-10-22 Multi-layer substrate and its base material Pending JPH11126979A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9289989A JPH11126979A (en) 1997-10-22 1997-10-22 Multi-layer substrate and its base material

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9289989A JPH11126979A (en) 1997-10-22 1997-10-22 Multi-layer substrate and its base material

Publications (1)

Publication Number Publication Date
JPH11126979A true JPH11126979A (en) 1999-05-11

Family

ID=17750347

Family Applications (1)

Application Number Title Priority Date Filing Date
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Country Status (1)

Country Link
JP (1) JPH11126979A (en)

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04262593A (en) * 1991-02-18 1992-09-17 Hitachi Ltd Multilayer interconnection structure and multilayers laminating method therefor
JPH0637206A (en) * 1992-07-16 1994-02-10 Ngk Insulators Ltd Thin film multilayer substrate and manufacture thereof
JPH0661369A (en) * 1992-08-12 1994-03-04 Ngk Insulators Ltd Manufacture of thin film multilayer board
JPH06310855A (en) * 1993-04-21 1994-11-04 Tokuyama Soda Co Ltd Manufacture of multilayer wiring board
JPH07263864A (en) * 1994-03-18 1995-10-13 Fujitsu Ltd Thin-film multilayer substrate and its manufacture
JPH09135077A (en) * 1995-11-07 1997-05-20 Ibiden Co Ltd Fabrication of printed circuit board

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JPH04262593A (en) * 1991-02-18 1992-09-17 Hitachi Ltd Multilayer interconnection structure and multilayers laminating method therefor
JPH0637206A (en) * 1992-07-16 1994-02-10 Ngk Insulators Ltd Thin film multilayer substrate and manufacture thereof
JPH0661369A (en) * 1992-08-12 1994-03-04 Ngk Insulators Ltd Manufacture of thin film multilayer board
JPH06310855A (en) * 1993-04-21 1994-11-04 Tokuyama Soda Co Ltd Manufacture of multilayer wiring board
JPH07263864A (en) * 1994-03-18 1995-10-13 Fujitsu Ltd Thin-film multilayer substrate and its manufacture
JPH09135077A (en) * 1995-11-07 1997-05-20 Ibiden Co Ltd Fabrication of printed circuit board

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