JPH11126873A - High-frequency circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a high-frequency circuit in which a low-loss spiral inductor is formed on a semiconductor substrate. SOLUTION: In a high-frequency circuit in which a spiral inductor is formed on a semiconductor substrate, windings 2 of the spiral inductor are formed of the second layer above the lowermost layer of metallic wiring layers which are provided on a plurality of insulators 9 laminated on a semiconductor substrate 8 and of metallic wirings in which metallic wiring layers above the second layer are laminated, and a part for leading out the winding 2 from the inside to the outside is formed of a metallic wiring, including a first layer metallic layer on the lowermost layer and a second layer metallic wiring thereabove. Further, the crossing part of the winding 2 and leading-out part is formed of a metallic wiring, including the uppermost layer metallic wiring above the metallic wiring which is used for the leading-out part.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high-frequency circuit formed on a semiconductor substrate, and more particularly to a reduction in loss of a spiral inductor and a capacitor.

[0002]

2. Description of the Related Art Conventionally, a spiral inductor formed on a silicon substrate of this type is disclosed in, for example, J. Org. N. B
urghartz, et. al. , “Microwav
e Inducers and Capacitor
s in StandardMultilevel I
nterconnect Silcon Techno
logic ", IEEE Trans. Microwav.
e Theory Tech. , Vol. MTT-4
4, no. 1, pp. 100-104 (1996.1)
There is what was shown in. FIG. 18 is a plan view of a conventional spiral inductor formed on a silicon substrate described in the above-mentioned document. FIG. 19 is a cross-sectional view of a portion (three-dimensionally) where the winding of the spiral inductor shown in FIG. FIG. 19A is a cross-sectional view of the AA 'layer at the intersection in FIG. 18, and FIG. 19B is a cross-sectional view of the BB' layer at the intersection in FIG. In the figure, 2 is a spiral inductor winding, 4 is a fourth-layer metal wiring, 5a, 5
In the drawing, b is an interlayer wiring connecting portion of a lead portion extending from the inside to the outside of the winding, 6 and 7 are external terminals, 9 is an insulator, 10 is a first layer metal wiring, 11 is a second layer metal wiring, and 12 is a third layer metal wiring. Layer metal wiring, 13 is a ground conductor, 17 is a substrate obtained by laminating an insulator on a silicon substrate, and 18 is a silicon substrate.

A winding 2 of a spiral inductor formed on a silicon substrate 18 is formed by laminating a second-layer metal wiring 11, a third-layer metal wiring 12, and a fourth-layer metal wiring 4, and this winding 2 Only the lead portion 3a for drawing the wire from the inside to the outside of the winding is formed of the lowermost first-layer metal wiring 10.

Next, the operation will be described. In FIG. 18, a high-frequency signal is supplied from an external terminal 6 to a second-layer metal wiring 11,
The signal is input to the winding 2 in which the third-layer metal wiring 12 and the fourth-layer metal wiring 4 are stacked, and transmitted through the winding 2. The high-frequency signal transmitted through the winding 2 is finally transmitted through the lowermost first-layer metal wiring 10 through the interlayer wiring connection portion 5a at the entrance of the lead portion drawn out from the inside to the outside of the winding. The winding 2 is transmitted again through the interlayer wiring connection portion 5b at the exit of the portion, and is output to the external terminal 7. 19 (a) and 19 (b)
As shown in (2), the second layer metal wiring 11, the third layer metal wiring 12, and the fourth layer metal wiring 4 are connected to each other at a portion where the winding of the spiral inductor intersects with a lead portion drawn from the inside to the outside of the winding. The stacked windings 2 are separated from the lowermost first-layer metal wiring 10 constituting the lead portion by an insulator 9 in a DC manner.

The lead-out portion of the winding is constituted by the lowermost first-layer metal wiring 10, and the conductor thickness of the lowermost first-layer metal wiring 10 is smaller than that of the uppermost metal wiring due to process restrictions. Therefore, the conductor loss is large, and since the lowermost first-layer metal wiring 10 is located closer to the silicon substrate 18 than the upper-layer metal wiring, when the substrate resistivity is low like a silicon substrate, There is a problem in forming a low-loss spiral inductor on a silicon substrate due to a large dielectric loss.

[0006] Conventionally, as a capacitor formed on a silicon substrate of this kind, for example, Masashi Takahashi, Yoshiki Nagatomo, Fumio Ichikawa, "PolySi-Insulator-
Reliability of PolySi Capacitor ", IEICE Technical Report, Silicon Materials and Devices, SDM89-1
67, pp. 49-54 (1989). FIG. 20 is a cross-sectional view showing a conventional capacitor disclosed in the above document. FIG. 21 is a diagram illustrating the configuration of the capacitor of FIG. In the figure, 6 and 7 are external terminals,
9 is an insulator, 10a and 10b are first layer metal wirings, 13 is a ground conductor, 14 is a lower layer electrode, 15 is a dielectric, 16 is an upper layer electrode, 18 is a silicon substrate, and 19b and 19a are upper and lower layer electrodes. The resistance 20 is the equivalent capacitance of the dielectric.

In this capacitor, a lower electrode 14 is formed using high-resistance polysilicon via an insulator 9 laminated on a silicon substrate 18, and a low-resistance polysilicon is formed thereon via a dielectric 15. The upper electrode 16 is formed by using this. Upper electrode 16, lower electrode 14, and external terminals 6, 7
Are connected using first-layer metal wirings 10a and 10b.

Next, the operation will be described. In FIG. 20, a high-frequency signal input from an external terminal 6 is transmitted to an upper electrode 16 using low-resistance polysilicon via a first-layer metal wiring 10a. This high-frequency signal is transmitted to the upper electrode 1
Via the dielectric 15 between the lower electrode 6 and the lower electrode 14, the phase is transmitted to the lower electrode 14 using high-resistance polysilicon with a phase advance. The high-frequency signal is transmitted from the lower-layer electrode 14 through the first-layer metal wiring 10c and output to the external terminal 7. As shown in FIG. 21, this capacitor is an equivalent circuit in which an equivalent capacitance 20 of a dielectric 15 formed between upper and lower electrodes and respective equivalent resistors 19b and 19a of upper and lower electrodes 16 and 14 are connected in series. Can be represented by Here, the equivalent resistance 19a corresponds to the lower electrode 14 using high-resistance polysilicon, and the equivalent resistance 19b corresponds to the upper electrode 16 using low-resistance polysilicon.

The electrode used in this type of capacitor is polysilicon (polycrystalline silicon) doped with impurities instead of metal due to process restrictions, and the substrate resistivity of polysilicon changes depending on the amount of impurities doped. The larger the impurity doping amount, the lower the substrate resistivity becomes, which is closer to a metal, and the lower the resistance value of the electrode becomes. The lower electrode 14 using high-resistivity polysilicon is made of 1 layer using low-resistivity polysilicon.
6, the equivalent resistance 19a has a higher resistance value than the equivalent resistance 19b. Since a series circuit of the equivalent capacitance of the dielectric between the upper and lower electrodes and the equivalent resistance of the upper and lower electrodes is connected between the external terminals 6 and 7, when the equivalent resistance of the electrodes increases, the insertion loss of this capacitor decreases. growing.

[0010]

A conventional spiral inductor formed on a semiconductor substrate is configured as described above, and the lowermost layer constituting a lead portion extending from the inside to the outside of the winding of the spiral inductor is formed. Due to process constraints, the first-layer metal wiring has a conductor thickness smaller than that of the upper-layer metal wiring, resulting in a larger conductor loss, and the lowermost first-layer metal wiring has a larger thickness than the upper-layer metal wiring. When the substrate is located near the silicon substrate and has a low substrate resistivity such as a silicon substrate, the dielectric loss is large, and this is a problem in reducing the loss of the spiral inductor formed on the semiconductor substrate.

A conventional capacitor formed on a semiconductor substrate is configured as described above. The equivalent capacitance of the dielectric between the upper and lower electrodes between the external terminals 6 and 7 and the capacitance of the upper and lower electrodes are formed. A series circuit of equivalent resistance is connected, the resistance of polysilicon (polycrystalline silicon) used for the upper and lower electrodes is large, the insertion loss of this capacitor is large, and the capacity formed on the semiconductor substrate is reduced. There was a problem.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and has as its object to obtain a high-frequency circuit in which a low-loss spiral inductor or capacitor is formed on a semiconductor substrate.

[0013]

According to a first aspect of the present invention, there is provided a high frequency circuit for forming a spiral inductor on a semiconductor substrate.
The winding of the spiral inductor uses a metal wiring in which a second layer of the uppermost layer of the lowermost layer and a metal wiring of each layer above the lowermost layer among the respective layers of metal wiring provided on the plurality of insulators stacked on the semiconductor substrate, The lead-out portion that pulls out this winding from the inside to the outside is formed by a lowermost first-layer metal wiring and a second upper-layer metal wiring.
A layered metal wiring including a layered metal wiring is used, and a portion where the winding intersects with the lead-out portion is formed using a metal wiring including an uppermost-layer metal wiring above the metal wiring used in the lead-out portion. It is characterized by the following.

According to a second aspect of the present invention, there is provided a high frequency circuit for forming a spiral inductor on a semiconductor substrate, wherein the winding of the spiral inductor is formed on a plurality of insulators provided on a plurality of insulators laminated on the semiconductor substrate. Among the metal wirings, a metal wiring in which a second upper layer of the lowermost layer and a metal wiring of each layer above the lowermost layer are laminated, and a lead portion for drawing out this winding from the inside to the outside is a second layer metal of the upper layer of the lowermost layer. A wire or a laminated metal wire including a second-layer metal wire and a metal wire in an upper layer thereof is used, and a portion where the winding intersects the lead portion is a top metal layer above the metal wire used in the lead portion. It is characterized by being formed using metal wiring including wiring.

According to a third aspect of the present invention, there is provided a high frequency circuit for forming a spiral inductor on a semiconductor substrate, wherein the winding of the spiral inductor is provided on a plurality of layers provided on a plurality of insulators laminated on the semiconductor substrate. Among the metal wires, a metal wire obtained by laminating a second upper layer of the lowermost layer and a metal wire of each layer above the lower layer is used, and a portion where this winding intersects with a lead portion for drawing this winding from inside to outside is:
A stacked metal wiring including a lowermost first-layer metal wiring and a second-layer metal wiring above the lower-layer metal wiring is used, and the lead portion is formed in a layer above the metal wiring used in a portion where the winding crosses the lead portion. It is characterized by being formed using a metal wiring including the uppermost metal wiring.

According to a fourth aspect of the present invention, there is provided a high-frequency circuit for forming a spiral inductor on a semiconductor substrate, wherein the winding of the spiral inductor is formed on a plurality of insulators provided on a plurality of insulators laminated on the semiconductor substrate. Among the metal wires, a metal wire obtained by laminating a second upper layer of the lowermost layer and a metal wire of each layer above the lower layer is used, and a portion where this winding intersects with a lead portion for drawing this winding from inside to outside is:
A second-layer metal wiring in the uppermost layer of the lowermost layer or a metal wiring in which the second-layer metal wiring and the upper-layer metal wiring are stacked is used, and the lead portion is a metal used in a portion where the winding intersects with the lead portion. It is formed using a metal wiring including an uppermost metal wiring above the wiring.

According to a fifth aspect of the present invention, there is provided a high-frequency circuit for forming a capacitor on a semiconductor substrate, wherein the capacitor is formed of a lower layer using high-resistance polysilicon via an insulator laminated on the semiconductor substrate. Forming electrodes,
An upper electrode is formed by using a low-resistance polysilicon and a metal wiring laminated thereon with a dielectric interposed therebetween.

According to a sixth aspect of the present invention, there is provided a high-frequency circuit for forming a capacitor on a semiconductor substrate, wherein the capacitor is formed of low-resistance polysilicon via an insulator laminated on the semiconductor substrate. Forming electrodes,
It is characterized in that an upper layer electrode is formed using metal wiring with a dielectric interposed therebetween.

[0019]

BEST MODE FOR CARRYING OUT THE INVENTION

Embodiment 1 FIG. FIG. 1 is a plan view of a spiral inductor formed on a semiconductor substrate according to the first embodiment of the present invention. FIG. 2 is a cross-sectional view of a portion where the winding of the spiral inductor of FIG. 1 intersects with a lead-out portion of the winding (intersection of the winding). FIG. 2 (a) shows the cross section A of the winding 2 in FIG.
FIG. 2B is a cross-sectional view of the BB ′ layer at the intersection of the windings 2 in FIG. 1. FIG. 3 is a sectional view of the CC 'layer of the winding 2 of the spiral inductor of FIG. Figure 1
In 2 and 3, 1 is a substrate in which an insulator is laminated on a semiconductor substrate, 2 is a winding of a spiral inductor, 3a is a portion where the winding is drawn, 3b is a portion where the winding intersects with the drawing portion,
Reference numerals 5a and 5b denote interlayer wiring connection portions at the leading portions of the windings.
Reference numerals c and 5d denote interlayer wiring connecting portions where the windings intersect with the lead-out portions, 6, 7 are external terminals, 8 is a semiconductor substrate, 9 is an insulator, 10 is a first-layer metal wiring, and 11 is a second-layer metal. Wiring, 1
Reference numeral 2 denotes a third-layer metal wiring, and reference numeral 13 denotes a ground conductor.

Referring to FIG. 1, FIG. 2 and FIG. 3, winding 2 of the spiral inductor formed on semiconductor substrate 8 in the first embodiment has a second-layer metal wiring 11 and a third-layer metal wiring 12. And a metal wiring in which the fourth-layer metal wiring 4 is laminated. A drawer portion 3 drawn from the inside to the outside of the winding 2
a is the lowermost first-layer metal wiring 10, the second-layer metal wiring 1
A metal wiring in which the first and third-layer metal wirings 12 are stacked is used, and a portion 3b where the winding 2 intersects with the above-mentioned lead portion 3a uses a fourth-layer metal wiring 4.

Next, the operation will be described. In FIG. 1, a high-frequency signal is input from the external terminal 6 to the winding 2 and
A spiral winding made of a metal wiring in which the layer metal wiring 11, the third layer metal wiring 12, and the fourth layer metal wiring 4 are stacked is transmitted, and the winding comes to a portion 3b where the winding intersects with the lead-out portion of the winding. Each time, the fourth-layer metal wiring 4 is transmitted via the interlayer line connecting portion 5c, returns to the winding 2 again via the interlayer line connecting portion 5d, and finally comes to the lead portion 3a which is drawn from the inside to the outside of the winding. And a metal wiring in which the lowermost first-layer metal wiring 10, the second-layer metal wiring 11, and the third-layer metal wiring 12 are stacked via the inter-layer line connection 5a, and transmitted again via the inter-layer line connection 5b. Return to the winding 2 and output to the external terminal 7.

With the above configuration, the metal wiring forming the lead portion 3a of the winding 2 of the spiral inductor uses the lowermost first-layer metal wiring 10, second-layer metal wiring 11, and third-layer metal wiring 12. Because of the process restrictions, the laminated metal wiring has a thicker conductor and a smaller conductor loss than the conventional metal wiring formed of the lowermost first-layer metal wiring 10 due to process restrictions. A low-loss spiral inductor can be formed on a semiconductor substrate.
Note that the same applies to the lead-out portion 3a of the winding, whether a stacked metal wiring is used or a metal wiring on a plurality of insulators connected in parallel at the interlayer line connecting portion without being stacked. It works.

Embodiment 2 FIG. FIG. 4 is a cross-sectional view of a portion where a winding of a spiral inductor and a lead-out portion of the winding intersect, showing Embodiment 2 of the present invention. The plan view of the spiral inductor formed on the semiconductor substrate according to the second embodiment is the same as that of FIG. The sectional view of the winding of the spiral inductor of the second embodiment is the same as that of FIG. 4A is a cross-sectional view of the AA 'layer at the intersection of the windings 2 in FIG. 1, and FIG. 4B is a cross-sectional view of the BB' layer at the intersection of the windings 2 in FIG. In the figure, FIGS.
The same reference numerals are given to the same components as.

Referring to FIG. 4 and FIGS. 1 and 3 of the first embodiment, winding 2 of the spiral inductor formed on semiconductor substrate 8 in the second embodiment is similar to that of the first embodiment. A metal wiring in which a two-layer metal wiring 11, a third-layer metal wiring 12, and a fourth-layer metal wiring 4 are stacked is used. The lead portion 3a extending from the inside to the outside of the winding 2 uses a metal wiring in which the lowermost first-layer metal wiring 10 and the second-layer metal wiring 11 are laminated.
The portion 3b intersecting with a uses the third-layer metal wiring 12 and the fourth-layer metal wiring 4.

With the above configuration, the metal wiring forming the lead-out portion 3a of the winding of the spiral inductor is formed using a metal wiring in which the lowermost first-layer metal wiring 10 and second-layer metal wiring 11 are laminated. Therefore, compared to the conventional metal wiring formed by the lowermost first-layer metal wiring having a small conductor thickness due to process restrictions, the laminated metal wiring has a large conductor thickness and a small conductor loss, and has a low level on a semiconductor substrate. A lossy spiral inductor can be formed. Here, for the lead portion 3a of the winding 2 and the portion 3b that intersects with the lead portion 3a of the winding 2, even if a laminated metal wire is used, the metal wires on the plurality of insulators are not laminated and the interlayer line connection is performed. The same effect can be obtained by using a part connected in parallel.

Embodiment 3 FIG. FIG. 5 is a cross-sectional view of a portion where a winding of a spiral inductor and a lead-out portion of the winding intersect, showing Embodiment 3 of the present invention. The plan view of the spiral inductor formed on the semiconductor substrate according to the third embodiment is the same as FIG. 1 according to the first embodiment except that the winding configuration of the spiral inductor is different and the winding 2 is replaced by the winding 2a. Therefore, the description is omitted. FIG. 5A shows the winding 2 of FIG.
FIG. 5B is a cross-sectional view of the AA 'layer at the intersection of the winding 2a and FIG. 5B is a cross-sectional view of the BB' layer at the intersection of the winding 2 of FIG. 1 as the winding 2a. In the figure, the same components as those in FIGS.

Referring to FIG. 5 and FIG. 1 of the first embodiment, the winding 2a of the spiral inductor formed on semiconductor substrate 8 in the third embodiment is different from the first embodiment in that the second-layer metal wiring 11 and a third-layer metal wiring 12 are used. A lead portion 3a extending from the inside to the outside of the winding 2a is a lowermost first-layer metal wiring 10
And a metal wiring in which the second-layer metal wiring 11 is laminated,
A portion 3b where the winding 2a intersects with the above-mentioned lead-out portion of the winding
Uses only the uppermost third-layer metal wiring 12.

With the above configuration, the metal wiring forming the lead portion 3a of the winding 2a of the spiral inductor is formed using a metal wiring in which the lowermost first-layer metal wiring 10 and second-layer metal wiring 11 are stacked. Therefore, compared to the conventional example in which the first layer metal wiring of the lowermost layer having a small conductor thickness is formed due to process restrictions, the laminated metal wiring has a large conductor thickness and a small conductor loss, and the metal loss on the semiconductor substrate is small. Thus, a low-loss spiral inductor can be formed. Note that the lead portion 3a of the winding 2a may be formed by using a stacked metal wiring, or by using a metal wiring on a plurality of insulators connected in parallel at an interlayer line connection portion without being stacked. Has the effect of

Embodiment 4 FIG. 6 is a cross-sectional view of a portion where a winding of a spiral inductor and a lead-out portion of the winding intersect each other according to Embodiment 4 of the present invention. Note that a plan view of a spiral inductor formed on a semiconductor substrate according to the fourth embodiment is the same as FIG. The sectional view of the winding of the spiral inductor according to the fourth embodiment is the same as that of FIG. 6A is a cross-sectional view of the AA 'layer at the intersection of the windings 2 in FIG. 1, and FIG. 6B is a cross-sectional view of the bb' layer at the intersection of the windings 2 in FIG. In the figure, FIGS.
The same reference numerals are given to the same components as.

Referring to FIG. 6 and FIGS. 1 and 3 of the first embodiment, winding 2 of the spiral inductor formed on semiconductor substrate 8 in the fourth embodiment is similar to that of the first embodiment. A metal wiring in which a second-layer metal wiring 11, a third-layer metal wiring 12, and a fourth-layer metal wiring 4 are stacked is used.
Unlike the first embodiment, the lead portion 3a extending from the inside to the outside of the winding 2 uses a metal wiring in which the second-layer metal wiring 11 and the third-layer metal wiring 12 on the lowermost layer are laminated, and the winding 2 3b intersects with the above-mentioned lead portion 3a of the winding
Uses the fourth-layer metal wiring 4 in the uppermost layer.

According to the above configuration, the metal wiring forming the lead-out portion 3a of the winding of the spiral inductor is composed of the second-layer metal wiring 11 and the third-layer metal wiring 12 on the lowermost layer.
Is formed using a metal wiring in which the semiconductor substrate is laminated, so that it is located farther from the semiconductor substrate than the conventional one formed by the lowermost first-layer metal wiring close to the semiconductor substrate. Even when the ratio is low, the dielectric loss is reduced, and the metal wiring layered by the laminated metal wiring is smaller than the conventional metal wiring formed by the lowermost first-layer metal wiring whose conductor thickness is thin due to process restrictions. The thickness is large, the conductor loss is small, and a low-loss spiral inductor can be formed on a semiconductor substrate. Note that the same applies to the lead-out portion 3a of the winding, whether a stacked metal wiring is used or a metal wiring on a plurality of insulators connected in parallel at the interlayer line connecting portion without being stacked. It works.

Embodiment 5 FIG. 7 is a cross-sectional view of a portion where a winding of a spiral inductor and a lead-out portion of the winding intersect, showing Embodiment 5 of the present invention. Note that a plan view of a spiral inductor formed on a semiconductor substrate according to the fifth embodiment is similar to that of FIG. The sectional view of the winding of the spiral inductor of the fifth embodiment is the same as that of FIG. 7A is a cross-sectional view of the AA 'layer at the intersection of the windings 2 in FIG. 1, and FIG. 7B is a cross-sectional view of the BB' layer at the intersection of the windings 2 in FIG. In the figure, FIGS.
The same reference numerals are given to the same components as.

Referring to FIG. 7 and FIGS. 1 and 3 of the first embodiment, the winding 2 of the spiral inductor formed on the semiconductor substrate 8 in the fifth embodiment is similar to that of the first embodiment. A metal wiring in which a second-layer metal wiring 11, a third-layer metal wiring 12, and a fourth-layer metal wiring 4 are stacked is used.
Unlike the fourth embodiment, the lead portion 3a extending from the inside to the outside of the winding 2 uses the second-layer metal wiring 11 on the lowermost layer, and the winding 2 intersects with the above-described leading portion 3a of the winding. The portion 3b uses a metal wiring in which a third-layer metal wiring 12 and an uppermost fourth-layer metal wiring 4 are stacked.

With the above configuration, the metal wiring forming the lead-out portion 3a of the winding of the spiral inductor is formed using the second-layer metal wiring 11 in the uppermost layer of the lowermost layer. Compared to the conventional one formed using single-layer metal wiring, it is located farther from the semiconductor substrate, and even when the substrate resistivity of this semiconductor substrate is low,
The dielectric loss is reduced, and the second-layer metal wiring is thicker than the conventional one formed by using the lowermost first-layer metal wiring whose conductor thickness is small due to process restrictions. In addition, the conductor loss is reduced, and a low-loss spiral inductor can be formed on a semiconductor substrate. Here, for the portion 3b where the winding intersects the lead-out portion, using a metal wire on a plurality of insulators connected in parallel at an interlayer line connection portion without using a laminated metal wire even if a laminated metal wire is used. Has the same effect.

Embodiment 6 FIG. FIG. 8 is a cross-sectional view of a portion where a winding of a spiral inductor and a lead-out portion of the winding intersect, showing Embodiment 6 of the present invention. The plan view of the spiral inductor formed on the semiconductor substrate according to the sixth embodiment is the same as FIG. 1 according to the first embodiment except that the winding configuration of the spiral inductor is different and the winding 2 is replaced by the winding 2a. Therefore, the description is omitted. FIG. 8A shows the winding 2 of FIG.
8A is a cross-sectional view of the AA 'layer at the intersection of the winding 2a, and FIG. 8B is a cross-sectional view of the BB' layer at the intersection of the winding 2 of FIG. 1 as the winding 2a. In the figure, the same components as those in FIGS.

Referring to FIG. 8 and FIG. 1 of the first embodiment, the winding 2a of the spiral inductor formed on the semiconductor substrate 8 in the sixth embodiment is different from the first embodiment in the second layer. Metal wiring 11 and third layer metal wiring 12
Are used. The lead portion 3a extending from the inside to the outside of the winding 2a uses the second-layer metal wiring 11 on the lowermost layer, and the portion 3b where the winding 2a intersects with the above-described winding portion 3a is formed in the third layer. The metal wiring 12 is used.

With the above configuration, the metal wiring forming the lead portion 3a of the winding 2a of the spiral inductor is formed using the second-layer metal wiring 11 in the uppermost layer of the lowermost layer. Compared with the conventional one formed using the first-layer metal wiring, the semiconductor substrate is located farther from the semiconductor substrate. Even when the substrate resistivity of the semiconductor substrate is low, the dielectric loss is reduced and the process is reduced. The second-layer metal wiring has a thicker conductor and a smaller conductor loss than the conventional one formed by using the lowermost first-layer metal wiring having a thinner conductor thickness due to the restriction of the above-described method. Thus, a low-loss spiral inductor can be formed.

Embodiment 7 FIG. 9 is a plan view of a spiral inductor formed on a semiconductor substrate according to the seventh embodiment of the present invention. FIG. 10 is a cross-sectional view of a portion where the winding of the spiral inductor shown in FIG. FIG. 10 (a) shows A at the intersection of winding 2 in FIG.
FIG. 10B is a cross-sectional view of the BB ′ layer at the intersection of the windings 2 in FIG. 9. The sectional view of the CC 'layer of the winding of the spiral inductor in FIG. 9 is the same as that in FIG. 9 and 10, reference numeral 1 denotes a substrate obtained by laminating an insulator on a semiconductor substrate, 2 denotes a spiral inductor winding, 3a denotes a winding extraction portion, 3b denotes a portion where the winding intersects with the extraction portion, 5a and 5b. Is an interlayer wiring connection portion at a portion where the winding is drawn, 5c and 5d are interlayer wiring connection portions at a portion where the winding intersects with the drawing portion, 6, 7 are external terminals, 8 is a semiconductor substrate, 9 is an insulator, and 10 is an insulator. A first layer metal wiring, 11 is a second layer metal wiring, 12 is a third layer metal wiring, and 13 is a ground conductor.

Referring to FIGS. 9 and 10 and FIG. 3 of the first embodiment, the winding 2 of the spiral inductor formed on the semiconductor substrate 8 includes the second-layer metal wiring 11 and the third-layer metal wiring 1.
A metal wiring in which the second and fourth-layer metal wirings 4 are stacked is used. A portion 3 where the winding 2 intersects a lead portion 3a of the winding
b is different from the first embodiment, and the lowermost first-layer metal interconnection 1
0, a second layer metal wiring 11 and a third layer metal wiring 12 are stacked. Unlike the first embodiment, the lead portion 3a extending from the inside to the outside of the winding 2 uses the fourth-layer metal wiring 4 of the uppermost layer.

Next, the operation will be described. In FIG. 9, a high-frequency signal is input from the external terminal 6 to the winding 2,
A spiral winding composed of a metal wiring in which the layer metal wiring 11, the third layer metal wiring 12, and the fourth layer metal wiring 4 are laminated is transmitted, and a winding 3d intersects a part 3b where the winding intersects with the lead part 3a of the winding. Each time it arrives, a metal wiring in which the lowermost first-layer metal wiring 10, second-layer metal wiring 11, and third-layer metal wiring 12 are stacked is transmitted via the interlayer line connecting part 5c, and the interlayer line connecting part 5d is connected. When the wire 3 returns to the winding 2 again, and finally reaches the lead portion 3a drawn from the inside to the outside of the winding, the fourth layer metal wiring 4 of the uppermost layer is transmitted through the interlayer line connecting portion 5a. The signal returns to the winding 2 again via 5b and is output to the external terminal 7.

According to the above configuration, the metal wiring forming the portion 3b where the winding 2 of the spiral inductor intersects with the lead-out portion of the winding is the lowermost first-layer metal wiring 10, second-layer metal wiring 11, and second-layer metal wiring. Since the three-layer metal wiring 12 is formed using a stacked metal wiring, the stacked metal wiring is smaller than the conventional metal wiring formed by the lowermost first-layer metal wiring having a small conductor thickness due to process restrictions. The conductor thickness is large, the conductor loss is small, and a low-loss spiral inductor can be formed on a semiconductor substrate. Here, for the portion 3b where the winding 2 intersects with the lead-out portion of the winding, even if the laminated metal wiring is used, the metal wiring on the plurality of insulators is connected in parallel at the interlayer line connection part without being laminated. The same effect can be obtained even if a material is used.

Embodiment 8 FIG. FIG. 11 is a cross-sectional view of a portion where a winding of a spiral inductor and a lead-out portion of the winding intersect, showing Embodiment 8 of the present invention. Note that a plan view of a spiral inductor formed on a semiconductor substrate according to the eighth embodiment is the same as that of FIG. 9 illustrating the seventh embodiment, and a description thereof will be omitted. Further, the sectional view of the winding of the spiral inductor of the eighth embodiment is the same as that of FIG. FIG. 11A is a cross-sectional view of the AA 'layer at the intersection of the windings 2 of FIG. 9, and FIG.
3 is a cross-sectional view of the BB ′ layer at the intersection of FIG. In the figure, the same components as those in FIGS. 9 and 10 are denoted by the same reference numerals.

Referring to FIG. 11, FIG. 9 of the seventh embodiment, and FIG. 3 of the first embodiment, winding 2 of spiral inductor formed on semiconductor substrate 8 in the eighth embodiment.
Uses a metal wiring in which a second-layer metal wiring 11, a third-layer metal wiring 12, and a fourth-layer metal wiring 4 are stacked. A part 3b where the winding 2 intersects with the lead part 3a of the winding differs from the seventh embodiment, and uses a metal wiring in which the lowermost first-layer metal wiring 10 and the second-layer metal wiring 11 are stacked. Unlike the first embodiment, the lead portion 3a extending from the inside to the outside of the winding 2 is different from the third-layer metal wiring 12 and the fourth-layer uppermost layer.
A metal wiring in which layer metal wirings 4 are stacked is used.

With the above configuration, the metal wiring forming the portion 3b where the winding 2 of the spiral inductor intersects with the lead-out portion 3a of the winding is formed by the lowermost first-layer metal wiring 10 and the lower-layer metal wiring 11. Since the metal wiring is formed using the laminated metal wiring, the laminated metal wiring has a thicker conductor thickness than the conventional metal wiring formed by the lowermost first-layer metal wiring 10 having a small conductor thickness due to process restrictions. The conductor loss is reduced, and a low-loss spiral inductor can be formed on the semiconductor substrate. Note that, here, with respect to the drawing portion 3a of the winding and the portion 3b where the winding intersects with the drawing portion,
The same effect can be obtained by using a stacked metal wiring or by using a metal wiring on a plurality of insulators connected in parallel at the interlayer line connection portion without using the stacked metal wiring.

Embodiment 9 FIG. FIG. 12 is a cross-sectional view of a portion where a winding of a spiral inductor and a lead-out portion of the winding intersect, showing Embodiment 8 of the present invention. The plan view of the spiral inductor formed on the semiconductor substrate according to the ninth embodiment is the same as FIG. 9 according to the seventh embodiment except that the winding configuration of the spiral inductor is different and the winding 2 is replaced by the winding 2a. Therefore, the description is omitted. FIG. 12A is a cross-sectional view of the AA 'layer at the intersection between the winding 2 of FIG. 9 as the winding 2a and FIG. 12B is a cross-sectional view of the winding 2 of FIG. It is sectional drawing of the BB 'layer of an intersection part. In the figure, the same components as those in FIGS. 9 and 10 are denoted by the same reference numerals.

Referring to FIG. 12 and FIG. 9 of the seventh embodiment, the winding 2a of the spiral inductor formed on semiconductor substrate 8 in the ninth embodiment differs from that of the seventh embodiment in the second layer. Metal wiring 11 and third layer metal wiring 12
Are used. A part 3b where the winding 2 intersects with the lead part 3a of the winding differs from the seventh embodiment, and uses a metal wiring in which the lowermost first-layer metal wiring 10 and the second-layer metal wiring 11 are stacked. Unlike the first embodiment, the lead portion 3a extending from the inside to the outside of the winding 2 uses the third-layer metal wiring 12 of the highest layer.

With the above configuration, the metal wiring forming the portion 3b where the winding 2a of the spiral inductor intersects with the lead-out portion of the winding is formed by laminating the first-layer metal wiring 10 and the second-layer metal wiring 11 in the lowermost layer. Since the metal wiring is formed using the metal wiring, the laminated metal wiring has a thicker conductor thickness and a lower conductor loss than the conventional metal wiring formed by the lowermost first-layer metal wiring having a smaller conductor thickness due to process restrictions. The size of the spiral inductor can be reduced, and a low-loss spiral inductor can be formed on the semiconductor substrate. In addition, here, even if the laminated metal wiring is used for the portion 3b where the winding 2a intersects the drawn portion,
The same effect can be obtained by using a metal wiring on a plurality of insulators connected in parallel at an interlayer line connection portion without using a stack.

Embodiment 10 FIG. FIG. 13 is a cross-sectional view of a portion where a winding of a spiral inductor and a lead-out portion of the winding intersect each other according to Embodiment 10 of the present invention. Note that a plan view of a spiral inductor formed on a semiconductor substrate according to the tenth embodiment is the same as that of FIG. 9 illustrating the seventh embodiment, and a description thereof will be omitted. Further, a sectional view of the winding of the spiral inductor of the tenth embodiment is shown in FIG.
The description is omitted because it is the same as. FIG. 13A is a cross-sectional view of the AA 'layer at the intersection of the windings 2 in FIG. 9, and FIG.
FIG. 4 is a cross-sectional view of a BB ′ layer at the intersection of the windings 2 of FIG. In the figure, the same components as those in FIGS. 9 and 10 are denoted by the same reference numerals.

Referring to FIG. 13, FIG. 9 of the seventh embodiment, and FIG. 3 of the first embodiment, winding 2 of the spiral inductor formed on semiconductor substrate 8 in the tenth embodiment is the same as that of the second embodiment. A metal wiring in which the layer metal wiring 11, the third layer metal wiring 12, and the fourth layer metal wiring 4 are stacked is used. A portion 3b where the winding 2 intersects with the lead portion 3a of the winding uses a metal wiring in which a second-layer metal wiring 11 and a third-layer metal wiring 12 on the lowermost layer are stacked. The leading portion 3a extending from the inside to the outside of the winding 2 uses the fourth-layer metal wiring 4 of the highest layer.

With the above configuration, the winding 3 of the spiral inductor is connected to the portion 3b intersecting with the lead 3a of the winding.
Is formed using a metal wiring in which a second-layer metal wiring 11 and a third-layer metal wiring 12 on the lowermost layer are stacked.
Compared to the conventional one formed by the lowermost first-layer metal wiring near the semiconductor substrate, the semiconductor substrate is located farther from the semiconductor substrate, and even when the substrate resistivity of the semiconductor substrate is low, the dielectric loss is small. In addition, compared to the conventional metal wiring formed of the lowermost first-layer metal wiring having a small conductor thickness due to process restrictions, the laminated metal wiring has a thicker conductor and a smaller conductor loss, and the semiconductor substrate has a smaller thickness. A low-loss spiral inductor can be formed thereon. Note that, here, a portion 3b where the winding 2a intersects the drawn portion is described.
The same effect can be obtained by using a stacked metal wiring or by using a metal wiring on a plurality of insulators connected in parallel at the interlayer line connection portion without using the stacked metal wiring.

Embodiment 11 FIG. FIG. 14 is a cross-sectional view of a portion where a winding of a spiral inductor and a lead-out portion of the winding intersect, showing an eleventh embodiment of the present invention. Note that a plan view of a spiral inductor formed on a semiconductor substrate according to the eleventh embodiment is similar to that of FIG. A sectional view of a winding of the spiral inductor of the eleventh embodiment is shown in FIG.
The description is omitted because it is the same as. FIG. 14A is a cross-sectional view of the AA 'layer at the intersection of the windings 2 in FIG. 9, and FIG.
FIG. 4 is a cross-sectional view of a BB ′ layer at the intersection of the windings 2 of FIG. In the figure, the same components as those in FIGS. 9 and 10 are denoted by the same reference numerals.

Referring to FIG. 14, FIG. 9 of the seventh embodiment, and FIG. 3 of the first embodiment, the winding 2 of the spiral inductor formed on semiconductor substrate 8 in the eleventh embodiment is A metal wiring in which the layer metal wiring 11, the third layer metal wiring 12, and the fourth layer metal wiring 4 are stacked is used. A portion 3b where the winding 2 intersects with the lead-out portion 3a of the winding uses a second-layer metal wiring 11 on the lowermost layer. Winding 2
A metal wiring formed by laminating a third-layer metal wiring 12 and a fourth-layer metal wiring 4 is used for a lead portion 3a that is drawn from the inside to the outside.

With the above structure, the winding 2 of the spiral inductor is connected to the portion 3b intersecting the lead 3a of the winding.
Is formed using the second-layer metal wiring 11 in the uppermost layer of the lowermost layer, so that it is located farther from the semiconductor substrate than the first-layer metal wiring of the lowermost layer, and the substrate resistivity of this semiconductor substrate is low. In addition, the dielectric loss can be reduced, and the stacked metal wiring is smaller than the conventional metal wiring formed using the lowermost first-layer metal wiring whose conductor thickness is thin due to process restrictions. The conductor thickness is large, the conductor loss can be reduced, and a low-loss spiral inductor can be formed on a semiconductor substrate. Note that the same applies to the lead-out portion 3a of the winding, whether a stacked metal wiring is used or a metal wiring on a plurality of insulators connected in parallel at the interlayer line connecting portion without being stacked. It works.

Embodiment 12 FIG. FIG. 15 is a cross-sectional view of a portion where a winding of a spiral inductor and a lead-out portion of the winding intersect, showing a twelfth embodiment of the present invention. The plan view of the spiral inductor formed on the semiconductor substrate according to the twelfth embodiment is the same as FIG. 9 showing the seventh embodiment except that the winding configuration of the spiral inductor is different and the winding 2 is replaced by the winding 2a. Therefore, the description is omitted. 15A is a cross-sectional view of the AA 'layer at the intersection of the winding 2 of FIG. 9 as the winding 2a, and FIG. 14B is a cross-sectional view of the winding 2 of FIG. 9 as the winding 2a. 13 is a sectional view of a BB ′ layer of FIG. In the figure,
9 and 10 are given the same reference numerals.

Referring to FIG. 15 and FIG. 9 of the seventh embodiment, winding 2 of the spiral inductor formed on semiconductor substrate 8 in the twelfth embodiment has a second-layer metal wiring 11 and a third-layer metal wiring. The metal wiring in which the metal wiring 12 is laminated is used. A portion 3 where the winding 2 intersects a lead portion 3a of the winding
b uses the second-layer metal wiring 11 on the lowermost layer. The extraction portion 3a that extends from the inside to the outside of the winding 2 is
The third layer metal wiring 12 is used.

With the above configuration, the metal wiring forming the portion 3b where the winding 2a of the spiral inductor intersects the lead portion 3a is formed by using the upper-layer second-layer metal wiring 11 on the lowermost layer. In the case where the substrate resistivity of the semiconductor substrate is lower than that of the first-layer metal wiring of the first embodiment, the dielectric loss can be reduced even if the substrate resistivity of the semiconductor substrate is low. The second-layer metal wiring 11 in the upper layer of the lowermost layer has a larger conductor thickness and a smaller conductor loss than the conventional one formed by using the lowermost first-layer metal wiring having a smaller thickness. A low-loss spiral inductor can be formed on a substrate.

Embodiment 13 FIG. FIG. 16 is a sectional view of a capacitor showing a thirteenth embodiment of the present invention. In the figure, 6 and 7 are external terminals, 8 is a semiconductor substrate, 9 is an insulator,
10a and 10b are first-layer metal wirings, 10c is a metal integrated with the first-layer metal wiring, 13 is a ground conductor, 14 is high-resistance polysilicon, 15 is a dielectric, and 16 is low-resistance polysilicon.

In this capacitor, a lower electrode made of high-resistance polysilicon 14 is formed via an insulator 9 laminated on a semiconductor substrate 8, a dielectric 15 is further formed thereon, and a first layer metal is further formed thereon. An upper electrode is formed by laminating a metal 10c integrated with the wiring 10 on the low-resistance polysilicon 16.
The first and second metal wirings 10a and 10b are used to connect the upper and lower electrodes to the external terminals 6 and 7, respectively.

Next, the operation will be described. The high-frequency signal input from the external terminal 6 is transmitted via the first-layer metal wiring 10a to the low-resistance polysilicon 13 in which a metal 10c integrated with the first-layer metal wiring 10a, which is the upper electrode of the capacitor, is laminated. The high-frequency signal transmitted to the upper layer electrode is transmitted from the upper layer electrode to the lower layer electrode made of high-resistance polysilicon 14 with a phase advance by the dielectric 11 interposed therebetween. The high-frequency signal is output from the lower electrode made of the high-resistance polysilicon 14 to the external terminal 7 via the first-layer metal wiring 10b.

As described above, by forming the upper layer electrode from the low-resistance polysilicon 16 in which the metal integrated with the first-layer metal wiring 10a is laminated, the equivalent resistance of the capacitor electrode can be reduced, and the insertion loss of the capacitor can be reduced. Can be reduced.

Embodiment 14 FIG. FIG. 17 is a sectional view of a capacitor according to a fourteenth embodiment of the present invention. In the figure, the same components as those of the thirteenth embodiment are denoted by the same reference numerals and are omitted.

In this capacitor, a lower electrode made of low-resistance polysilicon 16 is formed via an insulator 9 laminated on a semiconductor substrate 8, a dielectric 15 is further formed thereon, and a first layer metal is further formed thereon. An upper electrode made of a metal 10c integrated with the wiring 10a is formed. Here, the connection between the upper electrode and the lower electrode and the external terminals 6 and 7 is made by the first metal wiring 10 respectively.
a and 10b are used.

As described above, by forming the upper layer electrode from the metal 10c integrated with the first layer metal wiring 10a,
The equivalent resistance of the electrodes of the capacitor can be reduced, and the insertion loss of the capacitor can be reduced.

[0064]

As described above, according to the high-frequency circuit of the first aspect of the present invention, the drawing portion for drawing the winding of the spiral inductor from the inside to the outside is formed by the lowermost first-layer metal wiring and the upper-layer metal wiring. Since it is formed by using a laminated metal wiring including a two-layer metal wiring, the conductor thickness is smaller than that of the conventional one formed by the lowermost first-layer metal wiring due to process restrictions. It is possible to obtain a high-frequency circuit which is thick and has small conductor loss and has a low-loss spiral inductor formed on a semiconductor substrate.

According to the high-frequency circuit of the second aspect of the present invention, the lead portion for drawing out the winding of the spiral inductor from the inside to the outside is formed by the uppermost second-layer metal wiring or the second-layer metal wiring and the second-layer metal wiring. When formed using a laminated metal wiring including an upper metal wiring, when the substrate resistivity of the semiconductor substrate is smaller than that of the conventional one formed by the lowermost first-layer metal wiring close to the semiconductor substrate In addition, the dielectric loss is small, and the conductor thickness is large and the conductor loss is small as compared with the conventional one formed by the lowermost first layer metal wiring whose conductor thickness is thin due to process restrictions. Thus, a high-frequency circuit in which a low-loss spiral inductor is formed on a semiconductor substrate can be obtained.

According to the high-frequency circuit of the third aspect of the present invention, the portion intersecting the lead-out portion of the winding of the spiral inductor is formed by connecting the lowermost first-layer metal interconnection and the upper-layer second-layer metal interconnection. Since it is formed using laminated metal wiring including the same, the thickness of the conductor is large and the conductor loss is small compared to the conventional one formed by the first layer metal wiring of the lowermost layer due to the process limitation due to the process limitation. Thus, a high-frequency circuit in which a low-loss spiral inductor is formed on a semiconductor substrate can be obtained.

According to the high frequency circuit of the present invention, the portion of the spiral inductor that intersects with the lead-out portion of the winding is the second layer metal wiring or the second layer metal wiring on the lowermost layer. Since the upper metal wiring is formed using a laminated metal wiring, the lowermost first metal wiring near the semiconductor substrate is formed.
Even when the substrate resistivity of the semiconductor substrate is small as compared with the conventional one formed by layered metal wiring, the dielectric loss is small and the first layer of the lowermost layer whose conductor thickness is thin due to process restrictions is reduced. Compared with the conventional one formed by layer metal wiring, the conductor thickness is large and the conductor loss is small, so that a high-frequency circuit having a low-loss spiral inductor formed on a semiconductor substrate can be obtained.

According to the high-frequency circuit of the invention, the capacitor has a lower electrode formed of high-resistance polysilicon via an insulator laminated on a semiconductor substrate.
Since an upper electrode was formed using low-resistance polysilicon and metal wiring laminated on it with a dielectric sandwiched between them,
It is possible to obtain a high-frequency circuit in which the resistance value of the upper electrode is lower than in the conventional case and a low-loss capacitor is formed on a semiconductor substrate.

According to the high frequency circuit of the present invention, the capacitor has a lower electrode formed of low-resistance polysilicon through an insulator laminated on the semiconductor substrate,
Since the upper layer electrode is formed using metal wiring with a dielectric interposed therebetween, it is possible to obtain a high frequency circuit in which the resistance of both electrodes in the upper and lower layers is lower than before and a low loss capacitor is formed on a semiconductor substrate. Can be.

[Brief description of the drawings]

FIG. 1 is a plan view of a spiral inductor according to a first embodiment of the present invention.

FIG. 2 is a cross-sectional view of a portion where a winding of a spiral inductor and a lead-out portion of the winding intersect, showing Embodiment 1 of the present invention.

FIG. 3 is a cross-sectional view of a winding of the spiral inductor according to the first embodiment of the present invention.

FIG. 4 is a cross-sectional view of a portion where a winding of a spiral inductor and a lead-out portion of the winding intersect, showing Embodiment 2 of the present invention.

FIG. 5 is a cross-sectional view of a portion where a winding of a spiral inductor and a lead-out portion of the winding intersect, showing Embodiment 3 of the present invention.

FIG. 6 is a cross-sectional view of a portion where a winding of a spiral inductor and a lead-out portion of the winding intersect, showing Embodiment 4 of the present invention.

FIG. 7 is a cross-sectional view of a portion where a winding of a spiral inductor and a lead-out portion of the winding intersect, showing Embodiment 5 of the present invention.

FIG. 8 is a cross-sectional view of a portion where a winding of a spiral inductor and a lead-out portion of the winding intersect, showing Embodiment 6 of the present invention.

FIG. 9 is a plan view of a spiral inductor according to a seventh embodiment of the present invention.

10 is a cross-sectional view of a portion where a winding of the spiral inductor of FIG. 9 intersects with a lead-out portion of the winding.

FIG. 11 is a cross-sectional view of a portion where a winding of a spiral inductor and a lead-out portion of the winding intersect, showing Embodiment 8 of the present invention.

FIG. 12 is a cross-sectional view of a portion where a winding of a spiral inductor and a lead-out portion of the winding intersect, showing Embodiment 9 of the present invention.

FIG. 13 is a cross-sectional view of a portion where a winding of a spiral inductor and a lead-out portion of the winding intersect, showing Embodiment 10 of the present invention.

FIG. 14 is a cross-sectional view of a portion where a winding of a spiral inductor and a lead-out portion of the winding intersect, showing an eleventh embodiment of the present invention.

FIG. 15 is a cross-sectional view of a portion where a winding of a spiral inductor and a lead-out portion of the winding intersect, showing Embodiment 12 of the present invention.

FIG. 16 is a sectional view of a capacitor showing a thirteenth embodiment of the present invention.

FIG. 17 is a sectional view of a capacitor according to a fourteenth embodiment of the present invention.

FIG. 18 is a plan view showing a conventional spiral inductor.

FIG. 19 is a cross-sectional view of a portion where a winding of the spiral inductor of FIG. 18 intersects with a lead-out portion of the winding.

FIG. 20 is a sectional view showing a conventional capacitor.

21 is a diagram illustrating a configuration of the capacitor in FIG.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 The board | substrate which laminated | stacked the insulator on the semiconductor substrate 2 The winding of a spiral inductor 4 Fourth-layer metal wiring 3a The lead part of a winding 3b The part where a winding crosses the lead part 5a, 5b The interlayer wiring of the lead part of a winding Connection portions 5c, 5d Interlayer wiring connection portions at portions where windings intersect lead portions 6, 7 External terminals 8 Semiconductor substrate 9 Insulator films 10a, 10b, 10c First-layer metal wires 11 Second-layer metal wires 12 Third Layer metal wiring 13 Ground conductor 14 High resistance polysilicon (high resistance polycrystalline silicon) 15 Dielectric 16 Low resistance polysilicon (low resistance polycrystalline silicon)

 ────────────────────────────────────────────────── ─── Continued on the front page (72) Inventor Shunji Kubo 2-3-2 Marunouchi, Chiyoda-ku, Tokyo Mitsubishi Electric Corporation

Claims (6)

[Claims] In a high-frequency circuit for forming a spiral inductor on a semiconductor substrate, a winding of the spiral inductor is formed of a lowermost upper layer of metal wirings provided on a plurality of insulators laminated on the semiconductor substrate. A metal wiring in which two layers and a metal wiring of each layer above the two layers are stacked is used. The lead portion for drawing out the winding from the inside to the outside is formed by connecting the lowermost first-layer metal wiring and the upper-layer second metal wiring. A portion where the winding intersects the lead portion is formed using a metal wire including an uppermost layer metal wire above the metal wire used in the lead portion. High frequency circuit. 2. A high-frequency circuit for forming a spiral inductor on a semiconductor substrate, wherein a winding of the spiral inductor is formed of a lowermost upper layer of metal wirings provided on a plurality of insulators stacked on the semiconductor substrate. A metal wire formed by laminating two layers and metal wires of each layer above it is used. The lead portion for drawing out this winding from the inside to the outside is formed by the second layer metal wire or the second layer metal wire on the lowermost layer and the upper layer A portion where the winding intersects with the lead-out portion is formed using a metal wire including an uppermost layer metal wire above the metal wire used in the lead-out portion. A high frequency circuit characterized by the above. 3. In a high-frequency circuit for forming a spiral inductor on a semiconductor substrate, a winding of the spiral inductor is formed of a lowermost upper layer among metal wirings provided on a plurality of insulators laminated on the semiconductor substrate. A metal wiring in which two layers and a metal wiring of each layer of the upper layer are stacked is used, and a portion where this winding intersects with a lead portion that draws the winding from the inside to the outside is a lowermost first-layer metal wiring and the same. A stacked metal wiring including an upper-layer second-layer metal wiring is used, and a lead-out portion uses a metal wiring including an uppermost-layer metal wiring above a metal wiring used in a portion where the winding intersects with the lead-out portion. A high-frequency circuit characterized by being formed by: 4. In a high-frequency circuit for forming a spiral inductor on a semiconductor substrate, a winding of the spiral inductor is formed on a lowermost upper layer among metal wirings provided on a plurality of insulators laminated on the semiconductor substrate. A metal wire in which two layers and metal wires of each layer of the upper layer are stacked is used, and a portion where this winding intersects with a lead portion that draws the winding from the inside to the outside is a second layer metal wiring of the lowermost upper layer. Alternatively, a metal wiring in which a second-layer metal wiring and a metal wiring in a layer higher than the second-layer metal wiring are stacked is used, and the lead portion includes an uppermost-layer metal wiring higher than the metal wiring used in a portion where the winding crosses the lead portion. A high-frequency circuit formed using metal wiring. 5. In a high-frequency circuit for forming a capacitor on a semiconductor substrate, the capacitor is formed by forming a lower electrode using high-resistance polysilicon via an insulator laminated on the semiconductor substrate, and forming a dielectric on the lower electrode. A high-frequency circuit characterized by forming an upper layer electrode using low-resistance polysilicon and metal wiring laminated on the low-resistance polysilicon. 6. In a high-frequency circuit for forming a capacitor on a semiconductor substrate, the capacitor is formed by forming a lower electrode using low-resistance polysilicon via an insulator laminated on the semiconductor substrate, and forming a dielectric on the lower electrode. A high-frequency circuit, wherein an upper layer electrode is formed using a metal wiring with the interposition therebetween.