CN214477430U

CN214477430U - Redistribution layer structure with passive component and semiconductor packaging structure

Info

Publication number: CN214477430U
Application number: CN202120794244.7U
Authority: CN
Inventors: 赖振楠
Original assignee: Hosin Global Electronics Co Ltd
Current assignee: Hosin Global Electronics Co Ltd
Priority date: 2021-04-16
Filing date: 2021-04-16
Publication date: 2021-10-22
Anticipated expiration: 2031-04-16

Abstract

The utility model relates to the field of semiconductor technology, particularly, relate to a rewiring layer structure and semiconductor package structure with passive components and parts. The rewiring layer structure with the passive components comprises a laminated substrate and a dielectric layer, wherein a plurality of chip bonding pads are arranged on one side, facing the dielectric layer, of the substrate, a plurality of bump bonding pads are arranged on one side, facing away from the substrate, of the dielectric layer, and rewiring and first passive components with preset resistance values are formed in the dielectric layer. The embodiment of the utility model provides a rewiring layer structure and contain its packaging structure has following technological effect: the redistribution layer is provided with the redistribution lines and the passive components at the same time, so that the redistribution of the IO ports in the chip structure is realized on one hand; on the other hand, the passive components are formed in the redistribution layer structure, so that the space of the redistribution layer is fully utilized, and the integration density and the integration level of various electronic components in the integrated circuit are improved.

Description

Redistribution layer structure with passive component and semiconductor packaging structure

Technical Field

The application relates to the technical field of semiconductors, in particular to a rewiring layer structure with a passive component and a semiconductor packaging structure.

Background

Wafer Level Packaging (WLP) is one of chip Packaging methods, in which a whole Wafer is directly packaged and tested on the Wafer after production is completed, and then the Wafer is cut into single chips without routing or glue filling. The wafer level package has the advantages of small package size and excellent electrical performance after packaging, is easy to be compatible with wafer manufacturing and chip assembly, can simplify the process from wafer manufacturing to product shipment, and reduces the overall production cost.

In order to solve the problem of Redistribution of the IO port in the chip structure, a Redistribution layer (RDL) is used as an interface between a chip and a package in a chip assembly in the chip package in the prior art, so as to implement Redistribution of the pad position of the chip.

However, the existing redistribution layer structure is mainly used for redistribution, so as to achieve electrical connection between the original pad and the new interface, but the main body of the redistribution layer is still a dielectric material occupying a larger space except for redistribution, and has no other new applications, which is not in accordance with the principle that the semiconductor industry continues to improve the integration density of various electronic components by continuously reducing the feature size, so that it is necessary to integrate more electronic components by relying on the redistribution layer structure.

SUMMERY OF THE UTILITY MODEL

In order to solve the technical problems or at least partially solve the technical problems, the application provides a redistribution layer structure with a passive component and a semiconductor packaging structure.

According to the utility model discloses the first aspect of the embodiment provides a rewiring layer structure with passive components and parts.

The rewiring layer structure with the passive components comprises a laminated substrate and a dielectric layer, wherein a plurality of chip bonding pads are arranged on one side, facing the dielectric layer, of the substrate, a plurality of bump bonding pads are arranged on one side, facing away from the substrate, of the dielectric layer, and rewirings and first passive components with preset resistance values are formed in the dielectric layer.

Optionally, in the redistribution layer structure provided in the embodiment of the present invention, the first passive component is a long strip structure and the extending direction thereof is perpendicular to the thickness direction of the substrate.

Optionally, in the redistribution layer structure provided in the embodiment of the present invention, a second passive component is provided in the dielectric layer, the second passive component includes a first metal layer, a second metal layer and a dielectric material layer, the first metal layer and the second metal layer are arranged in parallel and at least have a partial region opposite to each other, and the dielectric material layer is filled between the first metal layer and the second metal layer.

Optionally, in the redistribution layer structure provided in the embodiment of the present invention, the first metal layer is connected to the chip pad through redistribution lines, and the second metal layer is connected to the bump pad through redistribution lines; and/or

The first passive component is connected with the chip bonding pad and the bump bonding pad through rewiring respectively.

Optionally, in the redistribution layer structure provided in the embodiment of the present invention, the first passive component and the second passive component are connected in series and are disposed between the chip pad and the bump pad.

Optionally, in the redistribution layer structure provided in the embodiment of the present invention, the first passive component and the second passive component are connected in parallel and disposed between the chip pad and the bump pad.

According to the utility model discloses in the second aspect, a rewiring layer structure with passive components and parts is provided.

The rewiring layer structure with the passive components comprises a laminated substrate and a medium layer, wherein a plurality of chip bonding pads are arranged on one side, facing the medium layer, of the substrate, a plurality of bump bonding pads are arranged on one side, facing away from the substrate, of the medium layer, rewiring and a third passive component are formed in the medium layer, and the third passive component is a coil which is arranged in a single layer or multiple layers.

Optionally, in the redistribution layer structure provided in the embodiment of the present invention, a magnetic core is disposed in the coil.

Optionally, in the utility model provides an in the rewiring layer structure, the passive components and parts of second have been formed in the dielectric layer of rewiring layer structure, the passive components and parts of second include first metal level, second metal level and dielectric material layer, first metal level and second metal level parallel arrangement just exist partial region at least just right, the dielectric material layer is filled between first metal level and the second metal level, the passive components and parts of third with the passive components and parts of second are parallelly connected or the series arrangement.

According to the utility model discloses in the second aspect of the embodiment, a semiconductor package structure is provided, it includes the utility model provides a rewiring layer structure with passive components and parts that first aspect or second aspect provided.

The embodiment of the utility model provides a rewiring layer structure and contain its packaging structure has following technological effect: the redistribution layer is provided with the redistribution lines and the passive components at the same time, so that the redistribution of the IO ports in the chip structure is realized on one hand; on the other hand, the passive components are formed in the redistribution layer structure, so that the space of the redistribution layer is fully utilized, and the integration density and the integration level of various electronic components in the integrated circuit are improved.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this application, serve to provide a further understanding of the application and to enable other features, objects, and advantages of the application to be more apparent. The drawings and their description illustrate the embodiments of the invention and do not limit it. In the drawings:

fig. 1 is a cross-sectional view of a first redistribution layer structure provided in an embodiment of the present invention;

fig. 2 is a cross-sectional view of a second redistribution layer structure provided in an embodiment of the present invention;

FIG. 3 is an enlarged view of the second passive component shown in FIG. 2;

fig. 4 is a cross-sectional view of a third redistribution layer structure according to an embodiment of the present invention;

fig. 5 is a schematic perspective view of a third passive component provided in fig. 4;

fig. 6 is a cross-sectional view of a fourth redistribution layer structure according to an embodiment of the present invention;

fig. 7 is a schematic perspective view of a third passive component provided in fig. 6;

fig. 8 is a cross-sectional view of a fifth redistribution layer structure according to an embodiment of the present invention;

fig. 9 is a cross-sectional view of a sixth redistribution layer structure according to an embodiment of the present invention;

fig. 10 is a cross-sectional view of a seventh redistribution layer structure according to an embodiment of the present invention;

fig. 11 is a schematic diagram of a circuit structure formed by the first passive component and the second passive component in fig. 10;

fig. 12 is a cross-sectional view of an eighth redistribution layer structure according to an embodiment of the present invention;

fig. 13 is a schematic diagram of a circuit structure formed by the first passive component and the second passive component in fig. 12;

in the figure:

1. a substrate; 2. a dielectric layer; 3. a chip bonding pad; 4. bump pads, 5, rewiring; 6. a first passive component; 7. a second passive component; 701. a first metal layer; 702. a second metal layer; 703. a layer of dielectric material; 8. a third passive component; 801. a first inductor coil; 802. a first conductive line; 803. a second inductor coil; 804. a second conductive line; 805. an inductor core.

Detailed Description

In order to make the technical solutions better understood by those skilled in the art, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only partial embodiments of the present application, but not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

It is noted that the terms "comprises" and "comprising," and any variations thereof, in the description and claims of this application and the above-described drawings are intended to cover non-exclusive inclusions, such that a system, product or apparatus that comprises a list of elements is not necessarily limited to those elements explicitly listed, but may include other elements not expressly listed or inherent to such product or apparatus.

In this application, the terms "upper", "lower", "inner", "middle", "outer", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings. These terms are used primarily to better describe the present application and its embodiments, and are not used to limit the indicated devices, components or elements to a particular orientation or to be constructed and operated in a particular orientation.

Moreover, some of the above terms may be used to indicate other meanings besides the orientation or positional relationship, for example, the term "on" may also be used to indicate some kind of attachment or connection relationship in some cases. The specific meaning of these terms in this application will be understood by those of ordinary skill in the art as appropriate.

Furthermore, the terms "disposed," "connected," and "secured" are to be construed broadly. For example, "connected" may be a fixed connection, a detachable connection, or a unitary construction; can be a mechanical connection, or an electrical connection; may be directly connected, or indirectly connected through intervening media, or may be in internal communication between two devices, components or groups. The specific meaning of the above terms in the present application can be understood by those of ordinary skill in the art as appropriate.

It should be noted that the embodiments and features of the embodiments in the present application may be combined with each other without conflict.

Exemplary embodiments of the present invention will be described in detail below with reference to the accompanying drawings. In the drawings, the thicknesses of layers and regions are exaggerated for convenience of description, and the sizes shown do not represent actual sizes. Although these figures do not reflect the actual dimensions of the device exactly, they do reflect the mutual positions of the regions and the constituent structures, in particular the upper and lower and adjacent relationships between the constituent structures. The reference figures are schematic illustrations of idealized embodiments of the present invention, which should not be construed as limited to the particular shapes of regions shown in the figures, but are to include resulting shapes.

Referring to fig. 1-13, the embodiment of the utility model provides a rewiring layer structure with passive components and parts, this rewiring layer structure is including base 1 and the dielectric layer 2 of range upon range of setting, base 1 orientation one side of dielectric layer 2 is provided with a plurality of chip pad 3, dielectric layer 2 deviates from one side of base 1 is provided with a plurality of lug pads 4, be formed with rewiring 5 and passive components and parts in the dielectric layer 2, can realize electric connection through rewiring 5 between chip pad 3 and the lug pad 4, wherein passive components and parts include but not limited to at least one in first passive components and parts 6, the passive components and parts of second 7 and the passive components and parts of third 8. The first passive component 6 has a preset resistance value and can be used as a resistance component; the second passive component 7 includes a first metal layer 701, a second metal layer 702, and a dielectric material layer 703, where the first metal layer 701 and the second metal layer 702 are arranged in parallel and at least some regions are arranged opposite to each other, and the dielectric material layer 703 is filled between the first metal layer 701 and the second metal layer 702, and can be used as a capacitor component; the third passive component 8 includes a single-layer or multi-layer coil, or the coil has a predetermined inductance value, and can be used as an inductance component.

In the redistribution layer structure provided by the embodiment, the redistribution lines 5 and the passive components are arranged in the redistribution layer at the same time, on one hand, the chip bonding pads 3 and the bump bonding pads 4 are electrically connected through the redistribution lines 5, and the redistribution of the IO ports in the chip structure is realized; on the other hand, a plurality of passive components are formed in the rewiring layer structure, the space of the rewiring layer is fully utilized, so that a resistance component, a capacitance component or an inductance component can be integrated in the rewiring layer, and the integration density and the integration level of various electronic components in the integrated circuit are improved.

In the above embodiment, the material of the substrate 1 may be silicon (Si), germanium (Ge), or silicon germanium (GeSi), silicon carbide (SiC); or silicon-on-insulator (SOI), germanium-on-insulator (GOI); or may be other materials such as group iii-v compounds such as gallium arsenide. Various semiconductor devices such as transistors (including PMOS, NMOS, or CMOS), field effect transistors, as desired, are formed in (or on) the substrate 1. The dielectric layer 2 is located on the surface of the semiconductor substrate and covers the semiconductor device formed in (or on) the semiconductor substrate, and several interconnect structures other than the rewiring 5 may be formed in the dielectric layer 2, which interconnect structures may be connected with the semiconductor device. Since it does not relate to the specific improvement point of the present invention, it is not repeated herein.

The embodiment of the utility model provides a concrete connection mode of the passive components and parts that contain does not do specific restriction in the rewiring layer structure that provides, and technical personnel in the field can have the design according to the demand, have realized corresponding function.

As an alternative embodiment, as shown in fig. 8, the first passive component 6 is connected to the die pad 3 and the bump pad 4 through the rewiring 5, that is, one end of the first passive component 6 is connected to the die pad 3 through one rewiring 5, and the other end of the first passive component 6 is connected to the bump pad 4 through the other rewiring 5, which corresponds to the first passive component 6 being connected in series between the bump pad 4 and the die pad 3. The material used to form the first passive component 6 is a metal and an alloy with a certain resistivity, including but not limited to molybdenum, chromium, tungsten, and their alloys, and those skilled in the art can combine and select the resistivity of the material to make the first passive component 6 with a specific length and a specific cross-sectional area to obtain a desired resistance value.

Preferably, as shown in fig. 8, the first passive component 6 has an elongated structure and an extending direction thereof is perpendicular to the thickness direction of the substrate 1, the first passive component 6 needs to be designed into an elongated structure in some cases to meet the requirement of being used as a resistance component, and in order to fully use the characteristics of the redistribution layer structure, a relatively sufficient extending space can be obtained by the method that the extending direction of the first passive component 6 is perpendicular to the thickness direction of the substrate 1.

As an alternative embodiment, as shown in fig. 9, the first metal layer 701 of the second passive component 7 is connected to the chip pad 3 through one redistribution line 5, and the second metal layer 702 is connected to the bump pad 4 through another redistribution line 5, which corresponds to the first passive component 6 connected in series between the bump pad 4 and the chip pad 3. The material used for forming the first metal layer 701 and the second metal layer 702 is preferably a metal with excellent conductivity, including but not limited to one or more of copper, tungsten, aluminum, titanium, silver, gold, platinum, and nickel, and the forming process of the first metal layer 701 and the second metal layer 702 may be electroplating or sputtering, and planarization is achieved through chemical mechanical masking or etching. The material used to form the dielectric material layer 703 is preferably an insulating medium, including but not limited to SiON, HfO₂、TiO₂、HfZrO、HfSiNO、Ta₂O₅、ZrO₂、ZrSiO₂、Al₂O₃、SrTiO₃Or BaSrTiO, for example, the dielectric material layer 703 may be formed by alternately stacking hafnium oxide and aluminum oxide, and the dielectric material layer may be formed by chemical vapor deposition or sputtering.

As shown in fig. 4-7, the third passive component 8 provided in the embodiments of the present invention can be in various shapes and configurations to obtain different inductance values according to the application and usage requirements. For example, referring to fig. 4 and 5, the third passive component 8 includes a plurality of first inductors 801 distributed on different horizontal planes, each first inductor 801 is spirally disposed with a plurality of turns in the same plane so as to generate a corresponding inductance value, and the first inductors 801 between different planes are connected by a first wire 802. As another example, referring to fig. 6 and 7, the third passive component 8 includes a plurality of second inductors 803 distributed on different horizontal planes, each second inductor 803 is spirally arranged with one turn in the same plane, and the second inductors 803 between different planes are connected by a second wire 804. Preferably, the third passive component 8 further includes an inductance core 805 for adjusting characteristics of impedance and frequency, inductance value and frequency, etc. of the third passive component 8, and the material thereof includes, but is not limited to, ferrite, iron-nickel-molybdenum alloy, iron-silicon-aluminum alloy, and iron-nickel alloy.

Furthermore, the embodiment of the utility model provides a can connect through rewiring 5 between the first passive components and parts 6, the passive components and parts 7 of second and the passive components and parts 8 of third that contain in the rewiring layer structure that provide to the combination forms different forms's circuit structure, specific combination form can be a plurality of same kind of combination between the passive components and parts, also can be a plurality of different kinds of combination between the passive components and parts, technical personnel in the field can have the design according to the demand, have realized corresponding function.

In the redistribution layer structure shown in fig. 10, the first passive component 6 and the second passive component 7 are arranged in series between the die pad 3 and the bump pad 4, and the corresponding circuit structure is an RC series circuit shown in fig. 11, because the second passive component 7 exists in the circuit and direct current cannot flow, the first passive component 6 and the second passive component 7 both have a blocking effect on the current, and the total impedance of the first passive component 6 and the second passive component 7 is determined by the resistance of the first passive component 6 and the capacitive reactance of the second passive component 7.

In the redistribution layer structure shown in fig. 12, the first passive component 6 and the second passive component 7 are arranged in parallel between the chip pad 3 and the bump pad 4. The corresponding circuit structure is the RC parallel circuit shown in FIG. 13, and the circuit can pass through both DC signals and AC signals.

For another example, the third passive component 8 and the second passive component 7 may be connected in series or in parallel in a redistribution layer structure to form a resonant circuit structure, so as to implement a corresponding function, and one first passive component 6 and one second passive component 7 may be connected in parallel and then connected in series with another first passive component to form an RC series-parallel circuit, that is, the number of the first passive component 6, the second passive component 7, and the third passive component 8 is not specifically limited, and the combination manner is various.

The above is an exemplary description and illustration of the redistribution layer structure with passive components according to the embodiments of the present invention, and other configurations of the redistribution layer structure and methods for making the same will be known to those skilled in the art, and will not be described in detail herein, and those skilled in the art can understand and apply the description with reference to the prior art.

The utility model discloses still the corresponding semiconductor package structure that provides, it includes the rewiring layer structure with passive components and parts that the above-mentioned embodiment of this application provided. The semiconductor package structure disclosed in the embodiment of the present application includes the redistribution layer structure with the passive component provided in the above embodiment, so the semiconductor package structure with the redistribution layer structure also has all the above technical effects, and details are not repeated herein. Other configurations, principles, and methods of fabrication of semiconductor package structures will be known to those of ordinary skill in the art and will not be described in detail herein.

Some embodiments in this specification are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other.

The foregoing is merely a detailed description of the invention that enables those skilled in the art to understand or implement the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. The utility model provides a rewiring layer structure with passive components and parts, its characterized in that, includes range upon range of base (1) and dielectric layer (2), base (1) orientation one side of dielectric layer (2) is provided with a plurality of chip pad (3), one side that dielectric layer (2) deviate from base (1) is provided with a plurality of lug pad (4), be formed with rewiring (5) and have first passive components and parts (6) of predetermineeing resistance value in dielectric layer (2).

2. A redistribution layer structure according to claim 1, wherein the first passive component (6) has an elongated structure and an extending direction thereof is perpendicular to a thickness direction of the substrate (1).

3. The redistribution layer structure according to claim 1, wherein a second passive component (7) is disposed in the dielectric layer (2), the second passive component (7) includes a first metal layer (701), a second metal layer (702), and a dielectric material layer (703), the first metal layer (701) and the second metal layer (702) are disposed in parallel, at least some regions of the first metal layer and the second metal layer are opposite to each other, and the dielectric material layer (703) is filled between the first metal layer (701) and the second metal layer (702).

4. A redistribution layer structure according to claim 3 wherein the first metal layer (701) is connected to the chip pad (3) by a redistribution line (5), and the second metal layer (702) is connected to the bump pad (4) by a redistribution line (5); and/or

The first passive component (6) is connected with the chip bonding pad (3) and the bump bonding pad (4) through a rewiring (5).

5. A redistribution layer structure according to claim 4, wherein the first passive component (6) and the second passive component (7) are arranged in series between the chip pad (3) and the bump pad (4).

6. A redistribution layer structure according to claim 4, wherein the first passive component (6) and the second passive component (7) are arranged in parallel between the chip pad (3) and the bump pad (4).

7. The utility model provides a rewiring layer structure with passive components and parts, its characterized in that, includes range upon range of base (1) and dielectric layer (2), base (1) orientation one side of dielectric layer (2) is provided with a plurality of chip pad (3), one side that dielectric layer (2) deviate from base (1) is provided with a plurality of lug pad (4), be formed with rewiring (5) and third passive components and parts (8) in dielectric layer (2), third passive components and parts (8) are the coil of single-layer or multilayer setting.

8. The redistribution layer structure of claim 7 wherein a magnetic core is disposed within the coil.

9. The redistribution layer structure according to claim 7, wherein a second passive component (7) is formed in the dielectric layer (2) of the redistribution layer structure, the second passive component (7) comprises a first metal layer (701), a second metal layer (702) and a dielectric material layer (703), the first metal layer (701) and the second metal layer (702) are arranged in parallel, at least partial regions of the first metal layer and the second metal layer are opposite to each other, the dielectric material layer (703) is filled between the first metal layer (701) and the second metal layer (702), and the third passive component (8) and the second passive component (7) are arranged in parallel or in series.

10. A semiconductor package structure comprising the redistribution layer structure with passive components of any of claims 1-9.