JPH11126809A - Method for evaluating semiconductor substrate with p-n junction diode - Google Patents

Method for evaluating semiconductor substrate with p-n junction diode

Info

Publication number
JPH11126809A
JPH11126809A JP29298397A JP29298397A JPH11126809A JP H11126809 A JPH11126809 A JP H11126809A JP 29298397 A JP29298397 A JP 29298397A JP 29298397 A JP29298397 A JP 29298397A JP H11126809 A JPH11126809 A JP H11126809A
Authority
JP
Japan
Prior art keywords
semiconductor substrate
junction diode
substrate
junction
measured
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP29298397A
Other languages
Japanese (ja)
Inventor
Kazunori Ishizaka
和紀 石坂
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Steel Corp
Original Assignee
Nippon Steel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Steel Corp filed Critical Nippon Steel Corp
Priority to JP29298397A priority Critical patent/JPH11126809A/en
Publication of JPH11126809A publication Critical patent/JPH11126809A/en
Withdrawn legal-status Critical Current

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Abstract

PROBLEM TO BE SOLVED: To estimate the density of crystal defects contained in a semiconductor substrate by evaluating the leakage currents from the junctions of p-n junction diodes formed on the semiconductor substrate. SOLUTION: Reverse leak currents from many p-n junction diodes formed on the surface of a semiconductor substrate are measured, and when the measured value of the leakage current from one p-n junction diode exceeds a specific value, the element is discriminated as being a defective element and the density of crystal defects contained in the substrate is deduced by using the element areas and the thicknesses of the depletion layers of the measured diodes. In addition, the density of crystal defects which affect the leak currents and are contained in the substrate can be estimated by evaluating the defects contained in the depletion layers of the p-n junctions with high sensitivity, by increasing the leakage currents from the p-n junctions caused by the defects by forming a well area containing a dopant at a higher concentration in the surface layer of the substrate, deliberately diffusing heavy metal impurities in the substrate, or combining the formation of the well area and diffusion of the impurity.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、半導体デバイスに
用いられる半導体基板の結晶欠陥の評価に用いられる方
法に関する。特に、半導体基板に含まれる結晶欠陥の密
度を推定する方法を提供する。
The present invention relates to a method for evaluating crystal defects of a semiconductor substrate used for a semiconductor device. In particular, a method for estimating the density of crystal defects contained in a semiconductor substrate is provided.

【0002】[0002]

【従来技術】半導体基板にpn接合ダイオードを形成
し、リーク電流により、半導体基板の結晶を評価する方
法は、よく知られている。
2. Description of the Related Art A method of forming a pn junction diode on a semiconductor substrate and evaluating a crystal of the semiconductor substrate by a leak current is well known.

【0003】pn接合ダイオードに逆方向の電圧を印加
した場合に、逆方向にリーク電流が流れる。このリーク
電流値をライフタイムに変換することにより、半導体基
板のライフタイムを求めることができる(Physic
s and Technology of Semic
onductor Devices p172からp1
92 1967 by John Wiley & S
ons INC A.S.Grove)。
When a reverse voltage is applied to a pn junction diode, a leak current flows in the reverse direction. By converting this leak current value into a lifetime, the lifetime of the semiconductor substrate can be obtained (Physic).
s and Technology of Semiic
conductor Devices p172 to p1
92 1967 by John Wiley & S
ons INC A. S. Grove).

【0004】また、逆方向に印加する電圧を変化させる
ことにより空乏層幅が変化し、空乏層幅の変化に対する
リーク電流量の変化より、半導体基板の表面から内部に
かけて、ライフタイムの変化を知ることができる(特開
平4−67646など)。
Further, by changing the voltage applied in the reverse direction, the width of the depletion layer changes, and the change in the lifetime from the surface to the inside of the semiconductor substrate is known from the change in the amount of leak current with respect to the change in the depletion layer width. (For example, JP-A-4-67646).

【0005】半導体基板中の結晶欠陥密度を導出する方
法として、ライトエッチングに代表される選択エッチン
グ法によるエッチングピット観察法が知られている。
As a method for deriving the crystal defect density in a semiconductor substrate, an etching pit observation method by a selective etching method represented by light etching is known.

【0006】[0006]

【発明が解決しようとする課題】従来の半導体基板のp
n接合リーク電流の評価方法では、リーク電流により表
面層のライフタイムの値として、半導体基板の結晶欠陥
を評価することができる。しかしながら、このような測
定で得られるライフタイム値は、このリーク電流の元に
なっているpn接合の空乏層中に含まれる結晶欠陥の平
均的な評価にすぎず、半導体基板に含まれる結晶欠陥密
度を評価することはできない。
SUMMARY OF THE INVENTION Conventional semiconductor substrate p
In the method for evaluating an n-junction leak current, a crystal defect of a semiconductor substrate can be evaluated as a lifetime value of a surface layer by a leak current. However, the lifetime value obtained by such measurement is only an average evaluation of the crystal defects contained in the depletion layer of the pn junction, which is the source of the leak current, and the crystal defects contained in the semiconductor substrate Density cannot be evaluated.

【0007】また、半導体基板中の結晶欠陥密度を導出
する方法として、ライトエッチングに代表される選択エ
ッチング法によるエッチングピット観察法により欠陥密
度を求めることは可能であるが、これらのエッチングピ
ットとなる結晶欠陥は、必ずしもpn接合のリーク電流
を増加させるわけではないため、pn接合リーク電流に
影響を与える欠陥密度を求めることができない。
As a method for deriving the crystal defect density in a semiconductor substrate, it is possible to obtain the defect density by an etching pit observation method by a selective etching method represented by light etching. Since crystal defects do not necessarily increase the leakage current of the pn junction, it is not possible to determine the defect density that affects the pn junction leakage current.

【0008】[0008]

【課題を解決するための手段】本発明の目的は、下記す
る手段により達成される。 (1) 半導体基板の表面に形成した多数のpn接合ダ
イオードの逆方向のリーク電流を測定し、測定されたp
n接合リーク電流の値が、規定のリーク電流を越えた素
子を不良素子と判定し、測定したそれぞれのpn接合ダ
イオードの素子面積と空乏層厚から(1)式により、欠
陥密度を推定することを特徴とするものである。
The object of the present invention is achieved by the following means. (1) The leakage current in the reverse direction of many pn junction diodes formed on the surface of the semiconductor substrate was measured, and the measured p
An element having an n-junction leakage current value exceeding a specified leakage current is determined to be a defective element, and the defect density is estimated from the measured element area and depletion layer thickness of each pn junction diode according to equation (1). It is characterized by the following.

【0009】[0009]

【数2】 (Equation 2)

【0010】また、基板の表面層のドーパント濃度を上
げたウェル領域を形成したり、意図的に重金属不純物を
半導体基板内に拡散させたり、この両者を組み合わせた
りして、欠陥起因のpn接合リーク電流を増加させるこ
とにより、pn接合の空乏層中に含まれる欠陥を高感度
に評価できる。
In addition, a well region in which the dopant concentration of the surface layer of the substrate is increased, a heavy metal impurity is intentionally diffused into the semiconductor substrate, or a combination of the two is used to form a pn junction leak caused by a defect. By increasing the current, defects contained in the depletion layer of the pn junction can be evaluated with high sensitivity.

【0011】(2) 前記半導体基板の表面層におい
て、前記半導体基板の表面と同じ型のドーパントの濃度
を増加させたウェル領域を形成したことを特徴とするも
のである。
(2) A well region in which a concentration of a dopant of the same type as that of the surface of the semiconductor substrate is increased in a surface layer of the semiconductor substrate.

【0012】(3) 前記半導体基板の表面に形成され
るpn接合ダイオードにおいて、前記半導体基板の内部
に重金属不純物元素を拡散することを特徴とするもので
ある。
(3) In the pn junction diode formed on the surface of the semiconductor substrate, a heavy metal impurity element is diffused into the semiconductor substrate.

【0013】(4) 前記半導体基板の表面に形成され
るpn接合ダイオードにおいて、前記半導体基板の内部
に重金属不純物元素を拡散し、かつ、前記半導体基板の
表面と同じ型のドーパントの濃度を増加させたウェル領
域を形成したことを特徴とするものである。
(4) In a pn junction diode formed on the surface of the semiconductor substrate, a heavy metal impurity element is diffused into the semiconductor substrate, and the concentration of a dopant of the same type as the surface of the semiconductor substrate is increased. In which a well region is formed.

【0014】[0014]

【発明の実施の形態】半導体基板表面にpn接合ダイオ
ードを形成し、pn接合の逆方向のリーク電流を測定し
た場合に、pn接合の空乏層中に電気的に活性な結晶欠
陥が含まれると著しくリーク電流が増加する。pn接合
の空乏層中に結晶欠陥が含まれない場合のリーク電流値
と比較して、適当な判定電流値を設定することにより、
評価しているpn接合の空乏層中の結晶欠陥の有無を判
定することができる。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS When a pn junction diode is formed on the surface of a semiconductor substrate and a leakage current in a direction opposite to that of the pn junction is measured, it is determined that an electrically active crystal defect is contained in a depletion layer of the pn junction. The leakage current increases significantly. By setting an appropriate determination current value in comparison with a leakage current value when no crystal defect is included in the depletion layer of the pn junction,
The presence or absence of a crystal defect in the depletion layer of the evaluated pn junction can be determined.

【0015】欠陥が存在しない場合のリーク電流値は、
素子面積に比例し、およそ10-10A/cm2 であるこ
とより、判定電流値としては、その10倍程度が好まし
く、10-9A/cm2 である。また、測定する素子面積
を小さくして、素子の無欠陥領域のリーク電流値を小さ
くすることにより、欠陥を高感度に評価する事ができ
る。そして、結晶欠陥がpn接合の空乏層中に含まれる
確率を結晶欠陥分布としてポアソン分布と仮定すること
により、次式の関係が成り立つ。
When no defect exists, the leakage current value is
Since it is proportional to the element area and is about 10 −10 A / cm 2 , the judgment current value is preferably about 10 times that, and is preferably 10 −9 A / cm 2 . Further, the defect can be evaluated with high sensitivity by reducing the element area to be measured and the leak current value in the defect-free region of the element. By assuming that the probability that a crystal defect is included in the depletion layer of the pn junction is a Poisson distribution as a crystal defect distribution, the following relationship is established.

【0016】[0016]

【数3】 (Equation 3)

【0017】この式を変形すると、By transforming this equation,

【0018】[0018]

【数4】 (Equation 4)

【0019】となり、欠陥密度を導出することができ
る。
Thus, the defect density can be derived.

【0020】なお、空乏層厚は、測定時の素子の静電容
量より容易に求めることができ、静電容量と空乏層厚
は、以下の関係式になることが知られている。
The depletion layer thickness can be easily obtained from the capacitance of the element at the time of measurement, and it is known that the capacitance and the depletion layer thickness have the following relational expression.

【0021】[0021]

【数5】 (Equation 5)

【0022】この評価は、評価素子の面積依存性や空乏
層の厚さ依存性より、精度を上げることができる。
The accuracy of this evaluation can be improved based on the area dependence of the evaluation element and the thickness dependence of the depletion layer.

【0023】pn接合ダイオードのリーク電流により評
価できる結晶欠陥は、電気的に活性な状態にある欠陥に
限られるが、結晶欠陥の電気的活性度を上げることによ
り、高感度に評価する事ができる。結晶欠陥の電気的活
性度を上げるために、意図的に半導体基板表面層のドー
パント濃度を上げたウェル構造を与えることによりpn
接合の空乏層にかかる電界強度をあげて、欠陥の電気的
活性度を上げる事ができる。
The crystal defects that can be evaluated by the leak current of the pn junction diode are limited to defects in an electrically active state, but can be evaluated with high sensitivity by increasing the electrical activity of the crystal defects. . In order to increase the electrical activity of crystal defects, pn is provided by intentionally providing a well structure in which the dopant concentration of the semiconductor substrate surface layer is increased.
By increasing the electric field strength applied to the depletion layer of the junction, the electrical activity of defects can be increased.

【0024】ウェル濃度としては、1016〜1018/c
3 が好ましい。また、Ti、V、Cr、Mn、Fe、
Co、Ni、Cu、W、Mo、Au、Ag、Ptなどの
重金属不純物を半導体基板内部に拡散固溶させ、結晶欠
陥にゲッタリングさせることにより、リーク電流を増加
させる事ができる。汚染量は、1010/cm3 から拡散
温度の固溶限までが好ましい。また、基板表面層のドー
パント濃度を上げる処理と重金属不純物を拡散固溶させ
る処理を組み合わせると、さらに高感度の評価ができる
が、その際、どちらの処理を先に行ってもかまわない。
The well concentration is 10 16 to 10 18 / c
m 3 is preferred. Also, Ti, V, Cr, Mn, Fe,
A heavy metal impurity such as Co, Ni, Cu, W, Mo, Au, Ag, or Pt is diffused and solid-dissolved in the semiconductor substrate and gettered to a crystal defect, whereby a leak current can be increased. The amount of contamination is preferably from 10 10 / cm 3 to the solid solubility limit of the diffusion temperature. Further, by combining the treatment for increasing the dopant concentration of the substrate surface layer and the treatment for diffusing and dissolving heavy metal impurities, evaluation with higher sensitivity can be performed. In that case, either treatment may be performed first.

【0025】この評価は、基板がp型でもn型でも同様
の評価が可能であることはいうまでもない。
It goes without saying that the same evaluation can be made regardless of whether the substrate is p-type or n-type.

【0026】[0026]

【実施例】【Example】

《実施例1》p型、6インチ、基板の抵抗率10Ωcm
のシリコンウェハに、pn接合ダイオードを形成し、リ
ーク電流の測定を行った。素子面積は10mm2 で、評
価素子数は100個である。リーク電流判定時の空乏層
厚は5μmである。リーク電流量の判定値は、1×10
-9A/cm2 とした。不良素子数は、40個であった。
(1)式より、半導体基板中に含まれる欠陥密度は、
1.0×104 個/cm3 である。
<< Example 1 >> p-type, 6 inches, substrate resistivity 10 Ωcm
Then, a pn junction diode was formed on the silicon wafer, and the leakage current was measured. The element area is 10 mm 2 and the number of evaluation elements is 100. The depletion layer thickness at the time of leak current determination is 5 μm. The judgment value of the leak current amount is 1 × 10
-9 A / cm 2 . The number of defective elements was 40.
From equation (1), the defect density contained in the semiconductor substrate is:
1.0 × 10 4 / cm 3 .

【0027】《実施例2》p型6インチ、基板の抵抗率
10Ωcmのシリコンウェハに、pn接合ダイオードを
形成し、リーク電流の測定を行った。素子面積は30m
2 で、評価素子数は100個である。リーク電流判定
時の空乏層厚は5μmである。リーク電流量の判定値
は、1×10-9A/cm2 とした。不良素子数は、30
個であった。(1)式より、半導体基板中に含まれる欠
陥密度は、2.4×103 個/cm3である。
Example 2 A pn junction diode was formed on a 6-inch p-type silicon wafer having a substrate resistivity of 10 Ωcm, and leakage current was measured. Element area is 30m
With m 2 , the number of evaluation elements is 100. The depletion layer thickness at the time of leak current determination is 5 μm. The determination value of the amount of leak current was 1 × 10 −9 A / cm 2 . The number of defective elements is 30
Was individual. From equation (1), the density of defects contained in the semiconductor substrate is 2.4 × 10 3 / cm 3 .

【0028】《実施例3》p型6インチ、基板の抵抗率
10Ωcmのシリコンウェハに、ウェル濃度を5×10
16/cm3 としたpn接合ダイオードを形成し、リーク
電流の測定を行った。素子面積は1mm2 で、評価素子
数は100個である。リーク電流判定時の空乏層厚は
0.5μmである。リーク電流量の判定値は、1×10
-9A/cm2とした。不良素子数は、40個であった。
(1)式より、半導体基板中に含まれる欠陥密度は、
1.0×106 個/cm3 である。
<< Embodiment 3 >> A silicon wafer having a p-type thickness of 6 inches and a substrate resistivity of 10 Ωcm having a well concentration of 5 × 10
A pn junction diode of 16 / cm 3 was formed, and the leakage current was measured. The element area is 1 mm 2 , and the number of evaluation elements is 100. The thickness of the depletion layer at the time of determining the leak current is 0.5 μm. The judgment value of the leak current amount is 1 × 10
-9 A / cm 2 . The number of defective elements was 40.
From equation (1), the defect density contained in the semiconductor substrate is:
1.0 × 10 6 / cm 3 .

【0029】《実施例4》p型6インチ、基板の抵抗率
10Ωcmのシリコンウェハに、Cuを1013/cm3
を固溶させたpn接合ダイオードを形成し、リーク電流
の測定を行った。素子面積は1mm2 で、評価素子数は
100個である。リーク電流判定時の空乏層厚は5μm
である。リーク電流量の判定値は、1×10-9A/cm
2 とした。不良素子数は、40個であった。(1)式よ
り、半導体基板中に含まれる欠陥密度は、1.0×10
5 個/cm3 である。
Example 4 A silicon wafer having a p-type thickness of 6 inches and a substrate resistivity of 10 Ωcm was coated with Cu at 10 13 / cm 3.
Was formed into a pn junction diode, and the leakage current was measured. The element area is 1 mm 2 , and the number of evaluation elements is 100. Depletion layer thickness at the time of leak current judgment is 5 μm
It is. The judgment value of the leak current amount is 1 × 10 −9 A / cm
And 2 . The number of defective elements was 40. From equation (1), the defect density contained in the semiconductor substrate is 1.0 × 10
5 pieces / cm 3 .

【0030】《実施例5》p型6インチ、基板の抵抗率
10Ωcmのシリコンウェハに、Niを1013/cm3
固溶させ、ウェル濃度を5×1016/cm3 としたpn
接合ダイオードを形成し、リーク電流の測定を行った。
素子面積は0.01mm2 で、評価素子数は100個で
ある。リーク電流判定時の空乏層厚は0.5μmであ
る。リーク電流量の判定値は、1×10-3A/cm2
した。不良素子数は、40個であった。(1)式より、
半導体基板中に含まれる欠陥密度は、1.0×108
/cm3 である。
Example 5 Ni was coated on a silicon wafer having a p-type thickness of 6 inches and a substrate resistivity of 10 Ωcm at 10 13 / cm 3.
Pn with a solid solution having a well concentration of 5 × 10 16 / cm 3
A junction diode was formed, and the leakage current was measured.
The element area is 0.01 mm 2 and the number of evaluation elements is 100. The thickness of the depletion layer at the time of determining the leak current is 0.5 μm. The determination value of the amount of leak current was 1 × 10 −3 A / cm 2 . The number of defective elements was 40. From equation (1),
The density of defects contained in the semiconductor substrate is 1.0 × 10 8 defects / cm 3 .

【0031】[0031]

【発明の効果】本発明により、半導体基板に含まれるリ
ーク電流に影響を及ぼす結晶欠陥の密度を推定すること
ができ、この結果と基板の履歴からpn接合リークに影
響を与える欠陥の少ない半導体基板を作るための指針を
得ることができる。
According to the present invention, it is possible to estimate the density of crystal defects affecting the leakage current contained in the semiconductor substrate, and from the result and the history of the substrate, to reduce the number of defects affecting the pn junction leakage. You can get guidelines for making

Claims (4)

【特許請求の範囲】[Claims] 【請求項1】 半導体基板の表面に形成した多数のpn
接合ダイオードの逆方向のリーク電流を測定し、測定さ
れたpn接合リーク電流の値が、規定のリーク電流を越
えた素子を不良素子と判定し、測定したそれぞれのpn
接合ダイオードの素子面積と空乏層厚から(1)式によ
り、欠陥密度を推定することを特徴とするpn接合ダイ
オードによる半導体基板の評価方法。 【数1】
A plurality of pns formed on a surface of a semiconductor substrate;
The leakage current in the reverse direction of the junction diode is measured, and the element whose measured pn junction leakage current exceeds a specified leakage current is determined to be a defective element, and each of the measured pn
A method of evaluating a semiconductor substrate using a pn junction diode, comprising estimating a defect density from the element area of the junction diode and the thickness of a depletion layer by the equation (1). (Equation 1)
【請求項2】 前記半導体基板の表面層において、前記
半導体基板の表面と同じ型のドーパントの濃度を増加さ
せたウェル領域を形成したことを特徴とする請求項1記
載のpn接合ダイオードによる半導体基板の評価方法。
2. The semiconductor substrate according to claim 1, wherein a well region in which a concentration of a dopant of the same type as that of the surface of the semiconductor substrate is increased is formed in a surface layer of the semiconductor substrate. Evaluation method.
【請求項3】 前記半導体基板の表面に形成されるpn
接合ダイオードにおいて、前記半導体基板の内部に重金
属不純物元素を拡散することを特徴とする請求項1記載
のpn接合ダイオードによる半導体基板の評価方法。
3. A pn formed on a surface of the semiconductor substrate.
2. The method for evaluating a semiconductor substrate using a pn junction diode according to claim 1, wherein a heavy metal impurity element is diffused into the semiconductor substrate in the junction diode.
【請求項4】 前記半導体基板の表面に形成されるpn
接合ダイオードにおいて、前記半導体基板の内部に重金
属不純物元素を拡散し、かつ、前記半導体基板の表面と
同じ型のドーパントの濃度を増加させたウェル領域を形
成したことを特徴とする請求項1記載のpn接合ダイオ
ードによる半導体基板の評価方法。
4. A pn formed on a surface of the semiconductor substrate
2. The junction diode according to claim 1, wherein a heavy metal impurity element is diffused into the semiconductor substrate, and a well region in which the concentration of a dopant of the same type as that of the surface of the semiconductor substrate is increased is formed. A method for evaluating a semiconductor substrate using a pn junction diode.
JP29298397A 1997-10-24 1997-10-24 Method for evaluating semiconductor substrate with p-n junction diode Withdrawn JPH11126809A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101929982A (en) * 2009-06-19 2010-12-29 中芯国际集成电路制造(上海)有限公司 Method for detecting integrity of gate oxide
JP2017005015A (en) * 2015-06-05 2017-01-05 信越半導体株式会社 Evaluation method for semiconductor substrate

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101929982A (en) * 2009-06-19 2010-12-29 中芯国际集成电路制造(上海)有限公司 Method for detecting integrity of gate oxide
JP2017005015A (en) * 2015-06-05 2017-01-05 信越半導体株式会社 Evaluation method for semiconductor substrate

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