JPH11126493A - Non-volatile semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prolong the operating life of a memory cell for erasing the charge accumulated in a floating gate by using Fowler Nordheim tunnel current by lowering the judging level on whether 0 or 1 when the number of times of data rewriting exceeds a preset number of times. SOLUTION: By using the Fowler Nordheim tunnel current flowing from the control gate CG into the floating gate FG, the charge accumulated in the floating gate FG is extracted to erase data. A control gate core circuit 132 counts the number of times of data rewriting and when the count value exceeds a prescribed value, it stores this situation to the memory cell 101. At the time of the reading mode after this, the control core circuit 132 changes the cell current value Ir of the reference cell as the discrimination level which discriminates whether the memory cell in the write condition or the erase condition to a lower value. Thus, the operating life of the memory cell and the flash EEPROM using it is prolonged.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile semiconductor memory, and more particularly, to erasing electric charges (electrons) accumulated in a floating gate of a flash EEPROM or the like by using a Fowler-Nordheim tunnel current. The present invention relates to a nonvolatile semiconductor memory for erasing data.

[0002]

2. Description of the Related Art In recent years, FRAM (Ferro-electric Random
Access Memory), EPROM (Erasable and Programma)
ble Read Only Memory), EEPROM (Electrical Era)
2. Description of the Related Art Non-volatile semiconductor memories such as sable and programmable read only memories (DRAMs) have attracted attention. EPROM and EEP
In the ROM, data is stored by storing charge in a floating gate and detecting a change in threshold voltage due to the presence or absence of the charge by a control gate. The EEPROM includes a flash EEPROM that erases data in the entire memory chip or divides a memory cell array into arbitrary blocks and erases data in each block unit.

[0003] Memory cells constituting a flash EPROM are roughly classified into a split gate type and a stacked gate type. (Split gate type) A flash EEPROM of a split gate type is disclosed in USP 5,029,130 (G11C 11/40).
Is disclosed.

FIG. 3 shows a sectional structure of a split gate type memory cell 101 described in the publication. An N-type source S and a drain D are formed on a P-type single crystal silicon substrate 102. A floating gate FG is formed on a channel CH sandwiched between a source S and a drain D via a first insulating film 103. A control gate CG is formed on the floating gate FG via a second insulating film 104 as a tunnel oxide film. A part of the control gate CG is arranged on the channel via the first insulating film 103, and forms a selection gate 105.

FIG. 4 shows a flash EEP using a split gate type memory cell 101 described in the publication.
1 shows the overall configuration of a ROM 121. Memory cell array 12
Reference numeral 2 denotes a configuration in which a plurality of memory cells 101 are arranged on a matrix. The control gates CG of the memory cells 101 arranged in the row direction are connected to common word lines WLa to WLz. The drains D of the memory cells 101 arranged in the column direction are connected to common bit lines BLa to BL. The sources S of all the memory cells 101 are connected to a common source line SL,
The common source line SL is grounded.

Each word line WLa-WLz is connected to a row decoder 123, and each bit line BLa-BLz is connected to a column decoder 124. The row address and column address specified from outside are stored in the address pad 1
25. The row address and the column address are transmitted from the address pad 125 to the address buffer 12.
6 to the address latch 127. Of the addresses latched by the address latch 127, the row address is transferred to the row decoder 123, and the column address is transferred to the column decoder 124.

The row decoder 123 selects one word line WLa-WLz corresponding to the row address, and controls the potential of the selected word line WL according to each operation mode, as described later. . Column decoder 124
Are the bit lines BLa-BL corresponding to the column address.
Lz is selected, and the potential of the selected bit line BL is controlled according to each operation mode, as described later.

Data specified externally is input to data pad 128. The data is stored in data pad 1
28 through the input buffer 129, the column decoder 1
24. The column decoder 124 controls the potentials of the bit lines BLa to BLz selected as described above in accordance with the data, as described later. Data read from any memory cell 101 is stored in bit line BLa
ＢＬBLz to the sense amplifier group 130 via the column decoder 124. The sense amplifier group 130 includes several sense amplifiers (not shown). The column decoder 124 is connected to the selected bit lines BLa to BLz.
And each sense amplifier. As will be described later, the data determined by the sense amplifier group 130 is output to the output buffer 13.
1 to the outside via the data pad 128.

The above circuits (123, 124, 12
6, 127, 129, 130, 131) are controlled by the control core circuit 132. Next, flash E
Each operation mode (erasing mode, writing mode, reading mode) of the EPROM 121 will be described. In any of the operation modes, the potential of the common source line SL is maintained at the ground level (= 0 V).

(A) Erasing Mode In the erasing mode, the potentials of all the bit lines BLa to BLz are held at the ground level. For example, 14V is supplied to the selected word line WLm, and the other word lines (non-selected word lines) WLa to WLl and WLn to
The potential of WLz is set to the ground level. Therefore, the control gate CG of each memory cell 101 connected to the selected word line WLm is raised to 14V.

When the capacitance between the floating gate FG and the drain D is compared with the capacitance between the control gate CG and the floating gate FG, the former is overwhelmingly larger.
Therefore, the control gate CG is 14 V and the drain D is 0 V
In the case of, a high electric field is generated between the control gate CG and the floating gate FG. As a result, the Fowler-Nordheim Tunnel Current, hereinafter,
It is called FN tunnel current. ) Flows and the floating gate FG
Are extracted to the control gate CG side (see the arrow A in FIG. 3), and the data stored in the memory cell 101 is erased.

This erase operation is performed by selecting the selected word line WL.
This is performed for all the memory cells 101 connected to m. Note that by simultaneously selecting a plurality of word lines WLa to WLz, an erase operation can be performed on all the memory cells 101 connected to each word line. The erasing operation of dividing the memory cell array 122 into arbitrary blocks for each of a plurality of sets of word lines WLa to WLz and erasing data in each block is called block erasing.

(B) Write mode In the write mode, the selected memory cell 101
For example, 1 V is supplied to the word line WLm connected to the control gate CG, and the potentials of the other word lines (non-selected word lines) WLa to WLl and WLn to WLz are set to the ground level. Selected memory cell 10
1 bit line BLm connected to the drain D,
For example, 12 V is supplied, and the potentials of the other bit lines (non-selected bit lines) BLa to BLl and BLn to BLz are set to the ground level.

The threshold voltage Vth of the memory cell 101 is, for example, 0.5V. Therefore, in the selected memory cell 101, the control gate CG becomes close to the threshold voltage Vth, and the electrons in the source S move into the weakly inverted channel CH. On the other hand, since 12 V is applied to the drain D, the potential of the floating gate FG is raised by the coupling between the drain D and the floating gate FG via the capacitance. Therefore, a high electric field is generated between the control gate CG and the floating gate FG. Therefore, channel CH
The electrons inside are accelerated and are injected into the floating gate FG as hot electrons. As a result, charges are accumulated in the floating gate FG of the selected memory cell 101, and 1-bit data is written and stored.

This write operation is different from the erase operation.
This can be performed for each selected memory cell 101. (C) Read mode In the read mode, the selected memory cell 101
For example, 5 V is supplied to the word line WLm connected to the control gate CG, and the potentials of the other word lines (non-selected word lines) WLa to WL1 and WLn to WLz are set to the ground level. Selected memory cell 10
For example, 2.5 V is supplied to the bit line BLm connected to one drain D, and the other bit lines (non-selected bit lines) BLa to BLl and BLn to BLz are set to the ground level.

As described above, since electrons are extracted from the floating gate FG of the memory cell 101 in the erased state, the floating gate FG is positively charged. Further, since electrons are injected into the floating gate FG of the memory cell 101 in the written state, the floating gate FG
Is negatively charged. Therefore, the channel CH immediately below the floating gate FG of the memory cell 101 in the erased state is on, and the channel CH immediately below the floating gate FG of the memory cell 101 in the written state is off. Therefore, when 5 V is applied to the control gate CG, the current (cell current) flowing from the drain D to the source S is larger in the erased memory cell 101 than in the written memory cell 101.

The value of the data stored in the memory cell 101 can be read by determining the magnitude of the cell current between the memory cells 101 by each sense amplifier in the sense amplifier group 130. For example, reading is performed with the data value of the memory cell 101 in the erased state being “1” and the data value of the memory cell 101 in the written state being “0”. That is, each memory cell 101 can store two values of the data value “1” in the erased state and the data value “0” in the written state.

This read operation is different from the erase operation.
This can be performed for each selected memory cell 101. Incidentally, in the split gate memory cell 101, a flash EEPROM in which the source S is called a drain and the drain D is called a source is WO92 / 18980.
(G11C 13/00).

(Stacked Gate Type) FIG. 5 shows a sectional structure of a stacked gate type memory cell 201. An N-type source S and a drain D are formed on a P-type single crystal silicon substrate. A first insulating film 20 as a tunnel oxide film is formed on a channel CH sandwiched between the source S and the drain D.
3, a floating gate FG is formed. The control gate CG is provided on the floating gate FG via the second insulating film 204.
Are formed. The floating gate FG and the control gate CG are stacked without shifting from each other. Therefore,
The source S and the drain D have a symmetric structure with respect to each of the gates FG and CG and the channel CH.

FIG. 6 shows a stacked gate type memory cell 2
1 shows the overall configuration of a flash EEPROM 221 using the same. In the flash EEPROM 221, FIG.
Are different from the flash EEPROM 121 using the split gate type memory cell 101 shown in FIG.

(1) In the memory cell array 122, a plurality of memory cells 201 are arranged in a matrix. (2) The sources S of the memory cells 201 arranged in the column direction are connected to common bit lines BLa to BLz. (3) The drains D of all the memory cells 201 are connected to a common drain line DL. The common drain line DL is connected to a common drain line bias circuit 222.
The common drain line bias circuit 222 controls the potential of the common drain line DL according to each operation mode, as described later. The operation of the common drain line bias circuit 222 is controlled by the control core circuit 132.

In this specification, the names of the source S and the drain D in the split gate memory cell 101 and the stacked gate memory cell 201 are determined based on the read operation, and the higher potential in the read operation is determined by the drain. , The lower potential is referred to as the source. In the writing operation and the erasing operation, the names of the source S and the drain D are the same as those in the reading operation.

Next, each operation mode (erase mode, write mode, read mode) of the flash EEPROM 221 will be described. (A) Erasing Mode In the erasing mode, all the bit lines BLa to BLz are set to the open state, and the potentials of all the word lines WLm are set to the ground level. Common drain line bias circuit 2
22 applies, for example, 12 V to the drains D of all the memory cells 201 via the common drain line DL.

As a result, an FN tunnel current flows, electrons in the floating gate FG are drawn to the drain D side (see the arrow B in FIG. 5), and the data described in the memory cell 201 is erased. . This erase operation is performed for all the memory cells 20 connected to the selected word line WLm.
1 is performed.

By simultaneously selecting a plurality of word lines WLa to WLz, an erase operation (block erase) can be performed on all the memory cells 201 connected to each word line. (B) Write mode In the write mode, the selected memory cell 201
For example, 12 V is supplied to the word line WLm connected to the control gate CG, and the potentials of the other word lines (non-selected word lines) WLa to WL1 and WLn to WLz are set to the ground level. Selected memory cell 2
01 to the bit line BLm connected to the source S
For example, 5 V is supplied, and the potentials of the other bit lines (non-selected bit lines) BLa to BLl and BLn to BLz are set to the ground level. Common drain line bias circuit 2
Reference numeral 22 holds the drains D of all the memory cells 201 at the ground level via the common drain line DL.

Then, the potential of the floating gate FG is raised by the coupling from the control gate CG, and hot electrons generated near the source S are injected into the floating gate FG. As a result, the selected memory cell 2
In the floating gate FG 01, charges are accumulated, and 1-bit data is written and stored. (C) Read mode In the read mode, the selected memory cell 201
For example, 5 V is supplied to the word line WLm connected to the control gate CG, and the potentials of the other word lines (non-selected word lines) WLa to WL1 and WLn to WLz are set to the ground level. All bit lines BLa-B
The potential of Lz is set to the ground level. The common drain line bias circuit 222 is connected to the common drain line
For example, 5 V is applied to the drains D of all the memory cells 201.

As a result, as in the case of the split gate memory cell 101, the current (cell current) flowing from the drain D to the source S is larger in the erased memory cell 201 than in the written memory cell 201. Become. Therefore, each memory cell 201 can store two values of the data value “1” in the erased state and the data value “0” in the written state.

As described above, in the erase mode in the split gate memory cell 101, electrons in the floating gate FG are drawn out to the control gate CG side as shown by the arrow A in FIG. Data is erased. At this time, since electrons accelerated by the high electric field pass through the silicon oxide film 104, a large stress is applied to the silicon oxide film 104.

Therefore, when the write operation and the erase operation are repeated, an electron trap is formed in the silicon oxide film 104 due to the stress applied to the silicon oxide film 104 during the erase operation. This electron trap becomes a barrier,
The transfer of electrons from the floating gate FG to the control gate CG is hindered. Therefore, as the number of times of writing and the number of times of erasing (that is, the number of times of rewriting of data) increase, the number of electron traps in the silicon oxide film 104 also increases, so that electrons in the floating gate FG cannot be sufficiently extracted.

Therefore, as shown in FIG. 7, the cell current in the read mode increases as the number of data rewrites increases.
While w hardly changes, the cell current Ii of the memory cell 101 in the erased state decreases. As a result, the difference between the cell current Iw of the memory cell 101 in the written state and the cell current Ii of the memory cell 101 in the erased state is reduced. When the cell current Ii of the memory cell 101 in the erased state becomes smaller than the predetermined cell current value Ir1 of the reference cell, the magnitude of the cell current between the memory cell 101 in the written state and the memory cell 101 in the erased state becomes smaller. It cannot be determined. That is, it becomes impossible to read the value of the data stored in the memory cell 101, and the function as the memory cell is not performed. The cell current Ir1
Is defined by the characteristics of each sense amplifier in the sense amplifier group 130, and can be said to be the lower limit of the cell current Ii of the memory cell 101 in the erased state.

The stacked gate type memory cell 20
In the erase mode 1, the electrons in the floating gate FG are drawn out to the drain region D side as shown by the arrow B in FIG. 5, and the data stored in the memory cell 201 is erased. At this time, since electrons accelerated by the high electric field pass through the silicon oxide film 203, a large stress is applied to the silicon oxide film 203.

Therefore, when the write operation and the erase operation are repeated, an electron trap is formed in the silicon oxide film 203 by the stress applied to the silicon oxide film 203 during the erase operation. This electron trap becomes a barrier,
The transfer of electrons from the floating gate FG to the drain region D is inhibited. Therefore, as the number of times of writing and the number of times of erasing (that is, the number of times of rewriting of data) increase, the number of electron traps in the silicon oxide film 203 also increases, and the electrons in the floating gate FG are sufficiently extracted within a preset erasing time. Can not be done.

Therefore, as shown in FIG. 8, the cell current in the read mode increases as the number of times of data rewriting increases.
While w does not substantially change, the cell current Ii of the memory cell 201 in the erased state decreases. As a result, the difference between the cell current Iw of the memory cell 201 in the written state and the cell current Ii of the memory cell 201 in the erased state is reduced. When the cell current Ii of the memory cell 201 in the erased state becomes smaller than the predetermined cell current value Ir1 of the reference cell, the magnitude of the cell current between the memory cell 201 in the written state and the memory cell 201 in the erased state becomes smaller. It cannot be determined. That is, it becomes impossible to read the value of the data stored in the memory cell 201, and the function as the memory cell is not performed. The cell current Ir1
Is defined by the characteristics of each sense amplifier in the sense amplifier group 130 and can be said to be the lower limit of the cell current Ii of the memory cell 201 in the erased state.

Conventionally, as shown in FIGS. 7 and 8, the cell current Ir at the time of erasing the reference cell has an initial value of 100 μm.
The point that dropped to 30 μA (Ir1), which is 30% of A, was taken as the limit point of the number of times of data rewriting, and the operating life of the memory cell.

[0035]

In the prior art described above, the memory cell 101 or the memory cell 201 is not used.
The problem is that the number of electron traps in the silicon oxide film 104 or the silicon oxide film 203 increases with an increase in the number of times of rewriting data, so that the operating life of the memory cell 101 or the memory cell 201 is limited. .
Then, the memory cell 101 or the memory cell 201
The limited operating life of the flash EE
PROM 121 or flash EEPROM 221
Operating life is also limited.

Accordingly, the present invention extends the operating life of a memory cell for erasing data using an FN tunnel current, and provides a long-life nonvolatile semiconductor memory using the memory cell.

[0037]

The nonvolatile semiconductor memory of the present invention uses the Fowler-Nordheim tunnel current flowing from the control gate CG to the floating gate FG to charge (electrons) accumulated in the floating gate FG. A counter for counting the number of data rewrites of a plurality of memory cells, a first memory unit for storing a preset number of rewrites of a plurality of data of the memory cells, and the counter A second memory unit for storing identification data for identifying that the counted number of times of data rewriting of the predetermined memory cell has reached a plurality of data rewriting times stored in the first memory unit; The cell current value Ir as a determination level for determining the write state or the erase state of the memory cell based on the It is characterized in that it has a that control circuit.

Further, the nonvolatile semiconductor memory of the present invention comprises:
The data is erased by extracting charges (electrons) stored in the floating gate FG by using a Fowler-Nordheim tunnel current flowing from the drain D to the floating gate FG, and counts the number of times of data rewriting of the memory cell. A counter, a first memory unit that stores a preset number of times of data rewriting of the memory cell,
A second memory unit that stores identification data for identifying that the number of times of data rewriting of the predetermined memory cell counted by the counter has reached the plurality of times of data rewriting stored in the first memory unit; A control circuit for changing a cell current value Ir as a judgment level for judging a write state or an erase state of the memory cell based on the identification data.

[0039]

Embodiments of the present invention will be described below with reference to the drawings. (First Embodiment) A first embodiment of the present invention will be described with reference to the drawings. In the first embodiment, the structure of the split gate memory cell 101 and the overall structure of the flash EEPROM 121 using the same are the same as those of the conventional embodiment shown in FIGS.

FIG. 1 shows the relationship between the number of data rewrites and the cell current in the read mode and the voltage Vg of the control gate CG in the erase mode. The erase mode, the write mode, and the read mode in the present embodiment are the same as those in the conventional mode. In this embodiment,
The difference from the conventional embodiment is as follows.

[1] The control core circuit 132 counts the number of times of data rewriting by a counter (not shown). If the counted value exceeds a predetermined value T1, the control core circuit 132 stores it in the memory cell 101, and thereafter, In the read mode, the cell current value Ir of the reference cell as the determination level for determining the write state or the erase state of the memory cell is set to Ir.
Control is performed to change from 1 to Ir2.

The predetermined value T1 is the cell current Ii of the memory cell 101 in the erased state when a certain erase voltage is applied.
Corresponds to the number of data rewrites at the time point when a predetermined cell current value Ir1 is reached. That is, in order to obtain the predetermined value T1 when a desired erase voltage is applied, the decrease in the cell current Ii with respect to the number of data rewrites for a large number of memory cells 101 may be actually measured. Until (the first number of times of data rewriting to the predetermined value T1), the cell current value Ir1 (for example, the cell current of the memory cell in the erased state is an initial value) as a determination level for determining the write state or the erase state of the memory cell 100
After a predetermined value T1, a cell current value Ir2 (for example, the cell current of the memory cell in the erased state is set to the initial value) is set as a determination level for determining the write state or the erase state of the memory cell after the predetermined value T1. 20 of 100 μA
%, Which is 20 μA).

[2-a] Erase Mode In the erase mode, the row decoder 123 supplies a desired voltage Vg (for example, 14 V) to the selected word line WLm. Therefore, the control gate CG of each memory cell 101 connected to the selected word line WLm
V lifted.

At this time, the column decoder 124 holds the potentials of all the bit lines BLa to BLz at the ground level, as in the conventional embodiment. Therefore, the potential of the drain region D becomes 0 V as in the conventional case. As a result, the control gate CG becomes 14 V and the drain D becomes 0 V, and a high electric field is generated between the control gate CG and the floating gate FG. As a result, an FN tunnel current flows, electrons in the floating gate FG are pulled out to the control gate CG side (see arrow A in FIG. 3), and the data stored in the memory cell 101 is erased.

[2-b] Write Mode In the write mode, the selected memory cell 101
For example, 1 V is supplied to the word line WLm connected to the control gate CG, and the potentials of the other word lines (non-selected word lines) WLa to WLl and WLn to WLz are set to the ground level. Selected memory cell 10
1 bit line BLm connected to the drain D,
For example, 12 V is supplied, and the potentials of the other bit lines (non-selected bit lines) BLa to BLl and BLn to BLz are set to the ground level.

As a result, the selected memory cell 101
In this case, the control gate CG becomes close to the threshold voltage Vth, and electrons in the source S move into the weakly inverted channel CH. On the other hand, since 12 V is applied to the drain D, the potential of the floating gate FG is raised by the coupling between the drain D and the floating gate FG via the capacitance,
A high electric field is generated between the control gate CG and the floating gate FG. Therefore, the electrons in the channel CH are accelerated, become hot electrons, and are injected into the floating gate FG. As a result, the floating gate FG of the selected memory cell 101
Charge is accumulated, and 1-bit data is written and stored.

[2-c] Read Mode In the read mode, the selected memory cell 101
For example, 5 V is supplied to the word line WLm connected to the control gate CG, and the potentials of the other word lines (non-selected word lines) WLa to WL1 and WLn to WLz are set to the ground level. Selected memory cell 10
1 bit line BLm connected to the drain D,
For example, 2.5 V is supplied, and the other bit lines (non-selected bit lines) BLa to BLl and BLn to BLz are set to the ground level.

As described above, since electrons are extracted from the floating gate FG of the memory cell 101 in the erased state, the floating gate FG is positively charged. Further, since electrons are injected into the floating gate FG of the memory cell 101 in the written state, the floating gate FG
Is negatively charged. Therefore, the channel CH immediately below the floating gate FG of the memory cell 101 in the erased state is on, and the channel CH immediately below the floating gate FG of the memory cell 101 in the written state is off. Therefore, when 5 V is applied to the control gate CG, the current (cell current) flowing from the drain D to the source S is larger in the erased memory cell 101 than in the written memory cell 101.

The value of the data stored in the memory cell 101 is read by determining the magnitude of the cell current between the memory cells 101 by each sense amplifier in the sense amplifier group 130. In this embodiment, reading is performed with the data value of the memory cell 101 in the erased state being “1” and the data value of the memory cell 101 in the written state being “0”.

Thereafter, the rewriting operation is continued similarly, and this rewriting operation becomes possible until the number of rewriting reaches a predetermined value T2 as shown in FIG. Therefore, in the present invention,
Compared to the conventional device, the memory cells 10
1 can be extended. For convenience of explanation, it has been described as if the selected word line WL is the word line WLm and the rewrite operation is performed continuously for all the memory cells 101 connected to the word line WLm. Naturally, all the memory cells 10 connected to the word line WL selected at random.
A rewrite operation to 1 is performed.

According to the present embodiment configured as described above, the data rewrite operation is repeated, and the cell current Ir in the read mode increases as the number of data rewrites increases as shown in FIG. While the cell current Iw of the memory cell 101 in the state does not substantially change, the cell current Ii of the memory cell 101 in the erased state decreases, and this cell current Ii is smaller than the cell current value Ir1 as the determination level. Rewrite times T1
(See FIG. 1), the memory cell 1 in the written state
01 and the memory cell 101 in the erased state, it is not possible to determine the magnitude of the cell current. This rewrite frequency T1 is the operating life of the conventional memory cell 101. In the present invention, the rewrite frequency T1 is counted. At this point, the cell current I in the read mode as a determination level for determining the write state or the erase state of the memory cell is determined.
By changing r to Ir2, as shown in FIG.
The operating life of the memory cell 101 can be extended by T1 times. That is, in the present invention, the memory cell 101
The rewriting operation, which greatly affects the operation life of the semiconductor device, is repeated, and the stress applied to the silicon oxide film 104 during the erasing operation forms an electron trap in the silicon oxide film 104. The electron trap serves as a barrier, and the floating gate FG becomes a barrier. In the initial stage of the rewriting operation, the cell current Ir in the read mode is changed to the cell state of the memory cell 101 in the write state as shown in FIG. 1 by utilizing the phenomenon that the transfer of electrons from the gate to the control gate CG is hindered. Current I
w (10 μm) and the cell current Ir1 (3
0 μm), this Ir1 is used as a determination level, and “0” and “1” determination of the memory cell is performed. By continuing the rewriting operation, an electron trap becomes a barrier, and the floating gate FG to the control gate CG Even if the cell current Ii decreases, the number of rewrites can be increased by changing the cell current Ir as a determination level from Ir1 to Ir2. In other words, the rewriting operation is continued, and electrons are more likely to remain on the floating gate FG at the time of erasing, so that the cell current Iw also tends to decrease below the initial value. However, when the number of times of rewriting T1 has been reached, the margin for the “1” determination is increased (“0”).
By performing the control (narrowing the judgment margin), the operating life of the memory cell 101 can be extended, and the flash EEPROM 121 using the memory cell 101 can be extended.
Can be extended, and the control for lowering the determination level after reaching the predetermined number of rewrites is effective.

Next, a second embodiment in which the present invention is embodied in a flash EEPROM 221 using a stacked gate type memory cell 201 will be described with reference to the drawings. In the second embodiment, the stacked gate type memory cell 2
01 and the entire structure of the flash EEPROM 221 are the same as those of the conventional embodiment shown in FIGS.

(Second Embodiment) FIG. 2 shows the relationship between the number of data rewrites and the cell current in the read mode and the voltage Vd of the drain region D in the erase mode. The erase mode, the write mode, and the read mode in the present embodiment are the same as those in the conventional mode. The present embodiment differs from the conventional embodiment in the following points.

[1] The control core circuit 132 counts the number of times of data rewriting by a counter (not shown). If the counted value exceeds a predetermined value T1, the control core circuit 132 stores it in the memory cell 201, and thereafter, In the read mode, the cell current value Ir of the reference cell as the determination level for determining the write state or the erase state of the memory cell is set to Ir.
Control is performed to change from 1 to Ir2.

The predetermined value T1 is the cell current Ii of the memory cell 201 in the erased state when a certain erase voltage is applied.
Corresponds to the number of data rewrites when the cell current Ir1 is reached. That is, to determine the predetermined value T1 when a desired erase voltage is applied, a large number of memory cells 20 are required.
1, cell current I with respect to the number of data rewrites
It is sufficient to actually measure the decrease of i, and in the present embodiment, the initial stage (the first number of data rewrites to the first predetermined value T1)
Until the predetermined cell current value Ir1 (for example, the cell current at the time of erasing is 100 μm as the reference level).
A, which is 30% of A, and a predetermined cell current value Ir2 as a reference cell determination level after the predetermined value T1.
(For example, when the cell current at the time of erasing is
%, Which is 20 μA).

[2-a] Erase Mode In the erase mode, the common drain line bias circuit 222 is used.
Supplies a desired voltage Vd (eg, 12 V) commonly to the common drain DL. Therefore, the drain regions D of all the memory cells 201 are raised to 12V.
At the same time, the row decoder 123 outputs the unselected word line WL
a to WLl and WLn to WLz are supplied with a voltage of 12V
To

Therefore, unselected word lines WLa-WL
1, each memory cell 20 connected to WLn to WLz
One control gate CG is raised to 12V. still,
The row decoder 123 sets the potential of the selected word line WLm to the ground level as in the conventional embodiment. Therefore, the control gate CG of each memory cell 201 connected to the selected word line WLm is set to the ground level as in the conventional embodiment.

At this time, the column decoder 124 keeps all the bit lines BLa to BLz open as in the conventional embodiment. As a result, the drain D becomes 12 V, the control gate CG becomes the ground level, and a high electric field is generated between the drain D and the floating gate FG. As a result, F-
An N tunnel current flows, electrons in the floating gate FG are drawn to the drain D side (see the arrow B in FIG. 5), and the data described in the memory cell 201 is erased.

This erase operation is performed by selecting the selected word line WL.
This is performed for all the memory cells 201 connected to m. [2-b] Write Mode In the write mode, the selected memory cell 201
For example, 12 V is supplied to the word line WLm connected to the control gate CG, and the potentials of the other word lines (non-selected word lines) WLa to WL1 and WLn to WLz are set to the ground level. Selected memory cell 2
01 to the bit line BLm connected to the source S
For example, 5 V is supplied, and the potentials of the other bit lines (non-selected bit lines) BLa to BLl and BLn to BLz are set to the ground level. Common drain line bias circuit 2
Reference numeral 22 holds the drains D of all the memory cells 201 at the ground level via the common drain line DL.

As a result, the potential of the floating gate FG is raised by the coupling from the control gate CG,
Hot electrons generated near the source S are injected into the floating gate FG. As a result, charges are accumulated in the floating gate FG of the selected memory cell 201, and 1-bit data is written and stored. (C) Read mode In the read mode, the selected memory cell 201
For example, 5 V is supplied to the word line WLm connected to the control gate CG, and the potentials of the other word lines (non-selected word lines) WLa to WL1 and WLn to WLz are set to the ground level. All bit lines BLa-B
The potential of Lz is set to the ground level. The common drain line bias circuit 222 is connected to the common drain line
For example, 5 V is applied to the drains D of all the memory cells 201.

As a result, as in the case of the split gate memory cell 101, the current (cell current) flowing from the drain D to the source S is larger in the erased memory cell 201 than in the written memory cell 201. Become. By determining the magnitude of the cell current between the memory cells 201 by each sense amplifier in the sense amplifier group 130, the value of the data stored in the memory cell 201 is read. In the present embodiment, reading is performed with the data value of the memory cell 201 in the erased state being “1” and the data value of the memory cell 201 in the written state being “0”.

Thereafter, the rewriting operation is continued similarly, and this rewriting operation becomes possible until the number of rewriting reaches a predetermined value T2 as shown in FIG. Therefore, in the present invention,
Compared to the conventional device, the number of memory cells 20 is equal to T2-T1 times.
1 can be extended. For convenience of explanation, the selected word line WL is a word line WLm, and all the memory cells 2 connected to the word line WLm are selected.
01 has been described as if the rewrite operation is performed, but it goes without saying that the rewrite operation is performed on the memory cell 201 connected to the word line WL selected at random. It is.

According to the present embodiment configured as described above, the data rewriting operation is repeated, and the cell current Ir in the read mode increases as the number of data rewrites increases as shown in FIG. While the cell current Iw of the memory cell 201 in the state does not substantially change, the cell current Ii of the memory cell 201 in the erased state decreases, and this cell current Ii is smaller than the cell current value Ir1 as the determination level. Rewrite times T1
(See FIG. 2), the memory cell 2 in the written state is reached.
01 and the memory cell 201 in the erased state cannot be discriminated, and the number of rewrites T1 is the operating life of the conventional memory cell 201. In the present invention, the number of rewrites T1 is counted. At this point, the cell current I in the read mode as a determination level for determining the write state or the erase state of the memory cell is determined.
By changing r to Ir2, as shown in FIG.
The operating life can be extended by T1 times. That is, in the present invention, the rewriting operation, which greatly affects the operation life of the memory cell 201, is repeated, and an electron trap is formed in the silicon oxide film 203 by the stress applied to the silicon oxide film 203 during the erasing operation. In the initial stage of the rewriting operation, the cell current Ir in the read mode is changed as shown in FIG. 2 by utilizing the phenomenon that the trap acts as a barrier to hinder the transfer of electrons from the floating gate FG to the control gate CG. Is set to a cell current Iw (10 μm) of the memory cell 201 in a written state and a cell current Ir1 (30 μm) having a relatively large margin,
Using this Ir1 as a determination level, “0”,
By making a “1” determination and continuing the rewrite operation,
The electron trap acts as a barrier, making it difficult for electrons to move from the floating gate FG to the control gate CG. Even if the cell current Ii decreases, the cell current Ir serving as the determination level is changed from Ir1 to Ir2, so that the number of times of rewriting can be improved. Can be extended. In other words, if the rewriting operation is continued and the electrons are more likely to remain on the floating gate FG at the time of erasing, the cell current Iw tends to decrease. Therefore, initially, the margin for the “0” and “1” determination is set to be wider, Number of rewrites T1
At the point when the value reaches “1”, the margin of judgment is expanded (“0”
By performing the control (narrowing the margin of determination), the operating life of the memory cell 201 can be extended, and the flash EEPROM 221 using the memory cell 201 can be extended.
The operation life can be extended, and control to lower the determination level after reaching the predetermined number of rewrites is effective.

As described above, according to the nonvolatile semiconductor memory of the present invention, when the charge (electrons) stored in the floating gate FG is erased by using the FN tunnel current, a preset value is set. When the number of times of data rewriting exceeds the number of times of data rewriting, the operation life of the memory cell can be extended by lowering the judgment level at the time of "0" or "1" judgment,
The operating life of the flash EEPROM using the memory cell can be extended.

[0065]

According to the nonvolatile semiconductor memory of the present invention, when the charges (electrons) stored in the floating gate FG are erased by using the Fowler-Nordheim tunnel current, the data of the preset data is erased. When the number of times of rewriting is exceeded, the operation life of the memory cell can be extended by lowering the judgment level at the time of "0" or "1" judgment,
The operating life of the flash EEPROM using the memory cell can be extended.

[Brief description of the drawings]

FIG. 1 is a characteristic diagram for explaining the operation of the first embodiment.

FIG. 2 is a characteristic diagram for explaining the operation of the second embodiment.

FIG. 3 is a schematic sectional view showing a configuration of a split gate type memory cell according to the first embodiment of the present invention and a conventional mode.

FIG. 4 shows a flash EEPROM using split gate type memory cells according to the first embodiment of the present invention and a conventional type.
FIG. 3 is an overall configuration diagram of M.

FIG. 5 is a schematic sectional view showing a configuration of a stacked gate type memory cell according to a second embodiment of the present invention and a conventional type.

FIG. 6 shows a flash EEPROM using stacked gate type memory cells according to a second embodiment of the present invention and a conventional type.
FIG. 3 is an overall configuration diagram of M.

FIG. 7 is a characteristic diagram for explaining the operation of a conventional split gate memory cell.

FIG. 8 is a characteristic diagram for explaining an operation of a conventional stacked gate memory cell.

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁶ Identification symbol FI H01L 29/788 29/792 (72) Inventor Katsumi Tatekawa 2-5-1, Keihanhondori, Moriguchi-shi, Osaka SANYO Electric Co., Ltd. In company

Claims (2)

[Claims] 1. A memory cell array in which a plurality of memory cells each including a floating gate FG, a control gate CG, a source S, a drain D, and a channel CH are arranged, and Fowler-Nordheim flowing from the control gate CG to the floating gate FG. A nonvolatile semiconductor memory for erasing data by extracting charges (electrons) stored in the floating gate FG using a tunnel current; a counter for counting the number of times data is rewritten in the memory cell; A first memory unit for storing a plurality of data rewrite counts of the memory cell; and a plurality of data rewrite counts stored in the first memory unit, the number of data rewrites of a predetermined memory cell counted by the counter. A second memory unit for storing identification data for identifying that Nonvolatile semiconductor memory characterized by a control circuit for changing the determination level for determining the write state or erase state of the memory cell based on another data. 2. A memory cell array in which a plurality of memory cells each including a floating gate FG, a control gate CG, a source S, a drain D, and a channel CH are arranged, and a Fowler-Nordheim flow from the drain D to the floating gate FG is provided. In a nonvolatile semiconductor memory for erasing data by extracting charges (electrons) stored in a floating gate FG using a tunnel current, a counter for counting the number of times of data rewriting of the memory cell is provided. A first memory unit that stores a plurality of data rewrite counts of the memory cell; and a data rewrite count of a predetermined memory cell counted by the counter is a plurality of data rewrite counts stored in the first memory unit. A second memory unit for storing identification data for identifying the arrival, Nonvolatile semiconductor memory characterized by a control circuit for changing the determination level for determining the write state or erase state of the memory cell based on the over data.