JP3301939B2 - Non-volatile semiconductor memory - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile semiconductor memory, and more particularly, to a flash EEPROM (Electro
ical Erasable and Programmable Read Only Memory)
It is about.

[0002]

2. Description of the Related Art In recent years, ferroelectric memories (Ferro-electric memories) have been developed.
Random Access Memory), EPROM (Erasable and
Non-volatile semiconductor memories such as Programmable Read Only Memory (EEPROM) and the like have attracted attention. EPROM
In EEPROMs and EEPROMs, data is stored by storing charges in a floating gate and detecting a change in threshold voltage due to the presence or absence of charges by a control gate. The EEPROM includes a flash EEPROM which erases data in the entire memory chip or divides a memory cell array into arbitrary blocks and erases data in each block unit.

[0003] Memory cells constituting a flash EEPROM are roughly classified into a split gate type and a stacked gate type. Split gate type flash EE
A PROM is disclosed in WO 92/18980 (G11C 13/00).

FIG. 6 shows the publication (WO92 / 18980).
Split-gate type memory cell 101 described in
1 shows a cross-sectional structure. An N-type source S and a drain D are formed on a P-type single crystal silicon substrate 102. On the channel CH sandwiched between the source S and the drain D,
The floating gate FG is formed via the insulating film 103 of FIG. The control gate CG is formed over the floating gate FG with the second insulating film 104 interposed. A part of the control gate CG is arranged on the channel CH via the first insulating film 103, and forms a selection gate 105.

FIG. 7 shows a cross-sectional structure of two split gate memory cells 101 arranged with a source S interposed therebetween. In order to keep the occupied area on the substrate 102 small, two memory cells 101 (hereinafter, referred to as “101a” and “101b” to distinguish the two) are connected to the source S
To the common source S and the floating gate F
G and the control gate CG are arranged in an inverted manner.

FIG. 8 shows a split gate type memory cell 1.
1 shows an overall configuration of a flash EEPROM 121 using the same. The memory cell array 122 includes a plurality of memory cells 101 arranged in a matrix.
The common word lines WLa to WLz are formed by the control gates CG of the memory cells 101 arranged in the row direction. The drains D of the memory cells 101 arranged in the column direction are connected to common bit lines BLa-BL.
Lz.

The odd-numbered word lines (WLa... WLm.
y) and the memory cells 101b connected to the even-numbered word lines (WLb... WLn... WLz) have a common source S, and the common source S causes each source line RSLa to be connected. To RSLm. For example, each memory cell 101a connected to the word line WLa and each memory cell 101b connected to the word line WLb have a common source S, and the common source S forms a source line RSLa. Each of the source lines RSLa to RSLm is connected to a common source line SL.

Each word line WLa-WLz is connected to a row decoder 123, and each bit line BLa-BLz is connected to a column decoder 124. The row address and column address specified from outside are
25. The row address and the column address are sent from the address pin 125 to the address buffer 12.
6 to the address latch 127. Of the addresses latched by the address latch 127, the row address is transferred to the row decoder 123, and the column address is transferred to the column decoder 124.

The row decoder 123 includes an address latch 1
One word line WLa to WLz (for example, WLm) corresponding to the row address latched at 27 is selected, and the selected word line WLm is connected to the gate voltage control circuit 134.

The column decoder 124 selects bit lines BLa to BLz (eg, BLm) corresponding to the column address latched by the address latch 127, and connects the selected bit line BLm to the drain voltage control circuit 133. .

The gate voltage control circuit 134 changes the potential of the word line WLm connected via the row decoder 123 to
Control is performed in accordance with each operation mode shown in FIG. The drain voltage control circuit 133 controls the potential of the bit line BLm connected via the column decoder 124 according to each operation mode shown in FIG.

The common source line SL is connected to the source voltage control circuit 1
32. The source voltage control circuit 132
Each of the source lines RSLa to RSL via the common source line SL
The potential m is controlled according to each operation mode shown in FIG.

Data specified externally is input to a data pin 128. The data is stored on data pin 128
Through the input buffer 129 and the column decoder 124
Transferred to The column decoder 124 controls the potentials of the bit lines BLa to BLz selected as described above in accordance with the data, as described later.

Data read from an arbitrary memory cell 101 is transferred from the bit lines BLa to BLz to the sense amplifier group 130 via the column decoder 124. The sense amplifier group 130 includes several sense amplifiers (not shown).
It is composed of The column decoder 124 connects the selected bit line BLm to each sense amplifier. As described later, the data determined by the sense amplifier group 130 is output from the output buffer 131 to the outside via the data pin 128.

The operation of each of the circuits (123 to 134) is controlled by the control core circuit 140. next,
Each operation mode (erase mode, write mode, read mode) of the flash EEPROM 121 will be described with reference to FIG.

(A) Erase Mode In the erase mode, all the source lines RSLa to RSL
The potentials of m and all the bit lines BLa to BLz are held at the ground level (= 0 V). 14 to 15 V is supplied to the selected word line WLm, and the other word lines (non-selected word lines) WLa to WL1, WLn to WL
The potential of z is set to the ground level. Therefore, each memory cell 10 connected to the selected word line WLm
One control gate CG is raised to 14-15V.

When the capacitance between the source S and the substrate 102 and the floating gate FG is compared with the capacitance between the control gate CG and the floating gate FG, the former is overwhelmingly larger. Therefore, the control gate CG becomes 14 to 1
When the voltage is 5 V and the drain is 0 V, a high electric field is generated between the control gate CG and the floating gate FG. As a result, the Fowler-Nordheim Tuner
nnel Current (hereinafter, referred to as FN tunnel current) flows, electrons in the floating gate FG are drawn out to the control gate CG side, and data stored in the memory cell 101 is erased.

This erase operation is performed by selecting the selected word line WL.
This is performed for all the memory cells 101 connected to m. Note that by simultaneously selecting a plurality of word lines WLa to WLz, an erase operation can be performed on all the memory cells 101 connected to each word line. The erasing operation of dividing the memory cell array 122 into arbitrary blocks for each of a plurality of sets of word lines WLa to WLz and erasing data in each block is called block erasing.

(B) Write Mode In the write mode, the potential of the selected bit line BLm is held at the ground level, and the other bit lines (unselected bit lines) BLa to BL1 and BLn to BLz
Is held at or above the potential (2 V) of the selected word line. Control gate C of selected memory cell 101
2V is supplied to the word line WLm connected to G, and the other word lines (non-selected word lines) WLa to WLm.
The potentials of WL1 and WLn to WLz are set to the ground level. 12 V is supplied to the common source line SL.

Incidentally, in the memory cell 101, the threshold voltage Vth of the transistor constituted by the control gate CG, the source S and the drain D is 0.5V. Therefore, in the selected memory cell 101, the electrons in the drain D move into the channel CH in the inverted state.
Therefore, a current (cell current) Id flows from the source S to the drain D. On the other hand, since 12 V is applied to the source S, the potential of the floating gate FG is raised by the coupling between the source S and the floating gate FG via the capacitance. Therefore, a high electric field is generated between the control gate CG and the floating gate FG. Therefore, the electrons in the channel CH are accelerated to become hot electrons, and are injected into the floating gate FG. That is, a current flows from the floating gate FG toward the substrate 102 (hereinafter referred to as a write current).
Ifg flows. As a result, the selected memory cell 10
Electric charge is accumulated in one floating gate FG, and one-bit data is written and stored.

This writing operation is different from the erasing operation.
This can be performed for each selected memory cell 101. (C) Read mode In the read mode, the selected memory cell 101
4V is supplied to the word line WLm connected to the control gate CG, and the potentials of the other word lines (non-selected word lines) WLa to WLl and WLn to WLz are set to the ground level. 2 V is supplied to the bit line BLm connected to the drain D of the selected memory cell 101, and the other bit lines (non-selected bit lines) BLa to BLm are supplied.
The potentials of BL1, BLn to BLz are set to the ground level.

As described above, since electrons are extracted from the floating gate FG of the memory cell 101 in the erased state, the floating gate FG is positively charged. Further, since electrons are injected into the floating gate FG of the memory cell 101 in the written state, the floating gate FG
Is negatively charged. Therefore, the channel CH immediately below the floating gate FG of the memory cell 101 in the erased state is on, and the channel CH immediately below the floating gate FG of the memory cell 101 in the written state is off. Therefore, when 4 V is applied to the control gate CG, the current flowing from the drain D toward the source S (cell current)
Id is larger in the erased memory cell 101 than in the written memory cell 101.

The cell current value I between the memory cells 101
By determining the magnitude of d by each sense amplifier in the sense amplifier group 130, the value of the data stored in the memory cell 101 can be read. For example, reading is performed with the data value of the memory cell 101 in the erased state set to “1” and the data value of the memory cell 101 in the written state set to “0”. That is, each of the memory cells 101 has a data value “1” in the erased state and a data value “0” in the written state.
Values can be stored.

This read operation is different from the erase operation.
This can be performed for each selected memory cell 101. Meanwhile, in the split gate type memory cell 101, a flash EEPROM in which a source S is called a drain and a drain D is called a source is disclosed in US Pat. No. 5,029,130.
(G11C 11/40).

FIG. 10 shows the publication (US Pat. No. 5,002,913).
0) Split gate type memory cell 2
01 shows a cross-sectional structure. FIG. 11 shows a flash EEPROM 20 using a split gate type memory cell 201.
2 shows the overall configuration.

FIG. 12 shows a flash EEPROM 202.
3 shows the potential of each part in each operation mode. The split gate memory cell 201 is different from the split gate memory cell 101 only in that the names of the source S and the drain D are reversed. That is, the source S of the memory cell 201 is called a drain D in the memory cell 101, and the drain D of the memory cell 201 is called a source S in the memory cell 101.

In the flash EEPROM 202,
The only difference from the flash EEPROM 121 is that the common source line SL is grounded. Therefore, in any operation mode, the potentials of the source lines RSLa to RSLm are held at the ground level via the common source line SL.

In the write mode, 12 V is supplied to the bit line BLm connected to the drain D of the selected memory cell 201, and the other bit lines (unselected bit lines) BLa to BL1, BLn ~ BLz
Is set to the ground level.

Incidentally, in the memory cell 201, the threshold voltage Vth of the transistor constituted by the control gate CG, the source S and the drain D is 0.5V. Therefore, in the selected memory cell 201, the electrons in the source S move into the channel CH in the inverted state. Therefore, a current (cell current) Id flows from the drain D to the source S. On the other hand, since 12 V is applied to the drain D, the potential of the floating gate FG is raised by the coupling between the drain D and the floating gate FG via the capacitance. Therefore, a high electric field is generated between the control gate CG and the floating gate FG. Therefore, channel CH
The electrons inside are accelerated to become hot electrons and are injected into the floating gate FG. That is, a current (hereinafter, referred to as a write current) Ifg flows from the floating gate FG toward the substrate 102. As a result, charges are accumulated in the floating gate FG of the selected memory cell 201, and 1-bit data is written and stored.

In the flash EEPROM 121, a configuration has been proposed in which the source voltage control circuit 132 is replaced with a source current control circuit. In this case, the source current control circuit controls the cell current value Id to a constant value, so that each source line RSL is connected via the common source line SL.
The potentials of a to RSLm are controlled in accordance with each operation mode shown in FIG.

A configuration has also been proposed in which the drain voltage control circuit 133 is replaced with a drain current control circuit in the flash EEPROM 121 or the flash EEPROM 202. In this case, by controlling the cell current value Id to a constant value by the drain current control circuit, the potential of the bit line BLm is controlled corresponding to each operation mode shown in FIG. 9 or FIG.

Further, a configuration in which a source line decoder is provided in the flash EEPROM 121 has been proposed. The source line decoder outputs 1 corresponding to the column address.
The source lines RSLa to RSLm are selected, and the selected source line is connected to the source voltage control circuit 132.

By the way, in recent years, flash EEPROM
In order to reduce power consumption, it is required to lower the power supply voltage (low power supply voltage operation). In recent years, in order to improve the degree of integration of a flash EEPROM, a binary (= 1 bit) of an erased state and a written state is provided in a memory cell.
Is required to store not less than three values (multi-value storage operation).

FIG. 13 shows characteristics of the potential Vfg of the floating gate FG and the cell current value Id in the split gate memory cells 101 and 201. Note that the floating gate potential Vf
g is the drain D of the memory cell 101 (memory cell 20
1 is the potential of the floating gate FG with respect to the source S).

In the read mode, the control gate CG
Is applied with a constant voltage (= 4 V), the channel CH immediately below the control gate CG functions as a constant resistance.
Therefore, the split gate memory cells 101 and 201
Can be regarded as a series connection of a transistor composed of the floating gate FG, the source S and the drain D, and a constant resistance composed of the channel CH immediately below the control gate CG.

Therefore, in the region where the floating gate potential Vfg is less than a certain value (= 3.5 V), the characteristics of the transistor become dominant. Therefore, in the memory cells 101 and 201, the threshold voltage Vth (=) of the transistor constituted by the floating gate FG, the source S and the drain D
In a region where the floating gate potential Vfg is smaller than 0.5 V), the cell current value Id becomes zero. When the floating gate potential Vfg exceeds the threshold voltage Vth, the cell current value Id
Indicates upward-sloping characteristics. In addition, the floating gate potential Vf
In the region where g exceeds 3.5 V, the characteristic of the constant resistance composed of the channel CH immediately below the control gate CG becomes dominant,
The cell current value Id is saturated.

The floating gate potential Vfg is generated by the electric charge accumulated in the floating gate FG in the write operation and the potential Vfgc generated by coupling from the source S of the memory cell 101 (the drain D of the memory cell 201). (Vfg =
Vfgw + Vfgc). In the read operation, the potential V
Since fgc is constant, the cell current value Id is equal to the potential Vfg.
It is uniquely determined by w. In the write operation, the amount of charge of the floating gate FG can be controlled by adjusting the operation time. Therefore, in the writing operation, if the potential Vfgw is controlled by controlling the operation time of the floating gate FG and controlling the amount of charge, the floating gate potential Vfg can be controlled.
As a result, the cell current value Id in the read operation can be set arbitrarily.

Therefore, as shown in FIG. 13, the area where the cell current value Id is less than 40 μA is defined as the data value “00”, 40 μA.
The data value “01”, 80 μA
The data value of “10”, 12
The region of 0 μA or more is associated with the data value “11”. In the write operation, the floating gate potential Vfg (= Va, Vb, Vc) is changed to the above-mentioned cell current value I.
The operation time is adjusted so as to have a value corresponding to d (= 40, 80, 120 μA).

That is, the memory cell 10 in the erased state
Since electrons have been extracted from the floating gates FG1,1,201, they are in the same state as storing the data value "11". At this time, the floating gate potential Vfg is higher than the potential Vc (= 2.5 V). Then, as the write operation is performed and the charges are accumulated in the floating gate FG, the floating gate potential Vfg decreases. Therefore, if the write operation is stopped when the floating gate potential Vfg becomes equal to or higher than Vb (= 1.5 V) and lower than Vc (= 2.5 V), the input data having the data value “10” is stored in the memory cells 101 and 201. It will be written. The floating gate potential Vfg is equal to or higher than Va (= 1.0 V).
If the write operation is stopped when the value becomes less than b, the input data having the data value “01” has been written to the memory cells 101 and 201. In addition, the floating gate potential Vf
If the write operation is stopped when g becomes less than Va, the input data having the data value “00” has been written to the memory cells 101 and 201.

In this way, one memory cell 10
Four values (= 2 bits) can be stored in 1,201. By the way, in order to perform a low power supply voltage operation and a multi-value storage operation in a flash EEPROM,
It is indispensable to precisely control the write state by precisely controlling the floating gate potential Vfg of the memory cells 101 and 201 during the write operation. That is, it is important to accurately set the floating gate potential Vfg of the memory cells 101 and 201 after writing to a desired value.

As a method therefor, a verify writing method is generally used at present. For example, regarding the verify write method in the multi-value storage operation,
JP-A-4-57294 (G11C 16/04, H01L 27/11
5, H01L 29/788, H01L 29/792).

In the verify write method, first, a certain time (several hundreds of nsec.) Is applied to the memory cells 101 and 201.
A write operation is performed for several μsec, and then a read operation for verification (verify read operation) is performed. Subsequently, the data value to be written in the write operation,
The data value read in the read operation (ie, the data value actually written in the write operation) is compared (comparison operation). Here, if the data value to be written does not match the read data value, the writing operation is performed again for a fixed time. As described above, the cycle of the write operation → the verify read operation → the comparison operation is repeated until the data value to be written matches the read data value.

[0043]

When the split gate type memory cell 101 is manufactured, the floating gate FG and the control gate CG are used as an ion implantation mask, and impurities are ion-implanted into the substrate 102 so that the source S is removed. And a drain D is formed. Therefore, the position of the drain D is defined by the end of the control gate CG, and the position of the source S is defined by the end of the floating gate FG.

Here, each of the gates FG and CG is separately formed through steps of electrode material film deposition → lithography → etching. Therefore, each gate FG, C
The position of G is determined in the lithography superimposition step. That is, there is a possibility that the position of each of the gates FG and CG may be shifted due to an overlay error of the lithographic apparatus.

Therefore, as shown in FIG. 14A, when the position of the etching mask RP for forming the control gate CG is shifted with respect to each of the memory cells 101a and 101b, the shape of the control gate CG is changed. Each memory cell 101
a and 101b are different.

Then, by using the control gate CG as a mask for ion implantation and implanting impurities into the substrate 102, a drain D is formed. As a result, FIG.
As shown in (b), each memory cell 101a, 101b
Channel CH lengths (channel lengths) L1 and L2 are different. However, the etching mask R
Since the width does not change even if the position of P is shifted, the width does not change even if the shape of the control gate CG changes. Therefore, as shown in FIG.
When the position of P is shifted to the left with respect to each of the memory cells 101a and 101b, as shown in FIG. 14B, the channel length L2 of the memory cell 101b arranged on the left is arranged on the right. Becomes longer than the channel length L1 of the memory cell 101a. Conversely, etching mask RP
Is shifted to the right with respect to each of the memory cells 101a and 101b, the memory cell 101 disposed on the right
The channel length L1 of “a” is longer than the channel length L2 of the memory cell 101b arranged on the left side.

When the channel lengths L1 and L2 are different, the resistance of the channel CH is also different, so that a difference occurs in the cell current Id during the write operation. In other words, the longer the channel length L, the greater the resistance of the channel CH, and the smaller the cell current Id during the write operation. Cell current Id
, A difference also occurs in the hot electron generation rate. As a result, the write characteristics of the memory cells 101a and 101b are different.

This problem occurs not only in the split gate memory cell 101 but also in the split gate memory cell 201. FIG. 15 shows the characteristics of the time required for the write operation (write operation time) Tpw and the cell current Id during the read operation. In the case of the verify write method, the write operation time Tpw is the total time of each write operation in the cycle (write operation → verify read operation → comparison operation).

When the channel length L is short (L1), the same write operation time Tpw is required as compared to when the channel length L is long (L2).
, The cell current Id during the read operation becomes smaller.
As described above, the cell current Id at the time of the read operation is set when the memory cells 101 and 201 are in the completely erased state (Id
1) is larger than (Id2) in the complete write state. Then, when the channel length L is short (L
1) requires only a short operation time (Tpw1),
In the case of a long time (L2), a long operation time (Tpw2) is required.

FIG. 16 shows the characteristics of the channel length L and the write operation time Tpw required for a complete write state. It can be seen that as the channel length L becomes longer, the write operation time Tpw required to attain a complete write state increases logarithmically.

As described above, the channel length L varies due to the displacement between the floating gate FG and the control gate CG, so that the write operation time Tpw also varies.
The variation in the write operation time Tpw is caused by the floating gate potential Vf of the memory cells 101 and 201 after writing.
This is a major obstacle in controlling g precisely.

If the write operation time Tpw is made very long, the floating gate potential Vfg of the memory cells 101 and 201 after writing can be made constant. However, in this case, the unnecessary write operation is continued even after the write operation is completed for the memory cell 101 which is completely written in the short write operation time Tpw. Accordingly, not only the writing operation speed is reduced, but also the power consumption required for the writing operation is increased.

The present invention has been made to solve the above-mentioned problem, and an object of the present invention is to be able to accurately control a write state of a memory cell regardless of structural variations of the memory cell. An object of the present invention is to provide a semiconductor memory.

[0054]

According to a first aspect of the present invention, there is provided a floating gate (FG), a control gate (CG), and a source.
(S), drain (D) and channel (CH)
Each memory cell (101) has a source, a drain,
By controlling the potential of the control gate,
Write control means (1) for controlling a data write operation
32 to 134, 140) and the floating gate of the memory cell.
Determine the flowing write current (Ifg) and determine the result
Write current determination that controls the write control means according to
The gist is to provide the means (2).

[0055]

[0056] According to a second aspect of the invention, a nonvolatile semiconductor memory according to claim 1, comprising the memory cell and the reference cell of the same size and shape (3a, 3b), said write control means includes reference The write operation of the reference cell is controlled by controlling the potentials of the source and drain of the reference cell and the potential of the control gate, and the write current determining means controls the write current (Ifg) flowing through the floating gate of the reference cell.
The gist is to judge c) and control the writing control means according to the judgment result.

The invention described in claim 3 is the invention according to claim 1 or
3. The nonvolatile semiconductor memory according to claim 2 , wherein said write current determination means controls said write control means so that said write current becomes constant.

According to a fourth aspect of the present invention, in the nonvolatile semiconductor memory according to any one of the first to third aspects,
A memory cell array (122) formed by arranging a plurality of memory cells in a matrix, and the memory cell array includes a plurality of cell blocks (122a, 122a);
The point is that the write current determination means is separately provided for each of the cell blocks.

According to a fifth aspect of the present invention, the floating gate (F
G), a control gate (CG), a source (S), a drain (D), and a channel (CH).
01) and write control means (132 to 134, 1) for controlling the data write operation to the memory cell by controlling the potentials of the source and drain and the control gate.
40) and determining means for determining the potential (Vfg) of the floating gate of the memory cell and controlling the writing control means in accordance with the result of the determination.

[0060]

According to a sixth aspect of the present invention, in the nonvolatile semiconductor memory according to any one of the first to fifth aspects,
The write control means includes a source voltage control circuit (132) for controlling the potential of the source (S) of the memory cell, a drain voltage control circuit (133) for controlling the potential of the drain (D) of the memory cell, Control gate (C
The gist thereof is that a gate voltage control circuit (134) for controlling the potential of G) is provided.

According to a seventh aspect of the present invention, in the nonvolatile semiconductor memory according to any one of the first to sixth aspects,
The write control means controls a source current by controlling a current flowing through a source (S) of the memory cell, and a drain voltage control circuit (a drain current control circuit) controls a potential of a drain (D) of the memory cell. 133) and a gate voltage control circuit (134) for controlling the potential of the control gate (CG) of the memory cell.

The invention according to claim 8 is the non-volatile semiconductor memory according to any one of claims 1 to 6 ,
The write control means includes a source voltage control circuit (132) for controlling the potential of the source (S) of the memory cell, and a drain current for controlling the potential of the drain by controlling the current flowing to the drain (D) of the memory cell. The gist is that a control circuit and a gate voltage control circuit (134) for controlling the potential of the control gate (CG) of the memory cell are provided.

According to a ninth aspect of the present invention, in the nonvolatile semiconductor memory according to any one of the first to eighth aspects,
The gist is that the memory cell is of a split gate type.

[0065]

BEST MODE FOR CARRYING OUT THE INVENTION

(First Embodiment) A first embodiment in which the present invention is embodied in a split gate type flash EEPROM will be described below with reference to the drawings. In this embodiment, FIGS.
The same components as those of the conventional embodiment shown in FIG. 9 are denoted by the same reference numerals, and detailed description thereof will be omitted.

FIG. 1 shows the overall configuration of a flash EEPROM 1 using the split gate memory cell 101 of the present embodiment. FIG. 1 differs from the conventional flash EEPROM 121 shown in FIG. 8 only in that a write current determination circuit 2 is provided. The write current determination circuit 2 includes reference cells 3a and 3b, a reference cell switching circuit 4, a reference current generation circuit 5, and a comparison circuit 6.

FIG. 2 shows a sectional structure of the reference cells 3a and 3b. In the reference cells 3a and 3b, the same components as those in the memory cells 101 have the same reference numerals. Each of the reference cells 3a, 3b is formed in the same size and shape in the vicinity of the memory cell array 122 by the same process as that of each of the memory cells 101a, 101b shown in FIG. Each of the reference cells 3a and 3b has a common source S,
The floating gate FG and the control gate CG are arranged in an inverted manner with respect to the source S. Therefore, the channel lengths L1 and L2 of the reference cells 3a and 3b are the same as those of the memory cells 101a and 101b. That is, as shown in FIG. 14B, when the channel length L2 of the memory cell 101b is longer than the channel length L1 of the memory cell 101a, the channel length L2 of the reference cell 3b is changed.
Is longer than the channel length L1 of the reference cell 3a.

A common source S for each of the reference cells 3a and 3b
Are connected to the source voltage control circuit 132 and each drain D
Is connected to the drain voltage control circuit 133, and each control gate CG is connected to the gate voltage control circuit 134.
Therefore, the potentials of the source S, the drain D, and the control gate CG of each of the reference cells 3a and 3b are respectively set to the memory cell selected by each of the decoders 123 and 124 in each operation mode (erase mode, write mode, and read mode). 101a, 101b of source S, drain D,
Control is performed so as to be equal to the potential of the control gate CG.
That is, the bias condition of each of the reference cells 3a and 3b becomes the same as that of the selected memory cells 101a and 101b.

Each floating gate F of each reference cell 3a, 3b
G is connected to the reference cell switching circuit 4. The reference cell switching circuit 4 selects the reference cells 3a and 3b corresponding to the word lines WLa to WLz selected by the row decoder 123, and the floating gate FG of the selected reference cells 3a and 3b and the comparison circuit 6 And connect. That is, when the row decoder 123 is connected to the odd-numbered word lines (WLa... WLm.
y) (ie, each memory cell 101a)
Is selected), the reference cell switching circuit 4 selects the reference cell 3a. When the row decoder 123 selects an even-numbered word line (WLb... WLn... WLz) (that is, when each memory cell 101b is selected), the reference cell switching circuit 4 selects the reference cell 3b. .

The reference current generation circuit 5 generates a reference current Ir. The reference current Ir is a write current Ifg (hereinafter, memory cell) flowing from the floating gate FG of the reference cells 3a, 3b toward the substrate 102 when the channel lengths L1, L2 of the reference cells 3a, 3b are the same. 101 is written as “Ifgc” in order to distinguish it from the write current Ifg of FIG. 101). That is, the reference current Ir is an average value of the write currents Ifgc of the reference cells 3a and 3b. Therefore, the reference current generation circuit 5
The method of generating the reference current Ir includes a method of generating a preset reference current Ir and a method of calculating an average value of the write current Ifgc of each of the reference cells 3a and 3b every time a write operation is performed.

The comparison circuit 6 compares the write current Ifgc of the reference cells 3a and 3b with the reference current Ir, and generates a control signal W based on the comparison result. In the write operation, the operation of each of the voltage control circuits 132 to 134 is controlled according to the control signal W of the comparison circuit 6.

That is, when the write current Ifgc is smaller than the reference current Ir, the comparison circuit 6 controls each of the voltage control circuits 132 to 134 by one of the following methods [1] to [4].

[1] Only the output potential of the source voltage control circuit 132 is raised from the value (12 V) shown in FIG. 9, and the output potential of each of the voltage control circuits 133 and 134 is kept at the value shown in FIG. As a result, the selected memory cells 101a,
Only the potential of the source S of the reference cell 101b and each of the reference cells 3a and 3b rises.

[2] Only the output potential of the gate voltage control circuit 134 is raised from the value (2 V) shown in FIG. 9, and the output potentials of the voltage control circuits 132 and 133 are kept at the values shown in FIG. As a result, the selected memory cell 101a, 1
01b and the control gate CG of each reference cell 3a, 3b
Only the electric potential of rises.

[3] The above [1] and [2] are performed simultaneously. That is, the output potentials of the source voltage control circuit 132 and the gate voltage control circuit 134 are raised from the values shown in FIG. 9, and the output potentials of the drain voltage control circuit 133 are kept at the values shown in FIG. As a result, the selected memory cell 101
a, 101b and the source S of each reference cell 3a, 3b
And the potential of the control gate CG rises.

[4] Only the output potential of the drain voltage control circuit 133 is lowered from the value (0 V) shown in FIG. 9, and the output potential of each of the voltage control circuits 133 and 134 is kept at the value shown in FIG. As a result, the selected memory cells 101a,
Only the potential of the drain D of the reference cell 101b and each of the reference cells 3a, 3b falls.

According to the above [1] to [4], the write current Ifgc increases and becomes equal to the reference current Ir. Also,
When the write current Ifgc is larger than the reference current Ir, the comparison circuit 6 controls each of the voltage control circuits 132 to 134 by one of the following methods [5] to [8].

[5] Only the output potential of the source voltage control circuit 132 is lowered from the value (12 V) shown in FIG. 9, and the output potential of each of the voltage control circuits 133 and 134 is kept at the value shown in FIG. As a result, the selected memory cells 101a,
Only the potential of the source S of the reference cell 101b and each of the reference cells 3a and 3b falls.

[6] Only the output potential of the gate voltage control circuit 134 is lowered from the value (2 V) shown in FIG. 9, and the output potentials of the voltage control circuits 132 and 133 are kept at the values shown in FIG. As a result, the selected memory cell 101a, 1
01b and the control gate CG of each reference cell 3a, 3b
Only the electric potential of rises.

[7] The above [5] and [6] are performed simultaneously. That is, the output potentials of the source voltage control circuit 132 and the gate voltage control circuit 134 are made lower than the values shown in FIG. 9, and the output potentials of the drain voltage control circuit 133 are kept at the values shown in FIG. As a result, the selected memory cell 101
a, 101b and the source S of each reference cell 3a, 3b
And the potential of the control gate CG drops.

[8] Only the output potential of the drain voltage control circuit 133 is raised from the value (0 V) shown in FIG. 9, and the output potential of each of the voltage control circuits 133 and 134 is kept at the value shown in FIG. As a result, the selected memory cells 101a,
Only the potential of the drain D of the reference cell 101b and each of the reference cells 3a, 3b rises.

By the above [5] to [8], the write current Ifgc decreases and becomes equal to the reference current Ir. As described above, according to the above [1] to [8], the write current Ifg
The output potentials of the voltage control circuits 132 to 134 are controlled such that c and the reference current Ir become equal. That is, the bias condition of each of the reference cells 3a and 3b in the write operation is controlled so that the write current Ifgc and the reference current Ir are equal. Therefore, each reference cell 3a,
Even when the channel lengths L1 and L2 of 3b are different, the write current Ifgc can be set to a constant value (= reference current Ir).

Here, the bias condition of each of the reference cells 3a and 3b is the same as that of the selected memory cells 101a and 101b. Therefore, each reference cell 3a, 3b
Is controlled, the selected memory cell 1
01a and 101b are biased by the write current If
Control is performed so that g and the reference current Ir become equal. Therefore, even when the channel lengths L1 and L2 of the memory cells 101a and 101b are different, the write current Ifg can be set to a constant value (= reference current Ir).

FIG. 3 shows the characteristics of the write operation time Tpw and the cell current Id during the read operation. In FIG. 3, the characteristic of the conventional embodiment shown in FIG. 15 is indicated by a dotted line, and the characteristic of the present embodiment is indicated by a solid line.

In this embodiment, regardless of whether the channel length L is short (L1) or long (L2), the cell current Id in the read operation during the same write operation time Tpw becomes equal. Further, the write operation time Tpw required to complete the write operation to complete the write state is the same time (Tpw3) whether the channel length L is short (L1) or long (L2).

FIG. 4 shows the characteristics of the channel length L and the write operation time Tpw required for a complete write state. In FIG. 4, the characteristic of the conventional embodiment shown in FIG. 16 is indicated by a dotted line, and the characteristic of the present embodiment is indicated by a solid line.

In this embodiment, regardless of the channel length L, the write operation time Tpw required to complete the write state is constant. As described in detail above, according to the present embodiment, the following operations and effects can be obtained.

(1) Selected memory cell 101a, 1
01b, the reference cells 3a and 3b are selected, and the write current Ifgc of the selected reference cells 3a and 3b is selected.
And the reference current Ir is controlled so that the output potentials of the voltage control circuits 132 to 134 are equal. Therefore, the bias condition of the selected memory cells 101a and 101b is controlled in accordance with the write current Ifgc of the reference cells 3a and 3b. As a result, each of the memory cells 101a, 10a
Even when the channel lengths L1 and L2 of 1b are different, the write current Ifg can be set to a constant value (= reference current Ir).

(2) As described above, the write current If
g corresponds to the cell current Id during the write operation. Therefore, if the write current Ifg is controlled to a constant value, the channel lengths L1 and L1 of the memory cells 101a and 101b can be adjusted.
2, the cell current Id during the write operation can be made equal.

(3) From the above (1) and (2), the write operation time Tpw can be kept constant even if the channel length L varies due to the displacement between the floating gate FG and the control gate CG. . Therefore, the floating gate potential Vfg of the memory cell 101 after writing can be precisely controlled.

(4) From the above (3), the floating gate potential V
The fact that fg can be precisely controlled is nothing less than the fact that the charge accumulated in the floating gate FG can be precisely controlled. Therefore, the write state of the memory cell 101 can be accurately controlled.

(5) From the above (3), since the write operation time Tpw can be kept constant, the power consumption required for the write operation can be reduced without lowering the write operation speed.

(6) From the above (3), a low power supply voltage operation and a multi-value storage operation can be easily realized. (Second Embodiment) A second embodiment in which the present invention is embodied in a split gate type flash EEPROM will be described below with reference to the drawings. In this embodiment, FIGS.
The same components as those in the first embodiment shown in FIG. 4 have the same reference numerals, and detailed description thereof will be omitted.

FIG. 5 shows a flash EEPROM 11 using the split gate type memory cell 101 of this embodiment.
1 shows the entire configuration. 5 differs from the flash EEPROM 1 of the first embodiment shown in FIG. 1 only in the following points.

(1) The memory cell array 122 includes two cell blocks 12 corresponding to the word lines WLa to WLz.
2a and 122b. That is, the cell block 122a is formed by the memory cells 101a and 101b connected to the word lines WLa to WLn, and the cell block 122a is formed by the word lines WLo to WLz.
Are connected to the memory cells 101a and 101b (not shown).

(2) Each cell block 122a, 122b
For each of the write current determination circuits 2
(Hereinafter, referred to as “2a” and “2b” to distinguish the two).

Each of the reference cells 3a and 3b forming the write current determination circuit 2a is formed in the same step and the same size as the memory cells 101a and 101b forming the cell block 122a, and is formed near the cell block 122a. I have. Each of the reference cells 3a and 3b (not shown) constituting the write current determination circuit 2b includes a cell block 12
The memory cells 101a and 101b forming the memory cell 2b are formed in the same process and in the same size and shape in the vicinity of the cell block 122b.

(3) In the write operation, the memory cells 101a, 101a,
When 101b is selected, the write current determination circuit 2
The operation of each of the voltage control circuits 132 to 134 is controlled in accordance with a control signal Wa of a comparison circuit 6 (not shown) constituting a. In the write operation, each of the word lines WLo to WLo.
Memory cells 101a, 101b connected to WLz
Is selected, the operation of each of the voltage control circuits 132 to 134 is controlled according to the control signal Wb of the comparison circuit 6 (not shown) constituting the write current determination circuit 2b.

As described above, according to the present embodiment, the following operation and effect can be obtained in addition to the operation and effect of the first embodiment. (1) The same operation and effect as in the first embodiment can be obtained for each of the cell blocks 122a and 122b. That is, each memory cell 10 constituting the cell block 122a is
1a and 101b, and the memory cells 1 constituting the cell block 122b.
The write current Ifg can be set to a constant value (= reference current Ir) even when the channel lengths L1 and L2 of 01a and 101b are different.

(2) When manufacturing a large-area memory cell array 122, the memory cell array 122 is divided into a plurality of cell blocks 122a and 122b. The lithography process for forming each etching mask for forming each gate FG and CG is performed for each of the cell blocks 122a and 122b. In this lithography process, the same reticle is used for each of the cell blocks 122a and 122b. Therefore, each memory cell 101a, 1
01b may have different channel lengths L1 and L2 between the cell blocks 122a and 122b.

As described above, each cell block 122a, 1
Even when the channel length L varies between 22b, the write current Ifg can be made constant from the above (1). (3) From the above (2), for all the memory cells 101 of the memory cell array 122, the write operation time Tpw
Can be made constant, and the floating gate potential Vfg of the memory cell 101 after writing can be precisely controlled.

That is, regardless of the variation in the positional characteristics in the memory cell array 122, the memory cell 101
Can be accurately controlled. (4) According to (2), the effect of the present embodiment becomes more remarkable as the memory cell array 122 has a larger area.
Therefore, a large-capacity flash EEPROM can be easily realized. .

The above embodiments may be modified as follows, and the same operation and effect can be obtained in such a case. (1) In the second embodiment, the memory cell array 122
Is divided into three or more cell blocks. Also in this case, the write current determination circuit 2 is provided for each cell block.

(2) In the second embodiment, the memory cell array 122 is not divided by the cell blocks 122a and 122b corresponding to the word lines WLa to WLz, but is divided into bit lines BLa to BLz or source lines RSLa to RSL.
Divide by the cell block corresponding to m.

(3) In the first and second embodiments, the split gate memory cell 101 is replaced with the split gate memory cell 201 shown in FIG. In this case, the source voltage control circuit 132 is omitted and the common source line S
L is grounded. Then, in each operation mode, the potential of each section is controlled as shown in FIG.

(4) In the first and second embodiments, the source voltage control circuit 132 is replaced with a source current control circuit. In this case, by controlling the cell current value Id to a constant value by the source current control circuit, the potentials of the source lines RSLa to RSLm are controlled via the common source line SL in accordance with the respective operation modes shown in FIG. I do.

(5) In the first and second embodiments, the drain voltage control circuit 133 is replaced with a drain current control circuit. In this case, the bit line BL is controlled by controlling the cell current value Id to a constant value by the drain current control circuit.
The potential of m is controlled in accordance with each operation mode shown in FIG. 9 or FIG.

(6) In the first and second embodiments, a source line decoder is provided. The source line decoder selects one source line RSLa to RSLm corresponding to the column address, and selects the selected source line and the source voltage control circuit 1
32.

(7) By controlling the floating gate potential Vfg instead of controlling the write current Ifg, the write state of the memory cell 101 can be accurately controlled regardless of the structural variation of the memory cell 101.

(8) By controlling the cell current Id during the write operation instead of controlling the write current Ifg, the write state of the memory cell 101 can be accurately controlled regardless of the structural variation of the memory cell 101. I do.

While the embodiments have been described above, technical ideas other than the claims that can be grasped from the embodiments will be described below together with their effects. (A) In the nonvolatile semiconductor memory according to claim 1 or 2 , the write current determination means includes a reference current generation circuit (5) for generating a reference current (Ir), and a reference cell (3a, 3b). A) a non-volatile semiconductor memory including a comparison circuit (6) for comparing a write current (Ifgc) with a reference current (Ir).

In this way, it is possible to easily determine whether or not the write current has a constant value (= Ir). (B) In the nonvolatile semiconductor memory according to claim 4 , for each cell block (122a, 122b),
A nonvolatile semiconductor memory in which reference cells (3a, 3b) are separately provided.

In this way, the write state of the memory cell can be accurately controlled irrespective of the variation in the positional characteristics in the memory cell array.

[0114]

According to the first aspect of the present invention, a memory is provided.
Write state of memory cell based on cell write current
By controlling the state, the
Regardless of the writing status,
You.

[0115]

According to the second aspect of the present invention, by controlling the write control means based on the write current of the reference cell, the write state of the memory cell can be changed without directly detecting the write current of the memory cell. Can be controlled.

According to the third aspect of the present invention, when the write current is smaller than the reference value, the write current is increased, and when the write current is larger than the reference value, the write current is reduced to be constant, thereby optimally controlling the write state of the memory cell. Can be.

According to the fourth aspect of the present invention, by controlling each of the cell blocks, it is possible to accurately control the write state of the memory cell regardless of the variation in the positional characteristics in the memory cell array. it can.

According to the fifth aspect of the present invention, by controlling the write state of the memory cell based on the potential of the floating gate of the memory cell, the write state can be accurately determined regardless of the structural variation of the memory cell. Can be controlled.

[0120]

According to the invention described in any one of the sixth to ninth aspects, the write control means can be easily embodied.

[Brief description of the drawings]

FIG. 1 is a block circuit diagram of a first embodiment.

FIG. 2 is a sectional view of a reference cell according to the first and second embodiments.

FIG. 3 is a characteristic diagram of the first and second embodiments.

FIG. 4 is a characteristic diagram of the first and second embodiments.

FIG. 5 is a block circuit diagram of a second embodiment.

FIG. 6 is a cross-sectional view of the memory cells according to the first and second embodiments and a conventional mode.

FIG. 7 is a cross-sectional view of the memory cells according to the first and second embodiments and a conventional mode.

FIG. 8 is a block circuit diagram of a conventional embodiment.

FIG. 9 is an explanatory diagram of the first and second embodiments and a conventional embodiment.

FIG. 10 is a cross-sectional view of a conventional memory cell.

FIG. 11 is a block circuit diagram of a conventional embodiment.

FIG. 12 is an explanatory view of a conventional mode.

FIG. 13 is an explanatory diagram of the first and second embodiments and a conventional embodiment.

FIG. 14 is a cross-sectional view of the memory cells according to the first and second embodiments and a conventional mode.

FIG. 15 is a characteristic diagram of a conventional embodiment.

FIG. 16 is a characteristic diagram of a conventional embodiment.

[Explanation of symbols]

 S: Source D: Drain CG: Control gate Ifg, Ifgc: Write current Ir: Reference current Id: Cell current Vfg: Floating gate potential 2: Write current determination circuit 3a, 3b: Reference cells 101, 101a, 101b: Memory cells 132: source voltage control circuit 133: drain voltage control circuit 134: gate voltage control circuit 140: control core circuit

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G11C 16/02 H01L 21/8247 H01L 27/115 H01L 29/788 H01L 29/792

Claims (9)

(57) [Claims] A floating gate (FG) and a control gate (C)
G), source (S), drain (D) and channel (C
H), write control means (132 to 134, 140) for controlling the data write operation to the memory cell by controlling the potentials of the source, drain and control gate; Write current (If) flowing to the floating gate of the cell
g), and a write current determining means (2) for controlling the write control means according to the result of the determination. 2. The non-volatile semiconductor memory according to claim 1 , wherein said reference cells have the same size and shape as said memory cells.
b), wherein the write control means controls the write operation of the reference cell by controlling the source and drain of the reference cell and the potential of the control gate. A nonvolatile semiconductor memory that determines a write current (Ifgc) flowing through a floating gate and controls a write control unit according to a result of the determination. 3. The nonvolatile semiconductor memory according to claim 1 , wherein said write current determining means controls a write control means such that said write current becomes a constant value (Ir). memory. 4. The nonvolatile semiconductor memory according to claim 1 , further comprising: a memory cell array (122) including a plurality of said memory cells arranged in a matrix. Represents a plurality of cell blocks (122a, 122
b) a nonvolatile semiconductor memory in which the write current determination means is separately provided for each of the cell blocks. 5. A floating gate (FG) and a control gate (C)
G), source (S), drain (D) and channel (C
H), write control means (132 to 134, 140) for controlling the data write operation to the memory cell by controlling the potentials of the source, drain and control gate; A non-volatile semiconductor memory comprising: a determination unit configured to determine a potential (Vfg) of a floating gate of a cell and control a write control unit according to a result of the determination. 6. The nonvolatile semiconductor memory according to claim 1 , wherein said write control means includes a source voltage control circuit (132) for controlling a potential of a source (S) of a memory cell. Non-volatile semiconductor memory comprising: a drain voltage control circuit (133) for controlling the potential of the drain (D) of the memory cell; and a gate voltage control circuit (134) for controlling the potential of the control gate (CG) of the memory cell. . 7. The nonvolatile semiconductor memory according to claim 1 , wherein said write control means controls a current flowing through a source (S) of the memory cell to control a potential of the source. A source current control circuit, a drain voltage control circuit (133) for controlling the potential of the drain (D) of the memory cell, and a gate voltage control circuit (134) for controlling the potential of the control gate (CG) of the memory cell. Non-volatile semiconductor memory provided. 8. The nonvolatile semiconductor memory according to claim 1 , wherein said write control means includes a source voltage control circuit (132) for controlling a potential of a source (S) of a memory cell. A drain current control circuit that controls the potential of the drain by controlling the current flowing through the drain (D) of the memory cell; and a gate voltage control circuit (134) that controls the potential of the control gate (CG) of the memory cell. Non-volatile semiconductor memory provided. 9. The nonvolatile semiconductor memory according to claim 1 , wherein said memory cells are of a split gate type.