JP3133675B2 - Semiconductor storage device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly, to a nonvolatile semiconductor memory, in particular, a flash EEPROM (Electrical Erasable and Programmable Memory).
ble Read Only Memory).

[0002]

2. Description of the Related Art In recent years, FRAM (Ferro-electric Random
Access Memory), EPROM (Erasable and Programma)
Non-volatile semiconductor memories such as a ble read only memory (EEPL) and an EEPROM are receiving attention. EPROM and EEPROM
In the OM, data is stored by storing charges in a floating gate and detecting a change in threshold voltage due to the presence or absence of charges by a control gate.

Further, there is a flash EEPROM which erases data in the entire memory chip or divides a memory cell array into arbitrary blocks and erases data in each block unit. Memory cells constituting a flash EEPROM are roughly classified into a split gate type and a stacked gate type.

1) Split-gate type memory cell A split-gate type flash EEPROM is disclosed in WO
92/18980 (G11C 13:00). FIG. 9 shows a cross-sectional structure of a split gate memory cell 101 described in the publication.

An N-type source S and a drain D are formed on a P-type single crystal silicon substrate 102. On the channel CH sandwiched between the source S and the drain D, a floating gate FG is formed via a first insulating film 103. The control gate CG is formed over the floating gate FG with the second insulating film 104 interposed. Part of the control gate CG is the first
Are arranged on the channel CH via the insulating film 103 of FIG.

FIG. 10 shows a split gate type memory cell 1.
1 shows an overall configuration of a flash EEPROM 121 using the same. The memory cell array 122 includes a plurality of memory cells 101 arranged in a matrix. The control gates CG of the memory cells 101 arranged in the row direction are connected to common word lines WLa to WLz. Each memory cell 1 arranged in a column direction
01 is connected to the common bit lines BLa to BLz. The sources S of all the memory cells 101 are connected to a common source line SL.

Each word line WLa-WLz is connected to a row decoder 123, and each bit line BLa-BLz is connected to a column decoder 124. The row address and the column address specified from the outside are applied to the address pins 12
5 is input. The row address and the column address are transferred from the address pin 125 to the address latch 127 via the address buffer 126. Among the addresses latched by the address latch 127, the row address is transferred to the row decoder, and the column address is transferred to the column decoder 124.

The row decoder 123 has an address latch 1
One word line WLa to WLz (for example, WLm) corresponding to the row address latched at 27 is selected, and the selected word line WLm is connected to the gate voltage control circuit 134. The column decoder 124 selects a bit line BLa to BLz (for example, BLm) corresponding to the column address latched by the address latch 127 and connects the selected bit line BLm to the drain voltage control circuit 133.

The gate voltage control circuit 134 changes the potential of the word line WLm connected via the row decoder 123 to
Control is performed in accordance with each operation mode shown in FIG. The drain voltage control circuit 133 controls the potential of the bit line BLm connected via the column decoder 124 according to the operation mode shown in FIG. The common source line SL is connected to the source voltage control circuit 132. The source voltage control circuit 132 controls the potential of the common source line SL according to each operation mode shown in FIG.

Data specified externally is input to a data pin 128. The data is stored on data pin 128
Through the input buffer 129 and the column decoder 124
Transferred to The column decoder 124 controls the potentials of the bit lines BLa to BLz selected as described above in accordance with the data, as described later. Data read from an arbitrary memory cell 101 is stored in bit lines BLa-B
Lz is transferred to the sense amplifier group 130 via the column decoder 124. The sense amplifier group 130 includes several sense amplifiers (not shown). The column decoder 124 connects the selected bit line BLm to each sense amplifier. As described later, the sense amplifier group 1
The data determined at 30 is output from the output buffer 131 to the outside via the data pin 128.

Each of the circuits (123, 124, 1)
26, 127, 129 to 134) are controlled by the control core circuit 140. Next, Flash EEP
Each operation mode (erase mode, write mode, read mode) of the ROM 121 will be described with reference to FIG. (A) Erasing Mode In the erasing mode, the potentials of the common source line SL and all the bit lines BLa to BLz are set to the ground level (= 0 V).
Is held. 14 to 1 are applied to the selected word line WLm.
5 V is supplied, and the potentials of the other word lines (non-selected word lines) WLa to WL1 and WLn to WLz are set to the ground level. Therefore, the selected word line WLm
CG of each memory cell 101 connected to
Is lifted to 14-15V.

When the capacitance between the source S and the substrate 102 and the floating gate FG is compared with the capacitance between the control gate CG and the floating gate FG, the former is overwhelmingly larger. Therefore, the control gate CG becomes 14 to 15
When V and the drain are 0 V, a high electric field is generated between the control gate CG and the floating gate FG. As a result, the Fowler-Nordheim Tunne current
l Current, hereafter referred to as FN tunnel current)
Electrons in the floating gate FG are pulled out to the control gate CG side, and the data stored in the memory cell 101 is erased.

This erasing operation is performed by selecting the selected word line WL.
This is performed for all the memory cells 101 connected to m. Note that by simultaneously selecting a plurality of word lines WLa to WLz, an erase operation can be performed on all the memory cells 101 connected to each word line. The erasing operation of dividing the memory cell array 122 into arbitrary blocks for each of a plurality of sets of word lines WLa to WLz and erasing data in each block is called block erasing.

(B) Write Mode In the write mode, the potential of the selected bit line BLm is kept at the ground level, and the other bit lines (unselected bit lines) BLa to BL1 and BLn to BLz
Is held at or above the potential (2 V) of the selected word line. Control gate C of selected memory cell 101
2V is supplied to the word line WLm connected to G, and the other word lines (non-selected word lines) WLa to WL
The potentials of WL1 and WLn to WLz are set to the ground level. 12 V is supplied to the common source line SL.

Incidentally, in the memory cell 101, the threshold voltage Vth of the transistor constituted by the control gate CG, the source S and the drain D is 0.5V. Therefore, in the selected memory cell 101, the electrons in the drain D move into the channel CH in the inverted state.
Therefore, a current (cell current) flows from the source S to the drain D.
Flows.

On the other hand, since 12 V is applied to the source S, the potential of the floating gate FG is raised by the coupling between the source S and the floating gate FG via the capacitance. Therefore, a high electric field is generated between the channel CH and the floating gate FG. Therefore, the electrons in the channel CH are accelerated to become hot electrons, and as shown by the arrow A in FIG.
Injected into As a result, the selected memory cell 101
Charge is accumulated in the floating gate FG, and 1-bit data is written and stored.

This writing operation is different from the erasing operation.
This can be performed for each selected memory cell 101. (C) Read mode In the read mode, the selected memory cell 101
4V is supplied to the word line WLm connected to the control gate CG, and the potentials of the other word lines (non-selected word lines) WLa to WL1 and WLn to WLz are set to the ground level. 2 V is supplied to the bit line BLm connected to the drain D of the selected memory cell 101, and the other bit lines (non-selected bit lines) BLa to BLm are supplied.
The potentials of BL1, BLn to BLz are set to the ground level.

As described above, since electrons are extracted from the floating gate FG of the memory cell 101 in the erased state, the floating gate FG is positively charged. Further, since electrons are injected into the floating gate FG of the memory cell 101 in the written state, the floating gate FG
Is negatively charged. Therefore, the channel CH immediately below the floating gate FG of the memory cell 101 in the erased state is on, and the channel CH immediately below the floating gate FG of the memory cell 101 in the written state is off. Therefore, when 4 V is applied to the control gate CG, the current (cell current) flowing from the drain D to the source S is larger in the erased memory cell 101 than in the written memory cell 101.

The cell current value I between the memory cells 101
By determining the magnitude of d by each sense amplifier in the sense amplifier group 130, the value of the data stored in the memory cell 101 can be read. For example, reading is performed with the data value of the memory cell 101 in the erased state set to “1” and the data value of the memory cell 101 in the written state set to “0”. That is, each of the memory cells 101 has a data value “1” in the erased state and a data value “0” in the written state.
Values can be stored.

This read operation is different from the erase operation.
This can be performed for each selected memory cell 101. By the way, in the split gate type memory cell 101, a flash EEPROM in which a source S is called a drain and a drain D is called a source is disclosed in US Pat. No. 5,029,130.
(G11C11 / 40).

FIG. 12 shows a cross-sectional structure of a split gate memory cell 110 described in the publication. FIG.
3 shows the overall configuration of a flash EEPROM 111 using the split gate memory cell 110. FIG.
5 shows the potential of each part of the flash EEPROM 111 in each operation mode. In the split gate type memory cell 110, the split gate type memory cell 101
The only difference is that the names of the source S and the drain D are reversed. That is, the source S of the memory cell 110 is called the drain D in the memory cell 101, and the drain D of the memory cell 110 is
1 is called source S.

In the flash EEPROM 111,
The only difference from the flash EEPROM 121 is that the common source line SL is grounded. Therefore, in any operation mode, the potential of the common source line SL is maintained at the ground level. In the write mode, 12 V is supplied to the bit line BLm connected to the drain D of the selected memory cell 110, and the other bit lines (unselected bit lines) BLa to BL
1, the potentials of BLn to BLz are set to the ground level.

In the memory cell 110, the threshold voltage Vth of the transistor formed by the control gate CG, the source S and the drain D is 0.5V. Accordingly, in the selected memory cell 110, the electrons in the source S move into the channel CH in the inverted state. Therefore, a current (cell current) flows from the drain D to the source S.

On the other hand, since 12 V is applied to the drain D, the potential of the floating gate FG is raised by the coupling between the drain D and the floating gate FG via the capacitance. Therefore, a high electric field is generated between the channel CH and the floating gate FG. Therefore, the electrons in the channel CH are accelerated to become hot electrons, and the hot electrons are injected into the floating gate FG as shown by an arrow A in FIG. As a result, the selected memory cell 1
Electric charges are accumulated in the ten floating gates FG, and 1-bit data is written and stored.

In the flash EEPROM 121, a configuration has been proposed in which the source voltage control circuit 132 is replaced with a source current control circuit. In this case, the potential of the common source line SL is controlled according to each operation mode shown in FIG. 11 by controlling the cell current value Id to a constant value by the source current control circuit. Also, Flash EEP
In the ROM 121 or the flash EEPROM 111, a configuration in which the drain voltage control circuit 133 is replaced with a drain current control circuit has also been proposed. In this case, by controlling the cell current value Id to a constant value by the drain current control circuit, the potential of the bit line BLm is controlled according to each operation mode shown in FIG. 11 or FIG.

In the flash EEPROM 121, the sources S of all the memory cells 101 are not connected to the common source line SL, but only the sources S of the memory cells 101 arranged in the row direction are connected to the common source line. There is also proposed a configuration for performing the above. In this case, a source line decoder is provided, one source line corresponding to the column address is selected, and the selected source line is connected to the source voltage control circuit 132.

By the way, in recent years, flash EEPROM
In order to improve the degree of integration, it is required to store not only binary (= 1 bit) of an erased state and a written state (= 1 bit) in a memory cell (multi-level storage operation). FIG. 15 shows a split gate type memory cell 1.
The characteristics of the potential Vfg of the floating gate FG and the cell current value Id at 01 and 111 are shown. Note that the floating gate potential Vfg
Is the potential of the floating gate FG with respect to the source S.

In the read mode, the control gate CG
Is applied with a constant voltage (= 4 V), the channel CH immediately below the control gate CG functions as a constant resistance. Therefore, the split gate memory cells 101, 1
Reference numeral 11 can be regarded as a series connection of a transistor including a floating gate FG, a source S and a drain D, and a constant resistance including a channel CH immediately below the control gate CG.

Therefore, in the region where the floating gate potential Vfg is less than a certain value (= 3.5 V), the characteristics of the transistor become dominant. Therefore, in the memory cells 101 and 111, the threshold voltage Vth (=) of the transistor constituted by the floating gate FG, the source S, and the drain D
In a region where the floating gate potential Vfg is smaller than 0.5 V), the cell current value Id becomes zero. Then, when the floating gate potential Vfg exceeds the threshold voltage Vth, the cell current value Id exhibits a characteristic that rises to the right. In the region where the floating gate potential Vfg exceeds 3.5 V, the control gate CG
Becomes dominant, and the cell current value Id is saturated.

The floating gate potential Vfg is the sum of the potential Vfgw generated by the charge stored in the floating gate FG in the write operation and the potential Vfgc generated by the coupling from the drain D (Vfg
= Vfgw + Vfgc). In the read operation, since the potential Vfgc is constant, the cell current value Id becomes the potential Vf
gw. In the write operation, the amount of charge of the floating gate FG can be controlled by adjusting the operation time.

Therefore, in the writing operation, the floating gate potential Vfg can be controlled by controlling the potential Vfgw by adjusting the operation time and controlling the charge amount of the floating gate FG. As a result, the cell current value Id in the read operation can be set arbitrarily. Therefore, as shown in FIG. 15, the area where the cell current value Id is less than 40 μA is the data value “11”, the area where the cell current value is 40 μA or more and less than 80 μA is the data value “10”, and the area where the cell current value Id is 80 μA or more is 120 μA.
An area smaller than the data value is associated with a data value “01”, and an area larger than 120 μA is associated with a data value “00”. In the write operation, the floating gate potential Vfg (= Va,
Vb, Vc) is the cell current value Id (= 40, 80,
The operation time is adjusted so as to have a value corresponding to 120 μA).

That is, the memory cell 10 in the erased state
Since electrons have been extracted from the floating gates FG of 1, 111, the state is the same as that storing the data value "00". At this time, the floating gate potential Vfg is higher than the potential Vc (= 2.5 V). Then, as the write operation is performed and the charges are accumulated in the floating gate FG, the floating gate potential Vfg decreases. Therefore, if the write operation is stopped when the floating gate potential Vfg becomes equal to or higher than Vb (= 1.5 V) and lower than Vc (= 2.5 V), the input data having the data value “01” is stored in the memory cells 101 and 111. It will be written. Further, the floating gate potential Vfg is changed to the threshold voltage Vth (=
If the write operation is stopped when the voltage becomes 0.5 V) or more and less than Vb, the data value “1” is stored in the memory cells 101 and 111.
This means that the input data of "0" has been written. If the write operation is stopped when the floating gate potential Vfg becomes lower than the threshold voltage Vth, the memory cell 101,
This means that the input data having the data value “11” has been written into the memory 111.

In this way, one memory cell 10
Four values (= 2 bits) can be stored in 1, 111. 2) Stacked Gate Memory Cell FIG. 16 shows a cross-sectional structure of the stacked gate memory cell 201. An N-type source S and a drain D are formed on a P-type single crystal silicon substrate 202. A first insulating film 2 is formed on the channel CH between the source S and the drain D.
The floating gate FG is formed through the gate line 03. The control gate C is provided on the floating gate FG via the second insulating film 204.
G is formed. Floating gate FG and control gate CG
Are stacked without shifting from each other. Therefore, the source S and the drain D have a symmetric structure with respect to each of the gates FG, CG and the channel CH.

FIG. 17 shows a stacked gate type memory cell 2.
1 shows the overall configuration of a flash EEPROM 221 using the same. In the flash EEPROM 221, FIG.
The difference from the flash EEPROM 121 using the split gate type memory cell 101 shown in FIG.

The memory cell array 122 includes a plurality of memory cells 201 arranged in a matrix. Source S of each memory cell 201 arranged in the column direction
Are connected to common bit lines BLa to BLz. The drains D of all the memory cells 201 are connected to a common drain line DL. The common drain line DL is connected to a common drain line bias circuit 222. The common drain line bias circuit 222 controls the potential of the common drain line DL according to each operation mode, as described later. The operation of the common drain line bias circuit 222 is controlled by the control core circuit 140.

In this specification, the names of the source S and the drain D in the split gate memory cell 101 and the stacked gate memory cell 201 are determined based on the read operation, and the higher potential in the read operation is used. The drain and the lower potential are called sources. In the writing operation and the erasing operation, the names of the source S and the drain D are the same as those in the reading operation.

Next, each operation mode (erase mode, write mode, read mode) of the flash EEPROM 221 will be described with reference to FIG. (A) Erasing Mode In the erasing mode, all the bit lines BLa to BLz are set to the open state, and the potentials of all the word lines WLm are set to the ground level. Common drain line bias circuit 2
Reference numeral 22 applies 12 V to the drains D of all the memory cells 201 via the common drain line DL.

As a result, an FN tunnel current flows, electrons in the floating gate FG are drawn to the drain D side, and the data stored in the memory cell 201 is erased.
This erase operation is performed on all the memory cells 201 connected to the selected word line WLm. still,
By simultaneously selecting a plurality of word lines WLa to WLz, an erase operation (block erase) can be performed on all the memory cells 201 connected to each word line.

(B) Write Mode In the write mode, the selected memory cell 201
12V is supplied to the word line WLm connected to the control gate CG, and the potentials of the other word lines (non-selected word lines) WLa to WL1 and WLn to WLz are set to the ground level. 5 V is supplied to the bit line BLm connected to the source S of the selected memory cell 201, and the other bit lines (unselected bit lines) BLa to
The potentials of BL1, BLn to BLz are set to the ground level. The common drain line bias circuit 222 holds the drains D of all the memory cells 201 at the ground level via the common drain line DL.

Then, the potential of the floating gate FG is raised by coupling from the control gate CG, and hot electrons generated near the source S are injected into the floating gate FG. As a result, the selected memory cell 2
In the floating gate FG 01, charges are accumulated, and 1-bit data is written and stored. (C) Read mode In the read mode, the selected memory cell 201
5V is supplied to the word line WLm connected to the control gate CG, and the potentials of the other word lines (non-selected word lines) WLa to WL1 and WLn to WLz are set to the ground level. The potentials of all bit lines BLa to BLm are set to the ground level. The common drain line bias circuit 222 applies 5 V to the drains D of all the memory cells 201 via the common drain line DL.

As a result, similarly to the case of the split gate memory cell 101, the current (cell current) flowing from the drain D to the source S is larger in the erased memory cell 201 than in the written memory cell 101. Become. Therefore, each memory cell 201 can store two values of the data value “1” in the erased state and the data value “0” in the written state.

By the way, a multi-value memory for storing multi-values in a flash EEPROM using the stacked gate type memory cell 201 has been proposed. FIG. 19 shows characteristics of the potential Vfg of the floating gate FG and the cell current value Id in the stacked gate memory cell 201. still,
The floating gate potential Vfg is equal to the floating gate F with respect to the source S.
G potential.

In the stacked gate type memory cell 201, since the floating gate FG and the control gate CG are stacked without being shifted from each other, the channel CH immediately below the control gate CG as in the split gate type memory cell 101 is not used. It does not function as a constant resistance, but only functions as a transistor. Therefore, in a region where the floating gate potential Vfg is lower than the threshold voltage Vth (= 1 V) of the memory cell 201, the cell current value Id becomes zero. When the floating gate potential Vfg exceeds the threshold voltage Vth, the cell current value Id is directly proportional to the floating gate potential Vfg.

Therefore, the stacked gate type memory cell 2
01, the potential Vf is controlled by adjusting the operation time of the write operation to control the amount of charge of the floating gate FG.
By controlling gw, the floating gate potential Vfg can be controlled. Therefore, as shown in FIG. 19, the region where the cell current value Id is less than 40 μA is defined as the data value “11”, 40 μA.
The data value of “10”, 80 μA
The data value of “01”, 12
Regions of 0 μA or more and less than 160 μA are respectively associated with data values “00”. Then, in the write operation,
The floating gate potential Vfg (= Va, Vb, Vc, Vd) varies with the cell current value Id (= 40, 80, 120, 160).
The operation time is adjusted so as to have a value corresponding to μA).
In this way, quaternary (= 2 bits) data can be stored in one memory cell 101, 201.

Incidentally, in order to perform a multi-value storage operation in a flash EEPROM, it is necessary to precisely control the write state by precisely controlling the floating gate potential Vfg of the memory cells 101, 111, 201 during the write operation. Indispensable. That is, it is important to accurately set the floating gate potential Vfg of the memory cells 101 and 201 after writing to a desired value. As a method therefor, a verify writing method is generally used at present.

In the verify write method, a write operation is first performed on the memory cells 101, 111, and 201 for a fixed period (several hundreds of nanoseconds to several microseconds), and then a read operation for verification (verify read) is performed. Operation). Subsequently, the data value to be written in the write operation is compared with the data value read in the read operation (that is, the data value actually written in the write operation) (comparison operation). Here, if the data value to be written does not match the read data value, the writing operation is performed again for a fixed time.
As described above, the cycle of the write operation → the verify read operation → the comparison operation is repeated until the data value to be written matches the read data value.

With respect to such a multi-value storage memory and a verify writing method, see, for example, Japanese Patent Application Laid-Open No. 4-57294.
No. (G11C16 / 04).

[0048]

As described above, in order to write multi-valued data into a memory cell, a cell current region is made to correspond to multi-valued data, and the potential of the floating gate FG corresponding to the cell current is changed. This is done by controlling. FIG. 5 shows a distribution of cell current at the time of writing required for a four-valued EEPROM. Although the cell current varies from cell to cell, the cell current for each cell corresponds to the cell corresponding to the quaternary data. It is necessary to stay within each region of the current.

Similarly, FIG. 6 shows the distribution of the cell current at the time of writing required for an 8-valued EEPROM, and FIG. 7 shows the distribution of the cell current at the time of writing required for a 16-valued EEPROM. As described above, in order to write multi-valued data in a memory cell, it is necessary to set the cell current region narrower as the number of data increases.

However, in the case of the multi-value storage type memory cell, the data retention characteristics of the memory cell in an unattended state, the disturbance resistance of a non-selected memory cell at the time of rewriting, the endurance characteristics of the selected memory cell, and the like vary, so that writing is not performed. The data of the memory cell performed fluctuates, and if the fluctuation is large, the fluctuation of the cell current for each cell becomes large. Then, for example, as shown in FIG. 8, the cell current of each cell does not fit in each area of the cell current corresponding to the multi-value data, and overlaps with the adjacent area, so that reading becomes impossible. There is a problem.

This problem becomes more serious as the number of multivalued data increases. An object of the present invention is to improve the yield as a semiconductor memory device.

[0052]

According to a first aspect of the present invention, there is provided a semiconductor memory device in which a plurality of write states are set in a memory cell to store multi-valued data, and the set level of the write state is set at a predetermined level. means for varying is provided, a predetermined write
Defective memory cell set to programming level
If the product is a product,
By changing the setting level more, the quality is improved . According to a second aspect of the present invention, the means for changing the set level includes a set level switching circuit and a control circuit for changing a write state of the memory cell in accordance with an output from the switching circuit.

According to a third aspect of the present invention, in the semiconductor memory device, the means for changing the set level comprises a set level switching circuit, and changes a write state to a memory cell in accordance with an output from the switching circuit. According to a fourth aspect of the present invention, in the semiconductor memory device, the setting level switching circuit includes a signal switching circuit and a logic circuit that outputs a signal corresponding to a state of a signal input through the signal switching circuit.

According to a fifth aspect of the present invention, in the semiconductor memory device, the signal switching circuit changes a state of a signal input to the logic circuit by switching a bonding terminal.
Further, in the semiconductor memory device according to claim 6, the signal switching circuit comprises:
The state of the signal input to the logic circuit is changed depending on the state of the fuse being cut. According to a seventh aspect of the present invention, in the semiconductor memory device, the signal switching circuit includes a memory in which a state of a signal input to the logic circuit can be written.

Further, in the semiconductor memory device according to the present invention, the write state is changed by setting a plurality of gate potentials of the memory cell to correspond to each multi-valued data. According to a ninth aspect of the present invention, in the semiconductor memory device, the memory cell has at least a source, a drain, and a floating gate. It is made to correspond.

According to a tenth aspect of the present invention, the set level of a plurality of memory cells constituting the memory cell array is changed at a time by means for changing the set level. For example, when a memory cell for storing 16-valued data is initially designed and it is found that it is not possible to read and write 16-valued data due to variations in device characteristics of the memory cell, the setting level switching circuit changes the setting level from 16-valued data. Switch to 8 values. When the set level becomes eight-valued, for example, there is some margin in the width of each area of the cell current corresponding to the eight-valued data, and it is possible to absorb the variation in the device characteristics of the memory cell at 16 values.

Thus, a defective 16-level memory cell can be reproduced as an 8-level memory cell.

[0058]

BEST MODE FOR CARRYING OUT THE INVENTION

(First Embodiment) A first embodiment of the present invention will be described with reference to FIGS. However, the same parts as those in the prior art are denoted by the same reference numerals, and detailed description is omitted. FIG. 1 shows the entire configuration of the flash EEPROM 1.
In this embodiment, the structure of the memory cell may be either a split gate type or a stacked gate type.

The present embodiment is different from the conventional flash EEPROM shown in FIG. 10, FIG. 13 or FIG. 17 in that a multi-level switching circuit 2 for inputting a signal to a control core circuit 140 is provided. It is. FIG. 2 shows a detailed configuration of the multi-value level switching circuit 2. 1
Four NOR gates 3 to 6 are provided to output signals corresponding to the respective outputs of 6 values, 8 values, 4 values, and 2 values. These NOR gates 3 to 6 Signals from the output terminals 8 and 9 are input directly or via an inverter.

The switching circuit 7 includes two contacts 10 and 11 having the potential VDD and two contacts 12 and 13 having the potential VSS.
As shown in Table 1, four types of signals are output from the two output terminals 8 and 9 by switching between the contacts 10 and 13 and the two output terminals 8 and 9.
In the following description, the potential VDD is referred to as “High” for convenience.
(H) "and the potential VSS is" Low (L) ".

[0061]

[Table 1]

Each of the contacts 10 to 13 and the output terminals 8 and 9 of the switching circuit 7 is specifically constituted by a bonding pad, and the connection state is switched by connecting the pads with wiring. As described above, the switching method using the bonding pads cannot be inspected and switched for each chip during assembly, but is suitable for switching a large number of chips to the same multilevel level after the product is completed.

The signal at the output terminal 8 is input to one input of the NOR gate 3 via the inverter 14, and the signal at the output terminal 9 is input to the other input via the inverter 15. One input of the NOR gate 4 has:
The signal at the output terminal 8 is input via the inverter 14,
The signal at the output terminal 9 is directly input to the other input unit.

The signal of the output terminal 8 is directly input to one input portion of the NOR gate 5, and the signal of the output terminal 9 is input to the other input portion via the inverter 15. N
The signal of the output terminal 8 is directly input to one input portion of the OR gate 6, and the signal of the output terminal 9 is directly input to the other input portion. In such a configuration, the switching circuit 7
The NOR gates 3 to 6 have four types of outputs as shown in Table 2 and are input to the control core circuit 140 according to the switching state (patterns A to D) of the respective contacts.

[0065]

[Table 2]

The control core circuit 140 switches the number of levels according to the state of the signal input from the multi-level switching circuit 2. Specifically, the flash EEPROM shown in FIG.
When OM1 is designed to correspond to 16 values and switches this to 8 values, the control core circuit 140
Each circuit designed corresponding to the value, that is, row decoder 123, column decoder 124, address buffer 126, address latch 127, input buffer 12
9, control is performed such that the sense amplifier group 130, the output buffer 131, the source voltage control circuit 132, the drain voltage control circuit 133, and the gate voltage control circuit 134 operate according to the 8-level data.

For example, in order to determine 16 values in the write and read operations, one having different thresholds is used.
Five sense amplifiers are incorporated in the sense amplifier group 130. Among them, only the sense amplifiers having a threshold for judging eight values are selected, and the sense amplifiers having other thresholds are not selected. State. Further, the row decoder 123, the column decoder 124, the address buffer 1
26 and the address latch 127, one of the address pins is set in a non-selected state, thereby reducing the number of decodes by the address to half.

In the input buffer 129 and the output buffer 131, half of the input / output of the data pin 128 is set to the unused state. The same control is performed when switching from eight values to four values or when switching from four values to two values. Also, as described in parentheses in FIG. 1, the signal from the multi-level switching circuit 2 is directly transmitted to the row decoder 123 and the column decoder 12 without passing through the control core circuit 140.
4, address buffer 126, address latch 127,
The input buffer 129, the sense amplifier group 130, the output buffer 131, the source voltage control circuit 132, the drain voltage control circuit 133, and the gate voltage control circuit 134 are input to the input buffer 129, and the number of levels according to the state of the input signal It may be designed so that each circuit operates so as to switch to. The specific operation of each circuit is the same as described above.

(Second Embodiment) A second embodiment of the present invention
Will be described with reference to FIG. However, the second embodiment differs from the first embodiment only in the specific configuration of the switching circuit. The switching circuit 16 has one output terminal 8 connected to the potential VDD via a first fuse 17 and the other output terminal 9 connected to the potential VSS via a second fuse 18. Then, as shown in Table 1, four types of signals are output from the output terminals 8 and 9 by appropriately turning on and off the first and second fuses 17 and 18.
In this way, by allowing the multilevel level to be switched by the fuse, it is possible to inspect and switch each chip at the wafer stage during assembly, and to switch to a different number of levels for each chip.

(Third Embodiment) A third embodiment of the present invention
Will be described with reference to FIG. However, the third embodiment differs from the first embodiment only in the specific configuration of the switching circuit. The switching circuit 19 includes a first EEPR
One output terminal 8 is connected to the OM 20 and the second EEP
The other output terminal 9 is connected to the ROM 21. Then, by writing a state of “1” or “0” (H or L) in the first and second EEPROMs 20 and 21,
The states of the patterns A to D in Table 1 are created.

First and second EEPROMs 20, 21
Is V indicating that a normal power supply voltage has been applied to the chip.
It is activated upon receiving the DDOK signal. Since it is an EEPROM, it can be rewritten, can be inspected and switched for each chip at the wafer stage during assembly, and can be switched to a different number of levels for each chip. In addition, the switching operation is easier than the fuse method as in the second embodiment.

It should be noted that an EPROM may be used instead of the EEPROM. In short, ROM to which data can be written
Should be fine. In the above embodiment, when the multilevel level is switched, switching to a lower level than that level has been mainly described. However, the present invention is not limited to this. For example, four levels are set. It is also possible to control such a device to change it to eight values because of its good device characteristics.

Further, although a memory having a maximum of 16 values is assumed, it is needless to say that the present invention can be applied to a multi-value memory having more than 16 values.

[0074]

According to the present invention, since the quality of the memory cell can be improved according to the state of the device characteristics, the yield of the semiconductor memory device storing multi-value data can be improved.

[Brief description of the drawings]

FIG. 1 shows a flash EEPROM according to an embodiment of the present invention.
It is a block circuit diagram of M.

FIG. 2 is a circuit diagram of a multi-value level switching circuit according to the first embodiment of the present invention.

FIG. 3 is a multi-level level switching circuit diagram according to a second embodiment of the present invention.

FIG. 4 is a circuit diagram of a multi-value level switching circuit according to a third embodiment of the present invention.

FIG. 5 is a cell current distribution diagram of a quaternary memory.

FIG. 6 is a cell current distribution diagram of an eight-valued memory.

FIG. 7 is a cell current distribution diagram of a 16-valued memory.

FIG. 8 is a cell current distribution diagram of an eight-valued memory for explaining a problem of the conventional embodiment.

FIG. 9 is a sectional view of a split gate memory cell.

FIG. 10 is a block diagram of a conventional flash EEPROM.

FIG. 11 is an explanatory diagram of a conventional mode.

FIG. 12 is a cross-sectional view of another split gate memory cell.

FIG. 13 is a block diagram of another conventional flash EEPROM.

FIG. 14 is an explanatory diagram of another conventional embodiment.

FIG. 15 is a characteristic diagram of a split gate memory cell.

FIG. 16 is a cross-sectional view of a stacked gate memory cell.

FIG. 17 is a block diagram of a conventional flash EEPROM.

FIG. 18 is an explanatory diagram of a conventional embodiment.

FIG. 19 is a characteristic diagram of a stacked gate memory cell.

[Explanation of symbols]

 2 Multi-value level switching circuit (setting level switching circuit) 3-6 NOR gate (logic circuit) 7, 16, 19 Switching circuit (signal switching circuit) 8, 9 Output terminal (bonding terminal) 10-13 Contact (bonding terminal) 14, 15 Inverter (logic circuit) 17 First fuse 18 Second fuse 20 First EEPROM 21 Second EEPROM 140 Control core circuit (Control circuit)

Claims (10)

(57) [Claims] 1. A method for setting a plurality of write states in a memory cell and storing multi-valued data, comprising means for changing a set level of the write state ,
The memory cell set to the set level of the predetermined write state
If the tool is defective, change the set level.
A semiconductor memory device which is made non-defective by changing a set level by means . 2. The apparatus according to claim 1, wherein said means for changing the set level comprises a set level switching circuit and a control circuit for changing a write state to a memory cell in accordance with an output from the switching circuit. 13. The semiconductor memory device according to claim 1. 3. The semiconductor device according to claim 1, wherein said means for changing the set level comprises a set level switching circuit, and changes a write state to a memory cell in accordance with an output from the switching circuit. Storage device. 4. The setting level switching circuit according to claim 2, wherein the setting level switching circuit includes a signal switching circuit and a logic circuit that outputs a signal according to a state of a signal input through the signal switching circuit. 13. The semiconductor memory device according to claim 1. 5. The semiconductor memory device according to claim 4, wherein said signal switching circuit changes a state of a signal input to said logic circuit by switching a bonding terminal. 6. The semiconductor memory device according to claim 4, wherein said signal switching circuit changes a state of a signal input to said logic circuit according to a cut state of a fuse. 7. The semiconductor memory device according to claim 4, wherein said signal switching circuit comprises a memory in which a state of a signal input to said logic circuit can be written. 8. The method according to claim 1, wherein a write state is changed by setting a plurality of gate potentials of the memory cell to correspond to each of multi-valued data. 13. The semiconductor memory device according to claim 1. 9. The memory cell, comprising: at least a source;
9. The semiconductor memory device according to claim 8, comprising a drain and a floating gate, wherein a write state is changed by setting a plurality of potentials of the floating gate to correspond to each of multi-value data. 10. The apparatus according to claim 1, wherein said set level changing means changes the set levels of a plurality of memory cells constituting a memory cell array at one time.
10. The semiconductor memory device according to claim 1.