JPH11126156A - Programmable device and arithmetic processing method therein - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make realizable a plurality of circuits regarding the evaluation of a computer architecture without lowering the processing capability by performing the arithmetic processing of a specified multiplying circuit. SOLUTION: The constituent bits (32 bits) constituting a multiplier are divided into two-bit parts, which are multiplied by 0, 1, 2, and 3. When the multiplicant is multiplied by '3', the value obtained by multiplying the multiplicand by -1 is outputted and at the same time, 1 is added to a partial term where the multiplicand is multiplied by a high-order partial product (the number obtained by multiplying the partial product by '4' is handled). Thus, the value obtained by multiplying the multiplicand by '-1' is outputted and at the same time, 1 is added to the partial term where the multiplicand is multiplied by the high- order partial product, so that the value obtained by multiplying the multiplicand by '1' is subtracted from the value obtained by multiplying the multiplicand by '4'. Consequently, the result of the multiplication of the multiplicand by '3' can be obtained. Consequently, logic array blocks needed for the operation can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an arithmetic processing method in a programmable device. More specifically, the present invention relates to an improvement in an arithmetic processing method in a programmable device capable of performing arithmetic processing at high speed.

[0002]

2. Description of the Related Art Conventionally, in order to evaluate a computer architecture, a method of actually manufacturing an evaluation board with hardware has been used. In the method using the evaluation board as described above, a programmable device whose internal circuit can be changed by a program is generally used in the arithmetic processing unit. As an example of a method of realizing a multiplication circuit with the programmable device, an addition method is used. The method by has been taken.

As another example of a method of realizing a multiplication circuit by a programmable device, as shown in FIG. 2, constituent bits constituting a multiplier are divided into two bits, and each bit is divided into two bits (hereinafter referred to as a multiplicand). Subterms 0, 1, 2,
There is a method of multiplying by 3 and integrating the partial products to obtain a final result. FIG. 2 shows a case where 10 is multiplied by 99 and the result is output.

[0004]

However, if the multiplication circuit is realized by a conventional addition method, a data type conforming to the single precision of IEEE-754 (exponent part 8 bits, sign 1 bit, mantissa part 24 bits) is obtained. Taking an example of an arithmetic circuit for processing, the first stage requires 12
8 Logic Array Blocks (hereinafter simply referred to as LAB) are required, and 64, 32, 16, 8, and 4 LABs are used for each stage from the second stage onward.
Requires 52 LABs. In this case, most of the LAB of the programmable device must be multiplied by the multiplication circuit, and it is difficult to incorporate other circuits.

Further, as shown in FIG. 2, when the multiplication circuit is realized by a method of dividing the constituent bits, there is an advantage that the LAB to be used can be reduced as compared with the above-mentioned addition method, but the selector is not shown. X1, X2, X3 of 2
3 inputs and 2 inputs Y0 and Y1 for selection, that is, a total of 5 inputs
Input is required and a 4-input lookup table (Lo
ok up table (hereinafter simply referred to as LUT) cannot be realized efficiently. Specifically, there is a problem that two logic elements (hereinafter simply referred to as LE) are required to realize a three-input selector.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems, and it is an object of the present invention to provide a programmable device capable of realizing a plurality of circuits related to evaluation of a computer architecture without reducing the processing capability and an arithmetic processing in the programmable device. It is an object to provide a method.

Another object of the present invention is to provide a programmable device capable of efficiently realizing a multiplication circuit even in a 4-input LUT and an arithmetic processing method in the programmable device.

[0008]

According to a first aspect of the present invention, there is provided a method for processing a programmable device according to the present invention. Is divided into two bits, and the sub-terms 0,
The point is that when multiplying by 1, 2, -1 and multiplying by -1 are performed, a value obtained by multiplying the multiplicand by -1 is output, and at the same time, 1 is added to a partial term by which the multiplicand is multiplied by a higher partial product. In this way, outputting a value multiplied by -1 is equivalent to inverting the sign of the multiplicand, and therefore, when outputting, it is sufficient to simply invert each bit of the multiplicand and output.

Further, by adding a value of -1 to the partial term by which the multiplicand is multiplied by the higher partial product and adding 1 to the output, this is equivalent to multiplying the multiplicand by 3 and processing the input value of the multiplicand. , The multiplicand can be multiplied by 3 without adding a new input element.

A feature of the programmable device according to the present invention is that, as described in claim 2, constituent bits constituting a multiplier are divided by 2 bits, and partial terms 0, 1, and 2 are divided into each of the 2 bits to be a multiplicand. , -1 and multiplying by -1 constitutes a multiplying circuit by outputting a value obtained by multiplying the multiplicand by -1 and adding 1 to a partial term for multiplying the multiplicand by a higher partial product. On the point. As described above, when multiplying by −1, a value obtained by multiplying the multiplicand by −1 is output, and at the same time, a multiplication circuit is configured by adding 1 to a partial term by which the multiplicand is multiplied by a higher partial product. The required logic array blocks can be reduced.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a programmable device and an operation method in the programmable device according to the present invention will be described below. FIG. 1 is a block diagram and a circuit diagram showing an embodiment of a multiplication circuit of a programmable device according to the present invention. In the following description, an arithmetic circuit that processes a data type conforming to the single precision of IEEE-754 (exponent part 8 bits, sign 1 bit, mantissa part 24 bits), that is, the number of bits constituting a multiplier is 3
A case of performing an operation of multiplying 10 by 99 will be described as an example of the operation by taking the case of 2 bits as an example.

Hereinafter, an operation method in the multiplication circuit of the programmable device will be described. First, the constituent bits (32 bits) constituting the multiplier are divided into two bits, and each two bits are multiplied by 0, 1, 2, and 3. Here, the multiplied “0”, “1”, “2”, and “3” are called partial terms, and each of these products is called a partial product. here,
When multiplying the multiplicand by "3", a value obtained by multiplying the multiplicand by -1 is output, and at the same time, the partial term by which the multiplicand is multiplied by the higher partial product (the number obtained by multiplying the partial product by "4") is output. Add 1. As described above, a value obtained by multiplying the multiplicand by “−1” is output, and at the same time, 1 is added to the partial term by which the multiplicand is multiplied by the upper partial product, whereby the value obtained by multiplying the multiplicand by “4” is changed to “1” by the multiplicand. Is subtracted, and as a result, a value obtained by multiplying the multiplicand by “3” can be obtained.

In order to obtain a value obtained by multiplying the multiplicand by "-1", a two's complement, that is, a value obtained by inverting each bit of a given multiplicand and adding "1" inverts the sign of the multiplicand. If it is used, the number of bits required for the operation can be reduced.

A case in which a programmable device having a multiplication circuit formed by such an operation method is used for a 4-input LUT will be described below. In the four-input LUT, two of the inputs (X1 and X2 in FIG. 1) are set as inputs of the multiplicand. At this time, one of the inputs inputs the multiplicand as it is, and the other inputs the multiplicand shifted one bit to the left.

Then, the remaining two inputs, that is, Y in FIG.
The sub-terms "0", "1",
Select "2" or "-1". Selecting the sub-term "-1" is equivalent to inverting and outputting each bit of the multiplicand. Therefore, since it is only necessary to process and output the input value of the multiplicand, it is not necessary to add a new input element as in the related art.

As described above, according to the programmable device of the present invention, since it is not necessary to add an input element, it is only necessary to add 1 LE to each bit, and the 4-input L is efficiently provided.
Can be used for UT.

By using the programmable device configured as described above, it is no longer necessary to perform an addition for obtaining a value obtained by multiplying the multiplicand by "3" in the first stage as in the prior art. Eliminate delays.
Also, unlike the conventional case, it is necessary to calculate a partial term of a multiplier by which each of the partial products is multiplied.
It is 6 bits, which is about one half of the conventional value.

For example, in the case of 32 bits, which is the same as the conventional case, 32 LAB, 16 LAB, 8 LAB, and 8 LAB are sequentially added to an adder that adds 64 LAB in the first stage and 16 terms obtained in the first stage.
4 LABs are required, for a total of 124 LABs. That is,
As compared with the conventional 252 LAB, the number of logic array blocks required for the operation can be reduced. Moreover,
The processing speed and processing capacity do not decrease.

As described above, according to the programmable device of the present invention, it is possible to reduce the number of logic array blocks required for the multiplication circuit. Even when various circuits used for the above are mounted on a single substrate, it is not necessary to separately provide a control circuit, and an effect that a control circuit can be mounted in a programmable device can be obtained.

[0020]

According to the operation method of the programmable device of the present invention, the operation of the multiplication circuit is performed by dividing the constituent bits constituting the multiplier by two bits, and dividing the sub-items 0 and 1 into each of the two bits to be the multiplicand. , 2, -1. When multiplying by -1, a value obtained by multiplying the multiplicand by -1 is output. At the same time, 1 is added to the partial term by which the multiplicand is multiplied by a higher partial product. Logic array blocks can be reduced.

Further, according to the programmable device of the present invention, the constituent bits constituting the multiplier are divided into two bits, and the sub-terms 0, 1,
Multiply by 2, -1. When multiplying by -1, the multiplicand is -1.
The multiplication circuit is constructed by adding a 1 to the multiplicand multiplied by the higher partial product at the same time as outputting the value multiplied by. Therefore, it is effectively used for a 4-input LUT without increasing the number of input elements. can do.

[Brief description of the drawings]

FIG. 1 shows a block diagram and a circuit diagram of an embodiment of a multiplication circuit of a programmable device according to the present invention.

FIG. 2 shows a block diagram and a circuit diagram of an example of a conventional multiplication circuit of a programmable device.

[Explanation of symbols]

 X1 input X2 input Y0 input Y1 input

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Taihei Yamamoto, Inventor 436-5 Ichijokami-ru-Verita-Tomita-cho, Higashi-Horikawa-dori, Kamigyo-ku, Kyoto Photographic Chemistry Co., Ltd.

Claims (2)

[Claims] In the arithmetic processing method of a programmable device, the arithmetic processing of a multiplying circuit is performed by dividing constituent bits constituting a multiplier by two bits, and sub-terms 0, 1, 2, -1 are assigned to each of the two bits to be a multiplicand. And multiplying the multiplicand by -1 by outputting a value obtained by multiplying the multiplicand by -1 and simultaneously adding 1 to a partial term by which the multiplicand is multiplied by a higher partial product. Method. 2. The constituent bits constituting a multiplier are divided into two bits at a time, and the sub-terms 0,
A multiplication circuit is constructed by multiplying 1, 2, -1 and multiplying by -1 by outputting a value obtained by multiplying the multiplicand by -1 and simultaneously adding 1 to a partial term by which the multiplicand is multiplied by a higher partial product. A programmable device, comprising: