JPH11122561A - Matrix video display device and its drive method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide the matrix type video display device and its drive method in which display quality of the video display device is enhanced at a low cost. SOLUTION: A video signal is given to 1st to 4th 1st-stage and 2nd-stage sample-and-hold circuits 11-14, and 21-24, in which the video signal is converted into pluralities of phase expansion video signals, and each of them is written simultaneously to display pixels 9 consecutive by number of phases in the horizontal direction of a matrix video display device 5 to compress the band width of a video signal A with respect to a required write time of the matrix video display device 5. In this case, the sequence of the video data of the video signal and the horizontal scanning direction are inverted for each horizontal period so that a sum of a time differences of the sampling timing between the 1st stage an 2nd stage differential amplifier circuits for two adjacent horizontal periods is equal between phases and the inter-phase deviation of the time difference is suppressed to be less than the same deviation by one horizontal period or below in a time longer than the horizontal period.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a matrix type image display device such as a liquid crystal display device and a driving method thereof.

[0002]

2. Description of the Related Art A matrix type image display device such as a liquid crystal display device has been widely used in the market as a multimedia image display terminal. Particularly, in recent years, with the need for higher resolution of video display of video display terminals, higher definition of matrix type video display devices has been achieved.

[0003] First, a conventional matrix-type image display device will be described with reference to FIGS.

[0004] A conventional matrix type image display device is shown in FIG.
As shown in FIG. 4, the video signal generator 1, the phase expansion unit 2, the synchronization signal generator 3, the timing signal generator 25, and the matrix type video display device 5 are provided.

The matrix type video display device 5 comprises a horizontal scanning circuit 26, a vertical scanning circuit 7, an analog switch 8, and display pixels 9.

The phase developing section 2 is composed of first to fourth first-stage sample-hold circuits 11 to 14 and first to fourth second-stage sample-hold circuits 21 to 24.
Each of the first-stage and second-stage sample-hold circuits having a two-stage configuration is provided in parallel with the same number as the number of phases of the phase-developed video signal.

[0007] The video signal generator 1 and the phase expansion unit 2 are connected by a video signal line 29, and the synchronization signal generator 3 and the timing signal generator 25 are connected by a synchronization signal line 33.
The phase expansion section 2 and the timing signal generator 25 are
Control signal line 3 of the first stage sample and hold circuit
The phase expansion unit 2 and the matrix-type video display device 5 are connected by phase expansion video signal lines 311 to 314 of the first to fourth second-stage sample-hold circuits, and the timing signal generator 25 The matrix type display device 5 is connected to a horizontal start signal line 34, a horizontal clock signal line 35, a vertical start signal line 36, and a vertical clock signal line 37.

In the matrix type video display device 5, the horizontal scanning circuit 26 is connected to a horizontal start signal line 34 and a horizontal clock signal line 35, and the vertical scanning circuit 7 is connected to a vertical start signal line 36 and a vertical clock signal line 37. It is connected. The display pixel 9 and the vertical scanning circuit 7 are connected to a conductor 27.
And the display pixel 9 and the analog switch 8 are connected by analog switch control signal lines 381 to 38m. Further, the analog switch 8 is connected to phase-developed video signal lines 311 to 314 of the first to fourth second-stage sample-hold circuits.

In the phase expansion section 2, the video signal line 29 and the control signal lines 321 to 321 of the first to fourth first-stage sample-hold circuits are respectively connected to the first to fourth first-stage sample-hold circuits 11 to 14. 324 are connected. The first to fourth first-stage sample-and-hold circuits 1
1st to 14th and first to fourth second-stage sample-hold circuits 2
1 to 24 are connected by output video signal lines 301 to 304 of the first to fourth first-stage sample and hold circuits, respectively. Further, the first to fourth second-stage sample / hold circuits 21 to 24 include a common control signal line 325 of the second-stage sample / hold circuit and a phase-developed video signal line 311 of the first to fourth second-stage sample / hold circuits. ~ 314
Is connected.

A high-resolution video signal A output from the video signal generator 1 is phase expanded by first to fourth first and second stage sample-hold circuits 11 to 14 and 21 to 24. The four phases obtained by phase development by the part 2
The phase-developed video signals B21 to B24 of the first to fourth second-stage sample-hold circuits are input to the matrix-type video display device 5. Then, the phase-developed video signals B21 to B24 of the first to fourth second-stage sample-hold circuits are simultaneously inputted,
At the same time, the analog switch 8 simultaneously writes data into the display pixels 9 continuous for four phases in the horizontal direction.

On the other hand, the output from the synchronization signal generator 3
The synchronization signal synchronized with the video signal A is input to the timing signal generator 25. The timing signal generator 25 includes: first to fourth first-stage sample-and-hold circuit control signals C11 to C14 and a common control signal C2 of the second-stage sample-and-hold circuit, which match the timing of the synchronization signal; A horizontal start signal and a horizontal clock signal for controlling the horizontal scanning of the horizontal scanning circuit 26 of the device 5 and a vertical start signal and a vertical clock signal for controlling the vertical scanning of the vertical operation circuit 7 are output.

The horizontal start signal and the vertical start signal are signals for determining the horizontal and vertical scanning start positions on the display screen of the matrix type video display device 5, respectively. The horizontal clock signal and the vertical clock signal are , Signals for performing horizontal scanning and vertical scanning of the matrix type video display device 5, respectively.

In the phase developing section 2, the first to fourth first-stage sample-hold circuits 11 to 14 receive the video signal A and the control signals C11 to C14 of the first to fourth first-stage sample-hold circuits, respectively. Output video signals B11 to B11 of the first to fourth first-stage sample-hold circuits, respectively.
14 is output. The first to fourth second-stage sample-hold circuits 21 to 24 receive the output video signals B11 to B14 of the first to fourth first-stage sample-hold circuits and the common control signal C2 of the second-stage sample-hold circuit, respectively. , And outputs the phase-developed video signals B21 to B24 of the first to fourth second-stage sample-hold circuits.

Next, a method of phase development of the video signal A will be described. The horizontal period U of the video signal A includes a horizontal video period V and a horizontal blanking period W during the vertical video period as shown in FIG.

In the video signal A, n is the number of effective dots in the horizontal direction of the display screen of 5 of the matrix type video display device, and n is a multiple of the number of phases, that is, a multiple of 4, and the time is S
N pieces of video data from 1 to Sn are inserted. Here, S1 is the first video data in horizontal scanning in non-interlaced scanning, and i is n.
The video data Si + 1 is a video data Si + 1 that is temporally slower than the video data Si and temporally adjacent to the video data Si.

The video signal A is supplied to the first to fourth sample-hold circuits 11 to 14 by the first to fourth first-stage sample-hold circuits 11 to 14, respectively.
Control signal C1 of the first stage sample and hold circuit
At the timing of 1 to C14, the first to the first shown in FIG.
Output video signal B1 of the fourth first-stage sample-hold circuit
1 to B14. At this time, the first to fourth 1
Output video signals B11 to B1 of the stage sample-hold circuit
4, k is a natural number less than or equal to n / 4, and S4
Video data represented by k-3, S4k-2, S4k-1 and S4k are inserted in a state shifted from each other as shown in FIG.

The output video signals of the first to fourth first-stage sample-hold circuits are further respectively subjected to second-stage sample-hold circuits 21 to 24 at the timing of the common control signal C2 of the second-stage sample-hold circuit.
These are converted into phase-developed video signals B21 to B24 of the first to fourth second-stage sample-hold circuits shown in FIG. 4, respectively. As a result, the video data S4k-3, S4k-2, S4k-1, and S4k are respectively included in the phase expanded video signals B21 to B24 of the first to fourth second-stage sample-hold circuits.
k are all inserted at the same timing as shown in FIG.

By the above series of operations, the video signal A becomes the first
To the phase expanded video signals B21 to B24 of the fourth to second sample-hold circuits.

Next, a method of writing the phase expanded video signals B21 to B24 of the first to fourth second-stage sample and hold circuits in the matrix type video display device 5 will be described.

The phase-developed video signals B21 to B24 of the first to fourth second-stage sample-and-hold circuits are input to the video display device 5 in parallel, and are horizontally continuous and have the same number of display pixels 9 as the number of phases. Are written at the same time. For horizontal scanning, m =
n / 4, the control signal H of the analog switch
In the order from 1 to Hm, starting from H1 and ending at Hm, as shown in FIG. 4, analog switches for four phases that are continuous in the horizontal direction are simultaneously turned on. Here, the analog switch control signal H
When k is the ON control timing, the respective video data S4k-3 and S4k- inserted into the phase expanded video signals B21 to B24 of the first to fourth second-stage sample-hold circuits.
2, S4k-1 and S4k are (4k) in the horizontal direction from the horizontal scanning start direction of the display screen of the video display device 5, respectively.
-3) -th, (4k-2) -th, (4k-1) -th and 4k-th display pixels 9 are written. That is, the video data of the video signal A is written to the display pixel 9 of the video display device 5 at the horizontal position that matches the timing of the video data.

At the same time, the highest frequency included in the phase-developed video signals B21 to B24 of the first to fourth second-stage sample-hold circuits is one-fourth of the number of phases of the highest frequency included in the video signal A, that is, 1/4. By setting the number of phases so that the highest frequency included in the phase-developed video signals B21 to B24 of the first to fourth second-stage sample-hold circuits is equal to or lower than the highest writable frequency of the video signal of the video display device 5, Thus, the writing of the video data of the video signal A to the video display device 5 is realized.

Although the case where the phase expanded video signal has four phases has been described here, the number of phases is generally arbitrary.

By the above-described series of operations, a video display having a resolution corresponding to the resolution of the video signal A and a normal display pattern is realized by the high resolution video signal A in the matrix type video display device 5. Because

[0024]

In the above-mentioned conventional driving method, the first to fourth first-stage sample-hold circuits 11 to 1 are used.
4, the time difference between the output video signals B11 to B14 of the first to fourth first-stage sample-hold circuits and the common control signal C2 of the second-stage sample-hold circuit is different.

Generally, output video signals B11 to B14 of the first to fourth first-stage sample-hold circuits output from the first to fourth first-stage sample-hold circuits 11 to 14, respectively.
Signal level decreases with time due to the influence of leakage resistance and the like existing in the sample and hold circuit.

Therefore, if the time difference is different between the phases, 2
Common control signal C2 of the sample-and-hold circuit
Data S4 of the video signal A at the time when the
The ratios of the signal levels of the output video signals B11 to B14 of the first to fourth first-stage sample / hold circuits to the signal levels of k-3, S4k-2, S4k-1 and S4k are different.

Since the phase-developed video signals B21 to B24 of the first to fourth second-stage sample-hold circuits are outputs of the first to fourth second-stage sample-hold circuits 21 to 24,
As a result, video data S4k-3, S4 of video signal A
k-2, S4k-1 and S4k, the phase-expanded video signals B21 to B21 of the first to fourth second-stage sample-hold circuits.
The ratio of the signal level of B24, that is, the deviation of the phase-developed video signals B21 to B24 of the first to fourth second-stage sample-hold circuits also differs between the phases.

The phase-developed video signals B21 to B24 of the first to fourth second-stage sample-hold circuits are continuous with the matrix type video display device 5 in the horizontal direction by the same number as the number of phases of the phase-developed video signals. Since it is written to the display pixel at the same time,
If the deviations of the signal levels of the phase-developed video signals B21 to B24 of the first to fourth second-stage sample-and-hold circuits are different between the phases, the luminance variation for each dot in the horizontal direction on the display screen of the matrix type video display device 5 That is, a vertical streak fixed pattern is generated, and the display quality of the matrix type video display device 5 is degraded.

An object of the present invention is to provide a matrix-type image display device capable of improving the display quality of the image display device at a low cost and a driving method thereof.

[0030]

A matrix type video display device according to the present invention is a matrix type video display device including a phase expansion device and a plurality of display pixels, and divides a video signal into a plurality of video data. Video dividing means, first time changing means for changing a time order of the plurality of video data,
Output video forming means for forming a plurality of output video signals including the video data; and the video data of the video data included in the output video signal according to a time order changed by the first time changing means. Second time varying means for temporally changing the output, phase-developed video signal forming means for converting the output video signal into a phase-developed video signal, and writing means for writing the phase-developed video signal to the corresponding display pixel And third time changing means for changing the scanning direction of the video display of the matrix type video display device in time with the temporal change of the output of the video data included in the output video signal. It is.

Thus, the divided video data is stored in the first
The output of the video data included in the output video signal is temporally changed by the second time changing means in accordance with the time sequence of the video data changed by the first time changing means. The phase-expanded video signal is output by changing the scanning direction of the video display of the matrix-type video display device by the third time-varying means so as to match the video data temporally changed by the time-varying means. Is controlled, and as a result, the display quality of the matrix type video display device can be improved.

A driving method of a matrix type video display device according to the present invention is a matrix type video display device including a phase expansion device and a plurality of display pixels, wherein a video signal is divided into a plurality of video data. Dividing means, first time changing means for changing a time order of the plurality of video data,
Output video forming means for forming a plurality of output video signals including the video data; and the video data of the video data included in the output video signal according to a time order changed by the first time changing means. Second time varying means for temporally changing the output, phase-developed video signal forming means for converting the output video signal into a phase-developed video signal, and writing means for writing the phase-developed video signal to the corresponding display pixel And a third time varying means for temporally changing the scanning direction of the video display of the matrix type video display device in accordance with the temporal variation of the output of the video data included in the output video signal. A video signal is divided into a plurality of video data by using a video display device, and the time order of the plurality of video data is changed, and a plurality of outputs including the video data are changed. Forming a video signal, temporally changing the output of the video data included in the output video signal according to the time sequence of the video data, converting the output video signal into a phase-developed video signal, A video signal is written to the corresponding display pixel, and the scanning direction of the video display of the matrix type video display device is temporally changed in accordance with the temporal change of the output of the video data included in the output video signal. It is.

Thus, the scanning direction of the video display of the matrix type display device changes in accordance with the temporal change of the output of the video data included in the output video signal, so that the output of the video data included in the output video signal is performed. A deviation between phases of the signal level of the phase expanded video signal with respect to the level is suppressed. As a result, a vertical streak-shaped fixing pattern is suppressed.

[0034]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS.

The matrix type video display device according to one embodiment of the present invention comprises a video signal generator 1, a phase expansion section 2, a synchronization signal generator 3, a timing signal generator 4, and a matrix type video display device 5. .

The matrix type video display device 5 comprises a horizontal scanning circuit 6, a vertical scanning circuit 7, an analog switch 8, and a display pixel 9. The timing signal generator 4 is different from the conventional timing signal generator, and controls the first to fourth first-stage sample-hold circuits 11 to 14 every horizontal cycle. The configuration is such that the time sequence in which the control signals C11 to C14 of the circuit are generated is inverted, and the horizontal scanning direction control signal G is output to the matrix type video display device 5. Further, the horizontal scanning circuit 6 of the matrix type video display device 5 has a configuration in which the horizontal scanning direction is inverted by the horizontal scanning direction control signal G.

The phase developing section 2 has the same configuration as the conventional one, and includes first to fourth first-stage sample-hold circuits 11 to 14 and first to fourth second-stage sample-hold circuits 21 to 24.
And a two-stage configuration of each of the first-stage and second-stage sample-hold circuits is provided in parallel in the same number as the number of phases of the phase-developed video signal.

The video signal generator 1 and the phase developing unit 2 are connected by a video signal line 29, the synchronizing signal generator 3 and the timing signal generator 4 are connected by a synchronizing signal line 33, and The signal generator 4 includes first to fourth 1
The control signal line 321 of the stage sample hold circuit
To 324, the phase expansion unit 2 and the matrix type video display device 5 are connected by phase expansion video signal lines 311 to 314 of the first to fourth second-stage sample and hold circuits, and the timing signal generator 4 The matrix type video display device 5 is connected to a horizontal start signal line 34, a horizontal clock signal line 35, a horizontal scanning direction control signal line 39, a vertical start signal line 36, and a vertical clock signal line 37.

In the matrix type video display device 5, the horizontal scanning circuit 6 includes a horizontal start signal line 34, a horizontal clock signal line 35, and a horizontal scanning direction control signal line 39.
And the vertical scanning circuit 7 is connected to the vertical start signal line 36.
And the vertical clock signal line 37 are connected. The display pixel 9 and the vertical scanning circuit 7 are connected by a conducting wire 27, and the display pixel 9 and the analog switch 8 are connected by analog switch control signal lines 381 to 38m. Further, the analog switch 8 is connected to the phase expansion video signal line 311 of the first to fourth second-stage sample-hold circuits.
To 314 are connected.

In the phase developing section 2, the video signal line 29 and the control signal lines 321 to 321 of the first to fourth first-stage sample-hold circuits are respectively connected to the first to fourth first-stage sample-hold circuits 11 to 14. 324 are connected. The first to fourth first-stage sample-and-hold circuits 1
1st to 14th and first to fourth second-stage sample-hold circuits 2
1 to 24 are connected by output video signal lines 301 to 304 of the first to fourth first-stage sample and hold circuits, respectively. Further, the first to fourth second-stage sample / hold circuits 21 to 24 include a common control signal line 325 of the second-stage sample / hold circuit and a phase-developed video signal line 311 of the first to fourth second-stage sample / hold circuits. ~ 314
Is connected.

The high-resolution video signal A output from the video signal generator 1 is phase-expanded by the phase expansion unit 2 and the obtained four phases of the first to fourth second-stage sample-hold circuits are obtained. The expanded video signals B21 to B24 are input to the matrix type video display device 5. Then, the phase-developed video signals B21 to B24 of the first to fourth second-stage sample-hold circuits are simultaneously input, and are simultaneously written to the display pixels 9 which are continuous in four phases in the horizontal direction by the analog switch 8.

On the other hand, the output from the synchronization signal generator 3
The synchronization signal synchronized with the video signal A is input to the timing signal generator 4. The timing signal generator 4 controls the control signals C11 to C14 of the first to fourth first-stage sample / hold circuits and the common control signal C2 of the second-stage sample / hold circuit, which match the timing of the synchronization signal, and a matrix-type image. Horizontal scanning circuit 6 of display device 5
Start signal, horizontal clock signal and horizontal scanning direction control signal G for controlling horizontal scanning of
And a vertical start signal and a vertical clock signal for controlling the vertical scanning of the vertical scanning circuit 7 of the matrix type video display device 5.

The horizontal start signal and the vertical start signal are signals for determining the horizontal and vertical scanning start positions on the display screen of the matrix type video display device 5, respectively. The horizontal clock signal and the vertical clock signal are signals for performing horizontal scanning and vertical scanning of the matrix type video display device 5, respectively. Further, the horizontal scanning direction control signal G is a signal for switching the scanning direction of the horizontal scanning circuit 6.

In the phase developing section 2, the first to fourth first-stage sample-hold circuits 11 to 14 receive the video signal A and the control signals C11 to C14 of the first to fourth first-stage sample-hold circuits, respectively. Output video signals B11 to B11 of the first to fourth first-stage sample-hold circuits, respectively.
14 is output. The first to fourth second-stage sample-hold circuits 21 to 24 receive the output video signals B11 to B14 of the first to fourth first-stage sample-hold circuits and the common control signal C2 of the second-stage sample-hold circuit, respectively. , And outputs the phase-developed video signals B21 to B24 of the first to fourth second-stage sample-hold circuits.

Next, a method of phase expansion of the video signal A will be described with reference to FIG. The first and second horizontal periods U1 and U2 of the video signal A include a horizontal video period V and a horizontal blanking period W, respectively, as shown in FIG.

In the video signal A, n is the number of effective dots in the horizontal direction of the display screen of the matrix type video display device 5 and n is
Is a multiple of 4, and n pieces of video data from S1 to Sn are inserted. In the video signal A, the video data S1 is the first video data of the horizontal scanning in the non-interlaced scanning, and i is a natural number less than n.
i + 1 is the first horizontal cycle period that is temporally later and temporally adjacent to the video data Si and is temporally adjacent video data, and the video data Sn is the first video data of horizontal scanning in non-interlaced scanning, and The second horizontal cycle period in which the data Si is temporally later than the video data Si + 1 and is temporally adjacent video data is alternately repeated in each horizontal cycle.

The video signal A is supplied to the first to fourth first-stage sample-hold circuits 11 to 14 by the first to fourth first-stage sample-hold circuits 11 to 14, respectively.
Control signal C1 of the first stage sample and hold circuit
At the timing of 1 to C14, the first to the first shown in FIG.
Output video signal B1 of the fourth first-stage sample-hold circuit
1 to B14. At this time, the first to fourth 1
Output video signals B11 to B1 of the stage sample-hold circuit
4, k is a natural number less than or equal to n / 4, and S4
As shown in FIG. 2, video data represented by k-3, S4k-2, S4k-1, and S4k are inserted in a state where the order of the video data in the horizontal direction is inverted every horizontal cycle.

The output video signals B11 to B14 of the first to fourth first-stage sample-hold circuits are further supplied to the first
4 to the second-stage sample-hold circuits 21 to 24 at the timing of the common control signal C2 of the second-stage sample-hold circuits.
To the phase-developed video signals B21 to B24 of the fourth to second stage sample and hold circuits. As a result, the first to fourth
Phase expanded video signal B21 of the second stage sample and hold circuit
To B24 include video data S4k-3 and S4k, respectively.
-2, S4k-1 and S4k are all inserted at the same timing and with the order of the video data in the horizontal direction reversed every horizontal cycle.

By the above-described series of operations, the video signal A is converted into the first to fourth second-stage sample-hold circuits in which the order of the video data in the horizontal direction is inverted for each of the horizontal periods U1 and U2 as shown in FIG. Are converted into the phase development video signals B21 to B24.

Next, a method of writing the phase expanded video signals B21 to B24 of the first to fourth second-stage sample and hold circuits in the matrix type video display device 5 will be described.

The phase-developed video signals B21 to B24 of the first to fourth second-stage sample-and-hold circuits are input to the matrix type video display device 5 in parallel and continuous in the horizontal direction.
The same number of phases, that is, four display pixels are simultaneously written. In the horizontal scanning, m = n / 4, and the analog switch control signal Hk (k
Are natural numbers, 1 ≦ k ≦ m) in the order of starting from H1 and ending with Hm, by simultaneously turning on four analog switches 8 continuous in the horizontal direction as shown in FIG. In the second horizontal period U2, the analog switch control signals H1 to Hm start from Hm and end at H1, in the same manner as shown in FIG. At the same time, it is controlled by ON control.

Here, the order of the horizontal video data and the horizontal scanning direction are reversed every horizontal cycle while matching the order of the horizontal video data with the horizontal scanning direction.

That is, as indicated by the analog switch control signal Hk which is the ON control timing, the first
In both the horizontal cycle period U1 and the second horizontal cycle period U2, when the analog switch control signal Hk is at the ON control timing with respect to k, the phase expansion of the first to fourth second-stage sample-hold circuits is performed. Video signals B21 to B21
Each of the video data S4k-3 inserted into B24,
S4k-2, S4k-1 and S4k are (4k-3) th, (4k-2) th, and (4k-1) in the horizontal direction from the horizontal scanning start direction of the display screen of the video display device 5, respectively.
The 4th and 4kth display pixels 9 will be written. However, since the horizontal scanning direction is inverted every horizontal cycle, the horizontal scanning start direction is also inverted every horizontal cycle.

As a result, the video data Si of the video signal A
Is written to the display pixel 9 at the horizontal position of the matrix type video display device 5 that matches the timing of the video data Si, and the phase expansion of the first to fourth second-stage sample-hold circuits is performed in the same manner as in the related art. The highest frequency included in the video signals B21 to B24 is 1 / the number of phases of the highest frequency included in the video signal A.
Therefore, the number of phases is set so that the highest frequency included in the phase-developed video signals B21 to B24 of the first to fourth second-stage sample-hold circuits is equal to or lower than the highest writable frequency of the video signal of the video display device 5. Is set, writing of the video data of the video signal A to the matrix type video display device 5 is realized.

Further, as is clear from FIG. 2, the first to fourth first-stage sample-and-hold circuits 11 of the phase developing section 2
A time difference between the output video signals B11 to B14 of the first to fourth first-stage sample-hold circuits output from the first to fourth sample-hold circuits and the common control signal C2 of the second-stage sample-and-hold circuit is an arbitrary one horizontal cycle period Within the phase,
The sum of the above time differences within two adjacent horizontal periods is equal between the phases. That is, during a period that is very long compared to the horizontal period, the inter-phase deviation of the sum of the time differences is canceled out every two horizontal periods, and is suppressed to be equal to or less than the value of the time difference within one horizontal period. As a result, the generation level of the vertical streak fixed pattern is suppressed to a level that cannot be visually confirmed.

According to the above results, in the matrix type video display device 5, the video display having the resolution corresponding to the resolution of the video signal A and the normal display pattern by the high resolution video signal A is performed in the same manner as in the related art. Is performed, and the problem of display quality deterioration due to the vertical streak fixed pattern during image display, which was a conventional problem, is solved, so that a video display with higher display quality compared to the conventional method can be obtained. Can be.

The video signal in which the order of the video data is inverted for each horizontal cycle as described above is output from a processing circuit for an image compression signal such as an MPEG signal in a multimedia video device or the like. Can be easily obtained by using the video memory.

Although the present embodiment has been described on the assumption that the number n of effective horizontal dots of the matrix type video display device 5 is a multiple of the number of phases, even in a matrix type video display device where n is not a multiple of the number of phases. The same effect can be obtained by alternately changing the insertion timing of the video data of the video signal A in each horizontal cycle so as to match the structure of the video display device.

In this embodiment, the first horizontal period U
1 and the video data Si of the video signal A in the second horizontal period U2.
Are reversed, but the video data S of the video signal A is
The same effect can be obtained by appropriately changing the order of i and changing the time order of the control signals C11 to C14 of the first to fourth sample and hold circuits accordingly. What is the period for changing the order of the video data Si of the video signal A as long as it corresponds to the time order of the control signals C11 to C14 of the first to fourth first-stage sample and hold circuits? You may.

Furthermore, in the present embodiment, a four-phase expanded video signal is used. However, the same effect can be obtained by using a plurality of non-four phase expanded video signals. it can.

[0061]

As described above, according to the matrix-type image display device and the driving method of the present invention, it is possible to suppress the vertical stripe-shaped fixed pattern. As a result, the display quality of the matrix type video display device can be improved at low cost.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of a drive system of a matrix type video display device according to an embodiment of the present invention.

FIG. 2 is a diagram showing signal waveforms during operation of the matrix type video display device.

FIG. 3 is a diagram showing a configuration of a driving system of a conventional matrix type video display device.

FIG. 4 is a diagram showing signal waveforms during operation of the matrix type video display device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Video signal generator 2 Phase expansion part 3 Synchronous signal generator 4 Timing signal generator 5 Matrix type video display device 6 Horizontal scanning circuit 7 Vertical scanning circuit 8 Analog switch 9 Display pixel 11 1st 1st stage sample hold circuit 12 Second first-stage sample-hold circuit 13 Third third-stage sample-hold circuit 14 Fourth first-stage sample-hold circuit 21 First second-stage sample-hold circuit 22 Second second-stage sample-hold circuit 23 Third second-stage sample-hold circuit 24 Fourth second-stage sample-hold circuit 25 Timing signal generator 26 Horizontal scanning circuit 39 Horizontal scanning direction control signal line

Claims (2)

[Claims] 1. A matrix type video display device including a phase expansion device and a plurality of display pixels, wherein a video dividing means for dividing a video signal into a plurality of video data; First time changing means for changing;
Output video forming means for forming a plurality of output video signals including the video data; and the video data of the video data included in the output video signal according to a time order changed by the first time changing means. Second time varying means for temporally changing the output, phase-developed video signal forming means for converting the output video signal into a phase-developed video signal, and writing means for writing the phase-developed video signal to the corresponding display pixel And third time changing means for changing the scanning direction of the image display of the matrix type image display device with time in accordance with the time change of the output of the image data included in the output image signal. A matrix type image display device characterized by the above-mentioned. 2. A matrix-type image display device including a phase expansion device and a plurality of display pixels, wherein the image division means divides an image signal into a plurality of image data, and a time order of the plurality of image data is determined. First time changing means for changing;
Output video forming means for forming a plurality of output video signals including the video data; and the video data of the video data included in the output video signal according to a time order changed by the first time changing means. Second time varying means for temporally changing the output, phase-developed video signal forming means for converting the output video signal into a phase-developed video signal, and writing means for writing the phase-developed video signal to the corresponding display pixel And a third time varying means for temporally changing the scanning direction of the video display of the matrix type video display device in accordance with the temporal variation of the output of the video data included in the output video signal. A video signal is divided into a plurality of video data by using a video display device, and the time order of the plurality of video data is changed, and a plurality of outputs including the video data are changed. Forming a video signal, temporally changing the output of the video data included in the output video signal according to the time sequence of the video data, converting the output video signal into a phase-developed video signal, A video signal is written to the corresponding display pixel, and the scanning direction of the video display of the matrix type video display device is temporally changed in accordance with the temporal change of the output of the video data included in the output video signal. A method for driving a matrix type video display device, characterized by comprising the following: